Download as pdf or txt
Download as pdf or txt
You are on page 1of 11

Modeling of I-V characteristics in symmetric

double-gate polysilicon thin-film transistors


Cite as: AIP Advances 7, 065201 (2017); https://doi.org/10.1063/1.4985051
Submitted: 09 April 2017 • Accepted: 22 May 2017 • Published Online: 02 June 2017

Xiaoyu Ma, Songlin Chen, Wanling Deng, et al.

ARTICLES YOU MAY BE INTERESTED IN

A physics-based model of threshold voltage for amorphous oxide semiconductor thin-film


transistors
AIP Advances 6, 035025 (2016); https://doi.org/10.1063/1.4945410

An analytical drain current model for symmetric double-gate MOSFETs


AIP Advances 8, 045125 (2018); https://doi.org/10.1063/1.5024574

Surface potential calculation and drain current model for junctionless double-gate
polysilicon TFTs
AIP Advances 4, 087107 (2014); https://doi.org/10.1063/1.4892609

AIP Advances 7, 065201 (2017); https://doi.org/10.1063/1.4985051 7, 065201

© 2017 Author(s).
AIP ADVANCES 7, 065201 (2017)

Modeling of I-V characteristics in symmetric double-gate


polysilicon thin-film transistors
Xiaoyu Ma, Songlin Chen, Wanling Deng, and Junkai Huanga
Department of Electronic Engineering, Jinan University, Guangzhou 510630, China
(Received 9 April 2017; accepted 22 May 2017; published online 2 June 2017)

A new closed-form approximation for surface potential and drain current (DC) in
symmetric double-gate polysilicon thin-film transistors (DG poly-Si TFTs) is pro-
posed. The solution of the surface potential is single-piece and suitable for a wide
range of gate voltages under different conditions. A comparison with numerical results
shows that this scheme gives an accurate description of surface potential. The devel-
opment of surface-potential-based compact model for I-V characteristics is achieved
based on this calculation. Finally, the validity of the model is verified by compar-
isons with various experimental data. It is showing that the model is accurate over a
wide range of operation regions. © 2017 Author(s). All article content, except where
otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license
(http://creativecommons.org/licenses/by/4.0/). [http://dx.doi.org/10.1063/1.4985051]

I. INTRODUCTION
Among the state-of-the-art TFT technologies, polysilicon thin-film transistors (poly-Si TFTs)
have become increasingly important due to their low process temperature, high carrier mobility,
etc.1 However, with the decrease of channel length, the short-channel effects become more and
more obvious. The traditional single-gate devices are hard to meet the future needs of the integrated
circuit. The double-gate (DG) poly-Si TFT is a new kind of devices developed in recent years,
because it has better sub-threshold characteristics, lower leakage current and smaller short-channel
effects. Since the move to DG poly-Si TFTs in the emerging new electronic applications is urgently
needed, an accurate analytical TFT device models are available for circuit simulation have to be
developed.
In recent years, extensive work has been carried out in reproducing the current–voltage (I–V )
behaviors and the manufacturing process for DG poly-Si TFTs. For example, Akito Hara et al.2 fab-
ricated the DG poly-Si TFTs on a glass substrate using the back-exposure method. The experimental
results showed that the sub-threshold characteristics and the mobility of the devices were significantly
improved. The DG dual-channel poly-Si TFTs was realized by using the self-aligned process.3 It was
indicated that the leakage current and kink effect in the devices had effectively reduced. In terms of
solving the surface potential in DG poly-Si TFTs, the works4,5 used the regional approach; however,
the absolute errors of surface potential were relatively high. Ortiz-Conde et al.6 have reviewed and
developed the core compact models for undoped DG SOI MOSFETs. Although MOSFETs and TFTs
are counterparts, the high density of states (DOS) in polysilicon grain boundaries (GBs) should be
taken into account when modeling.
In this paper, we propose a compact DC models for symmetric DG poly-Si TFTs with the analyt-
ical solution of surface potential. Firstly, the relation between the surface potential and the potential
extremum at the center of film is derived by using the superposition method. After that, an explicit
surface potential calculation is obtained. Secondly, the I-V characteristics of the model based on
surface potential is developed by using the regional approximation and smooth functions. Finally,
the modeling results are compared with several numerical results and experimental measurements.

a
Correspondence to Professor Junkai Huang. Email: hjk196310@126.com, Phone: +86-20-85222727.

2158-3226/2017/7(6)/065201/10 7, 065201-1 © Author(s) 2017


065201-2 Ma et al. AIP Advances 7, 065201 (2017)

II. COMPUTATION OF SURFACE POTENTIAL


The structure diagram of ann-type symmetric DG poly-Si TFT is given in Fig. 1. The device has
a doped polysilicon film with the thickness of t poly , where x = ±t poly /2 and x = 0 correspond to the
interfaces and the film center, respectively. Herein, due to the symmetric TFT, it has two identical gates
with the same voltage bias and the same two gate oxide layers of equal materials and thicknesses(t ox ).
Following the gradual channel approximation and neglecting the hole concentration, the 1-D
Poisson’s equation of the device is acquired as follows
∂2 ϕ q ϕ − Vn ϕ − Vn
    
 q
= nfree + Nd + gta = n0 exp + Nd + Nta0 exp (1)
∂x 2 εsi εsi ϕt ϕg

where nfree is the free charge density; N d is the uniform doping concentration in the polysilicon film;
gta is the tail density of states; q is the electron charge; ε Si is the permittivity of polysilicon film; V n
is the channel potential; ϕt is the thermal voltage (kT /q); and ϕ is the electrostatic potential. To sim-
plify the description, we use the following denotation: N ta0 =gc1 ·[πkT ·sin(πkT /E 1 )]·exp[-E C /E 1 ], and
n0 = N d exp( 2V fp /ϕt ). In the above equations, V fp = ϕt ln(N d /ni ); ni is the intrinsic carrier concen-
tration; gc1 and E 1 are the density and the inverse slope of acceptor-like tail states at the bottom of
conduction band (E C ), respectively.
The boundary conditions of Eq. (1) can be described as
∂ϕ

= 0, ϕ(0) = ϕ0 (2)
∂x x=0
where ϕ0 is the potential extremum at the center of the polysilicon film (x = 0).
Using the relation of and the above boundary conditions, the channel electric field is obtained as
1/2
ϕ − Vn ϕ0 − Vn
    
s  ϕ

 N exp − exp 
 ta0 g ϕg ϕg
 
2q 
 
E(ϕ, Vn ) =


(3)
εsi  ϕ − Vn ϕ0 − Vn
    
ϕ ϕ
 
+n
 0 t exp − exp + Nd (ϕ − )
0 

ϕt ϕt
 
 
where ϕg =E 1 /q.
Using Gauss’law at the interface, the relation between ϕs and V gs can be determined by
εsi
Vgs − Vfb − ϕs = E(ϕs , Vn ) (4)
Cox
where V gs is the gate-to-source voltage; V fb is the flat-band voltage; and C ox is the gate oxide capacitor
per unit area.

FIG. 1. Cross-sectional view of a symmetric DG poly-Si TFT.


065201-3 Ma et al. AIP Advances 7, 065201 (2017)

The search for an approximate closed-form solution begins with an asymptotic solution of (1)–(4)
under different mathematical conditions. We split the potential ϕ(x) into four components: the center
potential ϕ0 , the potentials ϕ1 (x), ϕ2 (x) and ϕ3 (x), which are contributed by the trapped charges, the
mobile charges, and the doping concentration, respectively. These potentials are all taking ϕ0 as a
reference. Therefore, we have
ϕ(x) = ϕ0 + ϕ1 (x) + ϕ2 (x) + ϕ3 (x) . (5)
The approximations for ϕ1 (x), ϕ2 (x) and ϕ3 (x) can be obtained by solving the following asymp-
totic equations
 ∂ ϕ1 = q N exp ϕ1 − Vn
2
  

ta0
εsi ϕg

 ∂x 2




 ∂ 2 ϕ2

 q
 
ϕ2 − Vn

= n0 exp (6)


 ∂x 2 εsi ϕt
∂ 2 ϕ3

 q
= Nd



 ∂x 2 εsi

with the boundary conditions
∂ϕi (x)

 εsi =0



∂x x=0

(7)
 ϕi (x)| = 0


 x=0
where i=1,2,3. The asymptotic solutions are7
( "s  #)
ϕ

 N ta0 q 0 − V n
 ϕ1(x) = −2ϕg ln cos

exp x

2εsi ϕg



 2ϕg

ϕ0 − Vn
  r   
n0 q


ϕ (x) = −2ϕ ln cos exp x . (8)
2 t



 2ε si ϕt 2ϕ t
qx 2


 ϕ3(x) =

Nd


 2εsi
As a result, a crude initial approximation to the surface potential can be given by combing Eq. (5)
with (8), i.e.,
    
kg(ϕ0 − Vn )

tpoly
ϕs = ϕ = ϕ0 − 2ϕg ln cos kNta0 exp
2 2ϕg
    (9)
kt (ϕ0 − Vn )
− 2ϕt ln cos kNde exp + kNd
2ϕt
r r
2
Nta0 qtpoly 2
n0 qtpoly 2
qtpoly
where kNta0 = 8ϕg εsi , kNde = 8ϕt εsi , and kNd = 8εsi Nd . Nevertheless, when combining Eqs. (5)
and (8), the result of potential is not accurate enough, because it cannot reflect the influence of the
decrease of ϕ0 . In addition, due to the trapped charge, the surface potential and center potential are
less than those in DG MOSEFTS at the same V gs . Equations (5) and (8) cannot reflect the impact of
the reduced of ϕ0 . Also, the numerical tests show that ϕs in Eqs. (5) and (8) is less than numerical
result when substituting the numerical solution of ϕ0 . To obtain a more accurate solution, a small
refinement should be carried out. Therefore, we add two adjusting parameters (i.e., k t and k g ) into
(9) to correct the decrease of the center potential.
In order to determine k t and k g , two groups of data must be obtained first: (V gf max ,ϕs max ,ϕ0 max )
and (V gf turn ,ϕs turn ,ϕ0 turn ), where ϕs max and ϕ0 max are the surface potential and the center potential
respectively when V gf (i.e.,V gf =V gs V fb ) approaches to its maximum; ϕs turn and ϕ0 turn are also
the surface potential and center potential when V gf in the transition region, respectively. Through our
experiments, V gf turn can be arbitrarily selected in a wide range from 1V to 3V. The first group of
data is used to calculate k t in the strong inversion region, and the latter is employed to compute k g in
the transition region. Both groups of data are solved numerically. The procedure of our algorithm is
then divided into the following three steps:
065201-4 Ma et al. AIP Advances 7, 065201 (2017)

1) The calculation of k t .
We assume the initial value of k g is about 0.9, which is an empirical value. Substituting k g , ϕs max
and ϕ0 max into Eq. (9), k t is given by
2ϕt ln[arccos(kt 1 )/kNde ]
kt = (10)
ϕ0 max − Vn
 
ϕs max − [ϕ0 max −2ϕg ln(cos(kNta0 exp(kg (ϕ0 max −Vn )/(2ϕg ))))+kNd ]
Where kt 1 = exp −2ϕt .

2) The calculation of k g .
Substituting k t , ϕs turn and ϕ0
into Eq. (9), k g is calculated as follows
turn
  
2ϕg ln arccos kg 1 /kNta0
kg = (11)
ϕ0 turn − Vn
ϕ
n o
−[ϕ −2ϕ ln(cos(kNde exp(kt (ϕ0 turn −Vn )/(2ϕt ))))+kNd ]
Where kg 1 = exp s turn 0 turn t −2ϕg .

3) Repeating steps 1 and 2 to make the results of k t and k g more accurate.


Generally, steps 1 to 3 are calculated twice to further refine the result of k t and k g . It should
be noted that the combination of Eqs. (4) and (9) permits an accurate calculation of ϕ0 in terms of
V gf and V n . However, using the numerical calculation is time-consuming. It is necessary to further
simplify the calculations. Here, we try to model ϕ0 without numerical iterations by using8
q
φ0 a = U − U 2 − Vgf · ϕ0 max (12)
1
U=

Vgf +(1 + r)ϕ0 max . (13)
2
Substituting ϕ0 turn and V gf turn into Eqs. (12) and (13), r is given by
2u1 − Vgf turn − ϕ0 max
r= (14)
ϕ0 max
where u1 = (ϕ02 turn +V gf turn ϕ0 max )/(2ϕ0 turn ).
It is worth noting that although ϕ0 is modeled by using Eqs. (12) and (13), a high precision of ϕ0
is better for the compact modeling development. As a consequence, we use the Newton’s midpoint
method to improve its accuracy which are shown as Eqs. (15) and (16),
f (ϕ0 k )
zk+1 = ϕ0 k − 0 (15)
f (ϕ0 k )
f (ϕ0 k )
ϕ0 k+1 = ϕ0 k − 0 (16)
f (0.5ϕ0 k + 0.5zk+1 )
Here, f (ϕ0 ) is the function of ϕ0 determined by combining Eqs. (4) and (9); f 0(ϕ0 ) is the first derivative
of f (ϕ0 ); ϕ0 k is the corrected center potential. Eq. (12) is chosen as the initial value. The absolute
value of f (ϕ0 k +1 ) is calculated after each iteration. When its value is less than 10-4 V, the correction
is completed. Because the accuracy of the center potential and the number of iterations can meet the
requirements. If the values is greater than 10-4 V, the iteration continues. Through our experiments,
the number of iterations at each point is less than four. After using Newton’s midpoint method to
complete the correction of ϕ0 , we can get the final surface potential by substituting the results into
Eq. (9).With the above scheme, the complete solution of the physics-based surface potential with the
high precise can be obtained.

III. I–V CHARACTERISTICS MODEL


According to the Pao-Sah integral, we obtain the drain current as6

W Vds
Ids = −µeff Qi dVn (17)
L 0
065201-5 Ma et al. AIP Advances 7, 065201 (2017)

where µeff is the effective mobility; W is the channel width; L is the channel length; V ds is
the drain-source voltage; and Qi is the is the mobile charge density, which can be expressed as
ϕ
Qi = −2q ∫ϕ0s n0 exp [(ϕ − Vn )/ϕt ]/E(ϕ, Vn )dϕ.
In the sub-threshold region, since the most of the Qi is trapped in the sub-gap, the influence of
the mobile charge can be ignored. Then, the Pao-Sah integral can be simplified as the charge-sheet
approximation, i.e.,
 ϕsL 
W
Isub = −µeff Qi dϕs − ϕt (QiL − Qi0 ) (18)
L ϕs0

where ϕsL and ϕs0 are the surface potentials in source and drain ends, respectively; Qi0 and QiL are
the mobile charge densities at the source and drain ends, respectively.
The integral term in Eq. (18) can be approximated by
 ϕsL
Qi dϕs ≈ Qi0(ϕsL − ϕs0 ) . (19)
ϕs0

For further simplification, Qi is approximated by

Qi = a Vgf − ϕs

(20)

where a = Qi0 /(V gf ϕs ). Substituting Eq. (20) into (18), the sub-threshold drain current (I sub ) can be
expressed as
W ha i
Isub = µeff (ϕs0 − ϕsL ) ϕs0 + ϕsL − 2Vgf + ϕt (QiL − Qi0 ) .

(21)
L 2
With V gf increasing, the TFTs enter into the strong inversion region. In this case, all the induced
charges are the free charge. It is implies that the behavior of DG poly-Si TFTs in the strong inversion
is similar to that of crystalline MOSFETs. Extending the current formulation of symmetric DG
MOSFETs, we get the following drain current 5 for DG poly-Si TFTs in strong inversion:

Wh   i
Istr = µeff 2Cox Vgf (ϕsL − ϕs0 ) − Cox ϕsL
2
− ϕs0
2
+ 4ϕt Cox (ϕsL − ϕs0 ) . (22)
L
The effective mobility is given as follows5
 
−Vb
µh exp ϕt
µeff = µs + (23)
1 + θ 1 Vgf + θ 2 Vgf2

h 2  2 i 1/2
Vb = Vgf − Vi + VQ − κVds

− Vgf − Vi (24)

where µs is the low gate bias mobility; θ 1 and θ 2 are mobility degradation parameters; and κ, V Q , V i ,
and µh are the fitting parameters.
To avoid solving the equation set, a smooth transition from the linear to saturation regions can
be modeled by the following smoothing function:
n  p o 1/p
Vdse = Vds / 1 + Vds / αVgf (25)

where p controls the transition from V ds to saturation voltage;α is an adjustable parameter which
reduces with deceasing L.
The total drain current is given by9
Isub × Istr
Ids =  m (26)
1/m 1/m
1/Isub + 1/Istr
065201-6 Ma et al. AIP Advances 7, 065201 (2017)

where m is used to adjust the transition of I ds from the sub-threshold region to the strong inversion
region.

IV. RESULTS AND DISCUSSIONS


In order to verify the accuracy and effectiveness of the solution of surface potential in DG poly-Si
TFTs, the algorithm of surface potential was carried out by using the Matlab software under different
conditions.
As shown in Fig. 2, the validity of solution is verified by comparing with the numerical results
by solving Poisson’s equation directly. It is clear that, ϕ0 and ϕs vary linearly with the gate voltage
in the sub-threshold region and saturate gradually in the strong inversion region. With gc1 increases,
ϕs rises much less sharply in the sub-threshold region, and ϕ0 is reduced in all operational region
attributed to the higher density of trap states. Excellent accuracy is achieved over a wide range of
bias condition and device parameters. Fig. 3 shows the absolute error between simulation results and
numerical results. It can be seen from Fig. 3 (a) that the maximum absolute error is only in 10-4 V
range. It indicates that the proposed solution is useful to describe surface potential characteristics.
Fig. 3 (b) shows the absolute error under different V gf turn . It can be seen that the choice of V gf turn
have no significant effect on the absolute error of its surface potential. However, it only has a little
effect on the linear region. The relation between ϕs and V gf in different V n is also given in Fig. 4.

FIG. 2. ϕ 0 and ϕ s versus V gf with different gc1 .

FIG. 3. Absolute errors between the proposed surface potential solution and numerical results with (a) different Nd. and (b)
different Vgf turn .
065201-7 Ma et al. AIP Advances 7, 065201 (2017)

FIG. 4. ϕ s versus V gf for different channel potentials V n .

FIG. 5. ϕ 0 and ϕ s versus Vgf with different kt and kg.

FIG. 6. Absolute errors between numerical results and the proposed surface potential solution under different kt and kg .
065201-8 Ma et al. AIP Advances 7, 065201 (2017)

FIG. 7. Comparisons between the proposed model and experimental results10 of short-channel devices with (a) transfer and
(b) output characteristics.

FIG. 8. Comparisons between the proposed model and experimental results3 of long-channel devices with output character-
istics.

FIG. 9. Comparisons between the proposed model and experimental results of long-channel devices with transfer character-
istics.

The solution of surface potential is smoothly connected in all the working regions. Fig. 5 shows ϕ0
and ϕs versus Vgf with different kt and kg. We can see that the initial values of kt and kg lead to
bigger absolute errors of the center potential in the strong inversion region. But the impact of surface
065201-9 Ma et al. AIP Advances 7, 065201 (2017)

TABLE I. Parameters for simulations.

Symbols (units) Values in Fig. 7 Values in Fig. 8 Values in Fig. 9

N d (cm-3 ) 1×1013 1×1014 1×1012


W (µm) 1 10 1
L(µm) 1 10 10
t poly (nm) 100 50 50
t ox (nm) 100 200 90
C ox (F/cm2 ) 3.51×10-8 3.51×10-8 3.51×10-8
gc1 (cm-3 eV-1 ) 1×1018 1×1019 1×1018
E 1 (eV) 0.08 0.07 0.06
V fb (V) -2.6 0 -2
µs (cm2 V-1 s-1 ) 50 1 10
µh (cm2 V-1 s-1 ) 1450 310 1060
θ1 0.22 4×10-3 1.3×10-2
θ2 0.0117 6×10-3 1×10-2
V Q (V) 0.3 1 0.2
V i (V) 0 0.05 2.6
κ 0.01 0 0.2
m 0.05 0.05 0.05

potential is not obvious. Therefore, Fig. 6 shows the absolute errors between numerical results and
the proposed surface potential solution under various kt and kg. It can be used to compare the surface
potential absolute error between the two different values of kt and kg. Consequently, it can be seen
that the accuracy of surface potential has been significantly improved with the corrected kt and kg.
To verify our drain current model, we compared the model with experimental data from short to
long channel devices, as shown in Figs. 7 to 9. The simulation parameters are given in Table I, which
can be extracted through the common routine of the parameter extractions.12
For the short-channel devices, as shown in Fig. 7, the proposed model reproduces the measured
results of I-V characteristics10 in a wide range of operation regions. The I-V curves obtained from the
model match well with the measurements. For the long-channel devices, as shown in Figs. 8 and 9,
the derived model is employed by a comparison with experimental data.11 As we can see that, the
proposed model is fairly good at predicting drain current of long-channel devices in both transfer
and output characteristics. In addition, the drain current keeps flat after saturation because the short
channel effects are reduced.

V. CONCLUSION
In this paper, a compact drain current model based on surface potential for symmetric DG poly-Si
TFTs is presented. The proposed closed-form approximation of surface potential is single-piece and
smooth with the maximum absolute error is only in 10-4 V range. The drain current model is derived
from the Pao-Sah model, which covers from sub-threshold to above-threshold regions. Comparisons
of the model with different experimental results verified that our model is capable of accurately
predicting the drain current characteristics in symmetric DG poly-Si TFTs. This modeling is not only
essential for the design and simulation of complete TFT circuits but it also allows predicting the
influence of TFT parameters.

ACKNOWLEDGMENTS
This work was supported by the Guangdong Natural Science Foundation under Grant
2014A030313366.
1 J. Kim, H. Oh, J. Lee, C. K. Baek, M. Meyyappan, and J. S. Lee, Semiconductor Science and Technology 30, 675 (2015).
2 H. Akito, T. Sato, K. Kondo, K. Hirose, and K. Kitahara, Japanese Journal of Appl. Phys. 50, 021401 (2011).
3 F. T. Chien, C. W. Chen, T. C. Lee, C. L. Wang, C. H. Cheng, T. K. Kang, and H. C. Chiu, IEEE Transactions on Electron

Devices 60, 799 (2013).


4 W. Deng, X. Ma, and J. Huang, AIP Advances 4, 087107 (2014).
5 J. Huang, W. Deng, X. Zheng, and X. Jiang, IEEE Transactions on Electron Devices 57, 2607 (2010).
065201-10 Ma et al. AIP Advances 7, 065201 (2017)

6 A. Ortiz-Conde, F. J. Garcı́a-Sánchez, J. Muci, S. Malobabic, and J. J. Liou, IEEE Trans Electron Devices 54, 131 (2007).
7 Y. Taur, IEEE Electron Device Lett. 21, 245 (2000).
8 A. Ortiz-Conde, F. J. Garcı́a-Sánchez, and S. Malobabic, IEEE Trans. Electron Devices 25, 1669 (2005).
9 A. Tsormpatzoglou, N. A. Hastas, N. Choi, F. Mahmoudabadi, M. K. Hatails, and C. A. Dimitriadis, J. Appl. Phys. 114,

184502 (2013).
10 C. C. Tsai, K. F. Wei, Y. J. Lee, H. C. Cheng, J. L. Wang, I. C. Lee, and H. C. Cheng, IEEE Electron Device Letters 28, 11

(2007).
11 S. Yusuke, B. Takuro, O. Yasunori, O. Hiroyuki, K. Shinya, K. Kuniroti, and H. Akito, Japanese Journal of Applied Physics

52, 03BB01 (2013).


12 N. Arora, MOSFET Models for VLSI Circuit Simulation: Theory and Practice, 1st ed. (Springer-Verlag, Shrewsbury,

New York, 1993).

You might also like