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An analytical drain current model for引用量5 很新的文章
An analytical drain current model for引用量5 很新的文章
An analytical drain current model for引用量5 很新的文章
Surface potential calculation and drain current model for junctionless double-gate
polysilicon TFTs
AIP Advances 4, 087107 (2014); https://doi.org/10.1063/1.4892609
A two-dimensional model for the potential distribution and threshold voltage of short-
channel double-gate metal-oxide-semiconductor field-effect transistors with a vertical
Gaussian-like doping profile
Journal of Applied Physics 108, 034518 (2010); https://doi.org/10.1063/1.3460796
© 2018 Author(s).
AIP ADVANCES 8, 045125 (2018)
I. INTRODUCTION
Silicon ICs have the strong demand for increasing dense so that the feature size of devices
shrinks into the nanometer scale. Simultaneously, the further scaling leads to hard limits1 for the
device performance improvement due to the short channel effects (SCEs). Recently, the multiple-
gate (MG) MOSFETs,2,3 such as double-, Π-, Ω-, surrounding-, quadruple-gate MOSFETs, etc.,
have become as the promising candidates for the classical MOSFETs to overcome the scaling limits.
Therefore, it is necessary to develop a drain current compact model of symmetric double-gate (sDG)
MOSFETs, in order to better exploit sDG MOSFET circuit design and simulation.
Besides of physical and computational accuracy, it is imperative that a practical model must
be continuous,4 simple,5 and convergent,6 in all operational regions. There are some sDG transistor
models reported in the literatures,7–17 but most models,8–11 including those reviewed by Ortiz-Conde
et al.,7 are either suitable for the undoped device or based on the regional approach.12 In addition,
the physics-based 2-D model proposed by A. Sehgal et al.13 is complicated and unfitted for cir-
cuit simulators. Our previous works14 suitable for simulating sDG polysilicon thin-film transistors
cannot be directly applied into the sDG MOSFETs without any adjustment. T. K. Chiang et al.15
developed an analytical threshold voltage model for the sDG MOSFETs which can be applied to
circuit simulation due to its computational efficiency, but the drain current model is still required in
the circuit simulation. S.–C. Lo et al.16 solved the nonlinear Poisson equation for sDG metal-oxide-
semiconductor transistors to get the explicit solution of the surface potential, but they also used the
regional approach leading to the absence of the physical meaning and decrease of the computational
accuracy in the transition between the different operational regions. J. He et al.17 developed a con-
tinuous channel potential solution from the accumulation to the strong inversion region for the sDG
MOSFETs, but this model is not suitable for the short-channel devices. Based on the above literatures,
we can observe that the improvement rooms are left for accuracy, simplicity, and continuity without
a
Corresponding author e-mail: yufei jnu@126.com
smoothing functions, especially in the transition between the different regions of the short-channel
sDG MOSFETs.
In this paper, we give solutions of the surface and central potential in a closed form without
any smoothing functions, which are continuous from accumulation, subthreshold, to strong inversion
regions. Furthermore, we formulate the drain current expression by using the charge sheet model18 for
the sDG MOSFETs. Finally, we give the important attention on the high accuracy and fast convergence
of such a sDG MOSFET model, which is verified by the least square method results, Silvaco Atlas
simulation results, and experimental data.
Furthermore, according to Gauss’ law, we can obtain the first coupling equation between ϕs and ϕo ,
i.e.,
−Vch
2 2qVt ni2 e Vt ϕs ϕs − ϕo
!
ϕo
−ϕs −ϕ o
Cox Vgs − Vfb − ϕs =
2
e t − e t + Na
V V − Na e t − e t , (3)
V V
ε si Na
Vt
where C ox is the gate capacitance per unit area, Vgs is the gate-to-source voltage, and Vfb is the
flat-band voltage.
In (3), there are two unknown variables ϕs and ϕo . Therefore, we need look for another equation
between ϕs and ϕo to derive a solution. According to (1), the electrostatic potential ϕ at the arbitrary
position along the x axis in the channel can be expressed by integrating (1) twice, i.e.,
x v
q ni2 ϕ − Vch
! !
−ϕ
ϕ − ϕo = exp + Na − Na exp dudv, (4)
ε si Na Vt Vt
0 0
where u and v are integral intermediate variables. Considering (dϕ/dx)x =0 = 0, we can reformulate
(4) and get another equation between ϕs and ϕo as
ϕo Na tsi 2
" ! ! #
q −ϕo
ϕs − ϕo = η s exp + ρs exp + . (5)
ε si Vt Vt 8
Here, .
tsi
2v
ni2 e−Vch /Vt ϕs − ϕo
!
ηs = exp dudv, (6)
Na Vt
0 0
.
tsi
2v
ϕs − ϕo
!
ρs = −Na exp − dudv. (7)
Vt
0 0
In order to solve (6) and (7), we assume the difference between the surface potential and the central
potential as a constant:
q Na tsi 2
ϕs − ϕo = . (8)
ε si 2 2
It is noted that (8) can be derived directly from the simplified 1-D Poisson’s equation valid in the
subthreshold region. Substituting (6)–(8) into the right hand side of (5), the second coupling equation
between ϕs and ϕo can be obtained as
ϕo
! !
−ϕo
ϕs − ϕo = a · exp + b · exp + c. (9)
Vt Vt
qNa t 2
!
si Vch qNa t 2
2 2
q tsi ni − − si qNa t 2
where a = , b = − qN , and c = 8εsisi .
8εsi Vt Vt a
εsi 8Na e εsi e
8εsi Vt
Now, we can solve the surface potential and the central potential from the combination between
(3) and (9) by using the Newton iterative method,19 which leads to the fast convergences. It is
interesting that (9) is analogous as the approximation20 derived by J. M. Sallese et al. The distinction
is that the derivation of the initial guess difference between ϕs and ϕo is based on device physics
in this paper, rather than that the electrostatic potential ϕ is defined as a local approximation,21
i.e., ϕ=ϕo , in the coarse finite difference method.20
Furthermore, based on the solutions of ϕs and ϕo , we derive the threshold voltage Vth , which is
defined as the gate-to-source voltage on the condition that the free charge density is equated with the
twice time doping concentration in the 1-D Poisson’s equation. Combining with the 1-D Poisson’s
equation and Gauss’ law, and considering the condition of Boltzmann’s distribution, we can derive
Vth as
2N 2 qNa tsi tox
Vth = Vfb + Vt ln* 2a + + + 3Vt . (10)
, ni - ε ox
045125-4 Yu et al. AIP Advances 8, 045125 (2018)
FIG. 2. Comparisons between our electrostatic potential model and the least square method at the source terminal.
It is interesting that there is a little influence on Vth from both t si and t ox because of the sub-nanometer
scale dimensions in sDG MOSFETs.
FIG. 3. Errors between our electrostatic potential model and the least square method at the source terminal.
045125-5 Yu et al. AIP Advances 8, 045125 (2018)
FIG. 4. Comparisons between electrostatic potential model and the least square method for the different Vch .
FIG. 5. Comparisons between our electrostatic potential model and the least square method for the different t si .
FIG. 7. Comparisons between our electrostatic potential model and the least square method for the different t ox .
FIG. 9. Comparisons between our electrostatic potential model and the least square method for the different Na .
045125-7 Yu et al. AIP Advances 8, 045125 (2018)
According to Figs. 5–8, we can observe that the effects from t si and t ox on ϕs and ϕo . On the one
side, in Figs. 5 and 6, t si has a little influence on ϕs and Vth . However, the absolute results of ϕo in
both accumulation and strong inversion regions increase as t si decreases. On the other side, in Figs. 7
and 8, t ox has a little influence on ϕo and Vth , but the absolute results of ϕs in both accumulation and
strong inversion regions increase as t ox decreases.
Furthermore, we can see in Figs. 9 and 10 that N a affects ϕs , ϕo , and Vth , simultaneously. All of
them are show positive correlation with N a . However, N a has a little effect on the difference between
ϕs and ϕo .
ϕsd
W
Ids diff =µ dQi (ϕs ). (13)
L
ϕss
Here, ϕss and ϕsd are the solutions of ϕs at the source and drain terminals, corresponding to
Vch =0V and Vch = Vds , respectively. Vds is the drain-to-source voltage, µ is the charge mobility,
W is the channel width, and L is the channel length. Qi (ϕs ) is the free charge density per unit gate
area in the channel, that is obtained from the Gauss’ law as
Qi (ϕs ) = −Cox Vgs − Vfb − ϕs − Qa (14)
where Qa is the doping charge per unit gate area in the channel film in the case of full-depletion,
leading to
045125-8 Yu et al. AIP Advances 8, 045125 (2018)
FIG. 11. Comparisons of output characteristics between our drain current model (solid lines) and Atlas simulation (symbols).
tsi
Qb = −qNa
. (15)
2
Substituting (12)–(15) into (11), the drain current I ds is analytically derived as
" ! # ϕss
W qNa tsi
Ids = µCox −ϕ2s + 2 Vgs − Vfb − + Vt ϕs . (16)
L 2Cox ϕsd
It should be pointed that (16) derived from the charge sheet model is in close-form without any
smoothing functions and in continuity without any fitting parameters, because ϕs and ϕo are also
in both close-form and continuity for all the operational regions from the accumulation to strong
inversion regions of the sDG MOSFETs.
FIG. 12. Comparisons of transfer characteristics between our drain current model (solid lines) and Atlas simulation (symbols).
045125-9 Yu et al. AIP Advances 8, 045125 (2018)
FIG. 13. Comparisons of output characteristics between our drain current model (solid lines) and Atlas simulation (symbols).
FIG. 14. Comparisons of transfer characteristics between our drain current model (solid lines) and Atlas simulation (symbols).
FIG. 15. Comparisons of output characteristics between our drain current model (solid lines) and Atlas simulation (symbols).
045125-10 Yu et al. AIP Advances 8, 045125 (2018)
FIG. 16. Comparisons of transfer characteristics between our drain current model (solid lines) and Atlas simulation
(symbols).
the accurate matches are obtained not only in the subthreshold region but also in the strong inversion
region.
Secondly, for the short channel sDG MOSFETs, the short channel effects are prominent, as
shown in Figs. 15 and 16, especially in the strong inversion region due to the pinch-off behavior in
the channel. As such, we take the pinch-off behavior into account by adopting the effective drain-to–
source voltage approach.12 In practice, we substitute the effective drain-to–source voltage Vdseff for
Vch in (3) and (9) to make our model include the pinch-off behavior, i.e.,
Vds
Vdseff = q . (17)
β β
1 + (Vds /Vdsat )
Here, the parameter β governs the transition from Vds to Vdseff , and Vdsat is an extracted saturation
voltage parameter.
Finally, considering the practical validation comes from a comparison with experimental results
of the sDG MOSFETs. we added the comparison between our model with the experimental results,24
as shown in Figs. 17 and 18. We can observe that our model can be used to simulate the I-V
characteristics of the sDG MOSFETs coming into sub-nanometer scale.
FIG. 17. Comparisons of output characteristics between our drain current model (solid lines) and experimental results24
(symbols).
045125-11 Yu et al. AIP Advances 8, 045125 (2018)
FIG. 18. Comparisons of transfer characteristics between our drain current model (solid lines) and experimental results24
(symbols).
IV. CONCLUSION
In this paper, we have derived an analytical drain current model for symmetric double-gate
MOSFETs. Such a model starts from the fast derivation of the surface and central potentials. In
particularly, the solutions of the surface and central potentials are continuous without any smoothing
functions from the accumulation to strong inversion regions. Then, we verify the electrostatic potential
model with the results in the least square method. Furthermore, we use the surface potential results
to calculate directly the drain current based on the charge sheet model. Finally, we validate the drain
current model by using Silvaco Atlas simulation results and experimental data, and obtain the good
agreements over a wide range of bias voltages and channel lengths. As a result, this model is suitable
to be adopted as a useful tool implemented into a circuit simulator.
ACKNOWLEDGMENTS
This work was funded partially by the Scientific Research Funds of Huaqiao University under
grant 600005-Z16X0114 and partially by the Scientific Research Funds for the Young Teachers of
Fujian Province under grant JAT170034.
1 ITRS — International Technology Roadmap for Semiconductor, 2009.
2 I. Ferain, C. A. Colinge, and J.-P. Colinge, Nature 479, 310 (2011).
3 ITRS — International Technology Roadmap for Semiconductor, 2014.
4 Y. Taur, X. Liang, W. Wang, and H. Lu, IEEE Electron Device Lett. 25, 107 (2004).
5 N. Arora, “MOSFET models for VLSI circuit simulation: Theory and practice,” Shrewsbury, 1st ed. (Springer-Verlag,