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Mcq's On Embedded Systems
Mcq's On Embedded Systems
Mcq's On Embedded Systems
Sno 1
Name SECTION-1
Time 120
Mark 1
Negative 0
Questions – S1
Qno 1
Sno 1
Type Mcq
A Operating system
B Software
C Hardware
Answer D
Topic Chapter-1
Mark 1
Level 1
Qno 2
Type Mcq
A a,b,c
B b,c,d
C a,b,d
D a,b,c,d
Answer C
Topic Chapter-1
Mark 1
Level 1
Qno 3
Sno 3
Type Mcq
A System of components
B Silicon on chip
C Silicon on circuit
D System on chip
Answer D
Topic Chapter-1
Mark 1
Level 1
Qno 4
Sno 1
Type Mcq
D Peripheral controller
Answer A
Topic Chapter-1
Mark 1
Level 1
Qno 5
Sno 1
Type Mcq
Answer B
Topic Chapter-1
Mark 1
Level 1
Qno 6
Sno 1
Type Mcq
A Sensors
B Actuators
C CPU
D ADC
Answer A
Topic Chapter-1
Mark 1
Level 1
Qno 7
Sno 1
Type Mcq
A Sophisticated functionality
B Restricted memory
Answer D
Topic Chapter-1
Mark 1
Level 1
Qno 8
Sno 1
Type Mcq
Answer C
Topic Chapter-1
Mark 1
Level 1
Qno 9
Sno 1
Type Mcq
A 6
B 7
C 8
D 11
Answer C
Topic Chapter-1
Mark 1
Level 1
Qno 10
Sno 1
Type Mcq
A Baseline
B Midrange
C Enhanced midrange
D High end
Answer D
Topic Chapter-1
Mark 1
Level 1
Qno 11
Sno 1
Type Mcq
A 33
B 35
C 49
D 83
Answer B
Topic Chapter-1
Mark 1
Level 2
Qno 12
Sno 1
Type Mcq
A 33
B 35
C 49
D 83
Answer D
Topic Chapter-1
Mark 1
Level 2
Qno 13
Sno 1
Type Mcq
Answer C
Topic Chapter-1
Mark 1
Level 2
Qno 14
Sno 1
Type Mcq
A 2MIPS
B 5MIPS
C 8MIPS
D 10MIPS
Answer B
Topic Chapter-1
Mark 1
Level 2
Qno 15
Sno 1
Type Mcq
A Baseline
B Midrange
C Enhanced Midrange
D High end
Answer C
Topic Chapter-1
Mark 1
Level 2
Qno 16
Sno 1
Type Mcq
A 1MHz
B 2MHz
C 1GHz
D 2GHz
Answer D
Topic Chapter-1
Mark 1
Level 2
Qno 17
Sno 1
Type Mcq
Answer A
Topic Chapter-1
Mark 1
Level 2
Qno 18
Sno 1
Type Mcq
A Aux system
B User interface
C Money
D Sensor
Answer B
Topic Chapter-1
Mark 1
Level 2
Qno 19
data and code lie in different memory blocks, then the architecture is
Question
referred as
Sno 1
Type Mcq
A CISC architecture
B RISC architecture
D Harvard architecture
Answer D
Topic Chapter-1
Mark 1
Level 2
Qno 20
Sno 1
Type Mcq
A 8
B 14
C 28
D 40
Answer B
Topic Chapter-1
Mark 1
Level 2
Qno 21
Sno 1
Type Mcq
Answer C
Topic Chapter-1
Mark 1
Level 3
Qno 22
Sno 1
Type Mcq
Answer A
Topic Chapter-1
Mark 1
Level 3
Qno 23
Sno 1
Type Mcq
Answer C
Topic Chapter-1
Mark 1
Level 3
Qno 24
Sno 1
Type Mcq
A 16
B 32
C 64
D 128
Answer D
Topic Chapter-1
Mark 1
Level 3
Qno 25
Sno 1
Type Mcq
A 10
B 12
C 16
D 18
Answer B
Topic Chapter-1
Mark 1
Level 3
Qno 26
Sno 1
Type Mcq
A 368 Bytes
B 138 Bytes
C 1 KB
D 4 KB
Answer A
Topic Chapter-1
Mark 1
Level 3
Qno 27
Sno 1
Type Mcq
A 5MIPS
B 8MIPS
C 10MIPS
D 12MIPS
Answer B
Topic Chapter-1
Mark 1
Level 3
Qno 28
Sno 1
Type Mcq
A Baseline
B Midrange
C Enhanced midrange
D High end
Answer B
Topic Chapter-1
Mark 1
Level 3
Qno 29
Which of the following is a fetch unit for fetching instructions from the
Question
memory
Sno 1
Type Mcq
A Control unit
B Execution unit
D None
Answer A
Topic Chapter-1
Mark 1
Level 3
Qno 30
Sno 1
Type Mcq
Answer C
Topic Chapter-1
Mark 1
Level 3
Qno 31
Sno 1
Type Mcq
A Working register
B FSR register
C Shift register
D Destination register
Answer A
Topic Chapter-2
Mark 1
Level 1
Qno 32
Question How many memory banks are available in Direct addressing mode?
Sno 1
Type Mcq
A 2
B 4
C 8
D 16
Answer B
Topic Chapter-2
Mark 1
Level 1
Qno 33
Sno 1
Type Mcq
A Working register
B FSR register
C Shift register
D Destination register
Answer B
Topic Chapter-2
Mark 1
Level 1
Qno 34
Sno 1
Type Mcq
A W register
B F register
C Accumulator
D B register
Answer A
Topic Chapter-2
Mark 1
Level 1
Qno 35
Sno 1
Type Mcq
A DC
B O
C C
D Z
Answer D
Topic Chapter-2
Mark 1
Level 1
Qno 36
Question DECFSZ f,d instruction requires how many clock cycles if result is Zero?
Sno 1
Type Mcq
A 0
B 1
C 2
D 4
Answer C
Topic Chapter-2
Mark 1
Level 1
Qno 37
Sno 1
Type Mcq
A BTFSC
B BTFSS
C BFTSS
D BFTSC
Answer A
Topic Chapter-2
Mark 1
Level 1
Qno 38
Question BTFSS f,d requires how many clock cycles if result is non zero ?
Sno 1
Type Mcq
A 0
B 1
C 2
D 4
Answer B
Topic Chapter-2
Mark 1
Level 1
Qno 39
Sno 1
Type Mcq
A 0
B 1
C 2
D 3
Answer C
Topic Chapter-2
Mark 1
Level 1
Qno 40
Sno 1
Type Mcq
A Z
B C
C DC
D None
Answer D
Topic Chapter-2
Mark 1
Level 1
Qno 41
Question The instruction has to give to the processor to enter into standby mode?
Sno 1
Type Mcq
A Wdt
B Sleep
C Shtdwn
D Clear
Answer B
Topic Chapter-2
Mark 1
Level 2
Qno 42
In PIC assembly programming target files must be saved with which type
Question
?
Sno 1
Type Mcq
A .INC
B .JPG
C .PIC
D .PNG
Answer A
Topic Chapter-2
Mark 1
Level 2
Qno 43
Sno 1
Type Mcq
A Label
B Mnemonics
C Operand
D Comment
Answer D
Topic Chapter-2
Mark 1
Level 2
Qno 44
Sno 1
Type Mcq
A Bit
B Wait
C Loop
D _again
Answer D
Topic Chapter-2
Mark 1
Level 2
Qno 45
Sno 1
Type Mcq
A 16
B 32
C 128
D 64
Answer B
Topic Chapter-2
Mark 1
Level 2
Qno 46
Sno 1
Type Mcq
A UART
Answer D
Topic Chapter-2
Mark 1
Level 2
Qno 47
Sno 1
Type Mcq
Answer C
Topic Chapter-2
Mark 1
Level 2
Qno 48
Sno 1
Type Mcq
A PIE
B PIR
C PWM
D PPP
Answer A
Topic Chapter-2
Mark 1
Level 2
Qno 49
Sno 1
Type Mcq
A PIE
B PIR
C PWM
D PPP
Answer B
Topic Chapter-2
Mark 1
Level 2
Qno 50
Sno 1
Type Mcq
A Data Memory
B Register
C Stack
D Program memory
Answer C
Topic Chapter-2
Mark 1
Level 2
Qno 51
Sno 1
Type Mcq
Answer A
Topic Chapter-2
Mark 1
Level 3
Qno 52
Sno 1
Type Mcq
A Critical point
B Critical path
C Critical region
D Critical area
Answer C
Topic Chapter-2
Mark 1
Level 3
Qno 53
Sno 1
Type Mcq
A Out pins
B Ports
C Routers
D Connectors
Answer B
Topic Chapter-2
Mark 1
Level 3
Qno 54
Sno 1
Type Mcq
A 1
B 2
C 3
D 4
Answer B
Topic Chapter-2
Mark 1
Level 3
Qno 55
Question The 8pin 12C508 has ___ ports with ___ digital I/O pins respectively ?
Sno 1
Type Mcq
A 1,4
B 2,4
C 2,8
D 4,16
Answer A
Topic Chapter-2
Mark 1
Level 3
Qno 56
the 68pin 17C766 has ____ ports with ___ digital I/O pins
Question
Sno 1
Type Mcq
A 9,69
B 10,69
C 9,66
D 10,66
Answer C
Topic Chapter-2
Mark 1
Level 3
Qno 57
To directly drive the LED’s the source/sink pins must have a current of (in
Question
mA)
Sno 1
Type Mcq
A 10
B 20
C 25
D 15
Answer C
Topic Chapter-2
Mark 1
Level 3
Qno 58
Sno 1
Type Mcq
Answer A
Topic Chapter-2
Mark 1
Level 3
Qno 59
Question TIMER 0 is
Sno 1
Type Mcq
A Readable
B Writable
C Both
D None
Answer C
Topic Chapter-2
Mark 1
Level 3
Qno 60
Question TIMER 1 is
Sno 1
Type Mcq
B 16 bit timer/counter
Answer B
Topic Chapter-2
Mark 1
Level 3
Qno 61
Question TIMER 1 is
Sno 1
Type Mcq
A Readable
B Writable
C Both
D None
Answer C
Topic Chapter-3
Mark 1
Level 1
Qno 62
Sno 1
Type Mcq
A 1
B 2
C 3
D 4
Answer C
Topic Chapter-3
Mark 1
Level 1
Qno 63
Sno 1
Type Mcq
A Synchronised timer
B Synchronised counter
C Asynchronised timer
D Asynchronised counter
Answer B
Topic Chapter-3
Mark 1
Level 1
Qno 64
Sno 1
Type Mcq
A Synchronised timer
B Synchronised counter
C Asynchronised timer
D Asynchronised counter
Answer A
Topic Chapter-3
Mark 1
Level 1
Qno 65
Sno 1
Type Mcq
A Synchronised timer
B Synchronised counter
C Asynchronised timer
D Asynchronised counter
Answer D
Topic Chapter-3
Mark 1
Level 1
Qno 66
Question TIMER 2 is a
Sno 1
Type Mcq
Answer A
Topic Chapter-3
Mark 1
Level 1
Qno 67
Sno 1
Type Mcq
A Capture/Compare/PMW
B Compare/Capture/PWM
C Compare/Capture/PMW
D Capture/Compare/PWM
Answer D
Topic Chapter-3
Mark 1
Level 1
Qno 68
The CCP module bit operations are generally having a bit lengths
Question
of_,__,__ respectively
Sno 1
Type Mcq
A 10,16,16
B 16,10,16
C 16,16,10
D 16,16,16
Answer C
Topic Chapter-3
Mark 1
Level 1
Qno 69
Sno 1
Type Mcq
A Capture
B Compare
C PWM
D Program counter
Answer B
Topic Chapter-3
Mark 1
Level 1
Qno 70
Sno 1
Type Mcq
A Capture
B Compare
C PWM
D Program counter
Answer A
Topic Chapter-3
Mark 1
Level 1
Qno 71
Sno 1
Type Mcq
Intensity control
A
B Motor control
C Temperature control
D All of these
Answer D
Topic Chapter-3
Mark 1
Level 2
Qno 72
Sno 1
Type Mcq
A 8
B 16
C 10
D 20
Answer C
Topic Chapter-3
Mark 1
Level 2
Qno 73
Sno 1
Type Mcq
A Capture
B Compare
C PWM
Answer C
Topic Chapter-3
Mark 1
Level 2
Qno 74
Sno 1
Type Mcq
A 1 MHz
B 2 MHz
C 3 MHz
D 4 MHz
Answer D
Topic Chapter-3
Mark 1
Level 2
Qno 75
Sno 1
Type Mcq
A 10
B 12
C 14
D 16
Answer B
Topic Chapter-3
Mark 1
Level 2
Qno 76
Sno 1
Type Mcq
A 200 ns
B 100 ns
C 400 ns
D 300 ns
Answer A
Topic Chapter-3
Mark 1
Level 2
Qno 77
Sno 1
Type Mcq
A 2
B 4
C 8
D 16
Answer C
Topic Chapter-3
Mark 1
Level 2
Qno 78
Sno 1
Type Mcq
A In circuit Debugger
D In chip Debugger
Answer A
Topic Chapter-3
Mark 1
Level 2
Qno 79
Sno 1
Type Mcq
Answer A
Topic Chapter-3
Mark 1
Level 2
Qno 80
Sno 1
Type Mcq
A 8
B 16
C 32
D 64
Answer C
Topic Chapter-3
Mark 1
Level 2
Qno 81
Sno 1
Type Mcq
A 16
B 26
C 32
D 64
Answer B
Topic Chapter-3
Mark 1
Level 3
Qno 82
Sno 1
Type Mcq
A 16
B 26
C 32
D 64
Answer C
Topic Chapter-3
Mark 1
Level 3
Qno 83
Sno 1
Type Mcq
D All of these
Answer D
Topic Chapter-3
Mark 1
Level 3
Qno 84
Question Signal processing extensions are added in which version ?
Sno 1
Type Mcq
A Version 4
B Version 4T
C Version 5T
D Version 5TE
Answer D
Topic Chapter-3
Mark 1
Level 3
Qno 85
Sno 1
Type Mcq
A Link register
B Stack pointer
C Program counter
D ALU
Answer B
Topic Chapter-3
Mark 1
Level 3
Qno 86
Sno 1
Type Mcq
A Link register
B Stack pointer
C Program counter
D ALU
Answer A
Topic Chapter-3
Mark 1
Level 3
Qno 87
Sno 1
Type Mcq
Answer D
Topic Chapter-3
Mark 1
Level 3
Qno 88
Sno 1
Type Mcq
Answer A
Topic Chapter-3
Mark 1
Level 3
Qno 89
Sno 1
Type Mcq
A C
B O
C OF
D V
Answer D
Topic Chapter-3
Mark 1
Level 3
Qno 90
Sno 1
Type Mcq
A IRQ
B FIQ
C T bit
D J bit
Answer A
Topic Chapter-3
Mark 1
Level 3
Qno 91
Sno 1
Type Mcq
A IRQ
B FIQ
C T bit
D J bit
Answer B
Topic Chapter-4
Mark 1
Level 1
Qno 92
Sno 1
Type Mcq
A THUMB state
B Jazelle state
D ARM state
Answer D
Topic Chapter-4
Mark 1
Level 1
Qno 93
Question When T bit = 1 then processor is in
Sno 1
Type Mcq
A THUMB state
B Jazelle state
D ARM state
Answer A
Topic Chapter-4
Mark 1
Level 1
Qno 94
Sno 1
Type Mcq
A Abort mode
B Supervisor mode
C System mode
D Undefined
Answer A
Topic Chapter-4
Mark 1
Level 1
Qno 95
Question state after reset and generally the mode is in which OS kernel executes
Sno 1
Type Mcq
A Abort mode
B Supervisor mode
C System mode
D Undefined
Answer B
Topic Chapter-4
Mark 1
Level 1
Qno 96
Question special version of user mode that allows full read-write access of CPSR
Sno 1
Type Mcq
A Abort mode
B Supervisor mode
C System mode
D Undefined
Answer C
Topic Chapter-4
Mark 1
Level 1
Qno 97
Sno 1
Type Mcq
A 16
B 20
C 37
D 40
Answer C
Topic Chapter-4
Mark 1
Level 1
Qno 98
Sno 1
Type Mcq
A 16
B 20
C 37
D 40
Answer B
Topic Chapter-4
Mark 1
Level 1
Qno 99
Sno 1
Type Mcq
Answer D
Topic Chapter-4
Mark 1
Level 1
Qno 100
Question Expand SP
Sno 1
Type Mcq
A Status pointer
C Stack Pointer
D Status programme
Answer C
Topic Chapter-4
Mark 1
Level 1
Qno 101
Question LR stands
Sno 1
Type Mcq
A Link router
B Listed register
C Link register
D Listed router
Answer C
Topic Chapter-4
Mark 1
Level 2
Qno 102
Sno 1
Type Mcq
Answer B
Topic Chapter-4
Mark 1
Level 2
Qno 103
Sno 1
Type Mcq
A Byte
B Word
C Half word
D Half Byte
Answer C
Topic Chapter-4
Mark 1
Level 2
Qno 104
Sno 1
Type Mcq
A Byte
B Kilo Byte
C Half word
D Word
Answer A
Topic Chapter-4
Mark 1
Level 2
Qno 105
Sno 1
Type Mcq
A Byte
B Half Byte
C Half word
D Word
Answer D
Topic Chapter-4
Mark 1
Level 2
Qno 106
Sno 1
Type Mcq
A SWAP
B SWP
C SWPA
D SWPB
Answer B
Topic Chapter-4
Mark 1
Level 2
Qno 107
Sno 1
Type Mcq
A Shifting bits
B Guard bits
C Saturation bits
D Aliasing bits
Answer B
Topic Chapter-4
Mark 1
Level 2
Qno 108
Sno 1
Type Mcq
A Shifting bits
B Guard bits
C Saturation bits
D Aliasing bits
Answer C
Topic Chapter-4
Mark 1
Level 2
Qno 109
Sno 1
Type Mcq
A Delay
B Guard bands
C Multipliers
D Shifters
Answer D
Topic Chapter-4
Mark 1
Level 2
Qno 110
Type Mcq
A System on chip
B System on circuit
C Silicon on Chip
D Silicon on Circuit
Answer A
Topic Chapter-4
Mark 1
Level 2
Qno 111
Sno 1
Type Mcq
Answer B
Topic Chapter-4
Mark 1
Level 3
Qno 112
Which of the following is not a type of memory?
a)
Question b)
c)
d)
Sno 1
Type Mcq
A RAM
B FPROM
C EEPROM
D ROM
Answer C
Topic Chapter-4
Mark 1
Level 3
Qno 113
If a RAM chip has n address input lines then it can access memory
Question
locations upto __________
Sno 1
Type Mcq
A 2(n-1)
B 2(n+1)
C 2n
D 22n
Answer C
Topic Chapter-4
Mark 1
Level 3
Qno 114
Sno 1
Type Mcq
A BJT or MOSFET
B FET or JFET
C Capacitor or BJT
D BJT or MOS
Answer D
Topic Chapter-4
Mark 1
Level 3
Qno 115
Sno 1
Type Mcq
A BJT or MOSFET
B FET or JFET
C Capacitor or BJT
D BJT or MOS
Answer A
Topic Chapter-4
Mark 1
Level 3
Qno 116
Sno 1
Type Mcq
A ROM
B EROM
C PROM
D RAM
Answer D
Topic Chapter-4
Mark 1
Level 3
Qno 117
Sno 1
Type Mcq
Topic Chapter-4
Mark 1
Level 3
Qno 118
Sno 1
Type Mcq
Answer A
Topic Chapter-4
Mark 1
Level 3
Qno 119
Sno 1
Type Mcq
Answer C
Topic Chapter-4
Mark 1
Level 3
Qno 120
Sno 1
Type Mcq
A Layer based
B Packet based
D Spiral based
Answer C
Topic Chapter-4
Mark 1
Level 3
Qno 121
Sno 1
Type Mcq
B Printers &scanners
C cameras
D All of these
Answer D
Topic Chapter-5
Mark 1
Level 1
Qno 122
Sno 1
Type Mcq
A IEEE1394
B IEEE1346
C IEEE1394b
D IEEE1346b
Answer A
Topic Chapter-5
Mark 1
Level 1
Qno 123
Sno 1
Type Mcq
A 3200Kbps
B 400Kbps
C 400Mbps
D 3200Mbps
Answer D
Topic Chapter-5
Mark 1
Level 1
Qno 124
Sno 1
Type Mcq
A Control
B Isochronous
C Bulk
D Instruction
Answer D
Topic Chapter-5
Mark 1
Level 1
Qno 125
Type Mcq
A Hub is a bridge
D All of these
Answer D
Topic Chapter-5
Mark 1
Level 1
Qno 126
Sno 1
Type Mcq
A Data request
B Token packet
C Data packet
D Token request
Answer C
Topic Chapter-5
Mark 1
Level 1
Qno 127
Sno 1
Type Mcq
A IEEE1394,IrDA
B Bus protocol
C PIPE
D All of these
Answer D
Topic Chapter-5
Mark 1
Level 1
Qno 128
Sno 1
Type Mcq
Answer C
Topic Chapter-5
Mark 1
Level 1
Qno 129
Sno 1
Type Mcq
A 16
B 20
C 32
D 36
Answer B
Topic Chapter-5
Mark 1
Level 1
Qno 130
The master controls all the slave units at the same time operation is done
Question
in
Sno 1
Type Mcq
C Distributed protocol
Answer A
Topic Chapter-5
Mark 1
Level 1
Qno 131
The master controls all the slave units one after another in specific time
Question
this operation is done in
Sno 1
Type Mcq
C Distributed protocol
Answer B
Topic Chapter-5
Mark 1
Level 2
Qno 132
Sno 1
Type Mcq
A AHB
B AHP
C BHP
D None
Answer A
Topic Chapter-5
Mark 1
Level 2
Qno 133
Sno 1
Type Mcq
Answer B
Topic Chapter-5
Mark 1
Level 2
Qno 134
Sno 1
Type Mcq
Answer C
Topic Chapter-5
Mark 1
Level 2
Qno 135
Sno 1
Type Mcq
Answer D
Topic Chapter-5
Mark 1
Level 2
Qno 136
Sno 1
Type Mcq
Answer C
Topic Chapter-5
Mark 1
Level 2
Qno 137
Sno 1
Type Mcq
A ASP
B ASB
C AHB
D APB
Answer C
Topic Chapter-5
Mark 1
Level 2
Qno 138
Question The PCI follows a set of standards primarily used in _____ PC’s.
Sno 1
Type Mcq
A Intel
B Motorola
C IBM
D SUN
Answer C
Topic Chapter-5
Mark 1
Level 2
Qno 139
Sno 1
Type Mcq
B Expansion of Bandwidth
C None
Answer D
Topic Chapter-5
Mark 1
Level 2
Qno 140
Sno 1
Type Mcq
Answer C
Topic Chapter-5
Mark 1
Level 2
Qno 141
Sno 1
Type Mcq
A I/O
B Memory
C Configuration
Answer D
Topic Chapter-5
Mark 1
Level 3
Qno 142
Sno 1
Type Mcq
A PCI BUS
B PCI interface
C PCI bridge
D Switch circuit
Answer C
Topic Chapter-5
Mark 1
Level 3
Qno 143
Sno 1
Type Mcq
B program counter
C status register
D instruction register
Answer B
Topic Chapter-5
Mark 1
Level 3
Qno 144
Sno 1
Type Mcq
A physical address
B Offset address
C logical address
D absolute address
Answer C
Topic Chapter-5
Mark 1
Level 3
Qno 145
Which of the followingdo the operation for virtual to physical address run-
Question
time mapping?
Sno 1
Type Mcq
B CPU
C PCI
D Operating system
Answer A
Topic Chapter-5
Mark 1
Level 3
Qno 146
Sno 1
Type Mcq
A page register
B program counter
C stack pointer
Answer C
Topic Chapter-5
Mark 1
Level 3
Qno 147
Sno 1
Type Mcq
A page size
C page offset
D Page
Answer B
Topic Chapter-5
Mark 1
Level 3
Qno 148
Question a process is copied into the main memory from the secondary memory
Sno 1
Type Mcq
A Swapping
B Paging
C Segmentation
D Demand paging
Answer D
Topic Chapter-5
Mark 1
Level 3
Qno 149
Sno 1
Type Mcq
D no error occurs
Answer A
Topic Chapter-5
Mark 1
Level 3
Qno 150
Sno 1
Type Mcq
A Memory sharing
B Virtual memory
C Memory management
D Memory control
Answer B
Topic Chapter-5
Mark 1
Level 3
Qno 151
Sno 1
Type Mcq
A Main memory
B Cache
C Buffer
D Virtual memory
Answer D
Topic Chapter-6
Mark 1
Level 1
Qno 152
Sno 1
Type Mcq
Answer D
Topic Chapter-6
Mark 1
Level 1
Qno 153
Sno 1
Type Mcq
A Mobile systems
C Super computers
D Distributed systems
Answer A
Topic Chapter-6
Mark 1
Level 1
Qno 154
Sno 1
Type Mcq
A 264
B 232
C 216
D 224
Answer B
Topic Chapter-6
Mark 1
Level 1
Qno 155
Sno 1
Type Mcq
A i, ii, iii
B i, ii
C i, iv
D iii, iv
Answer B
Topic Chapter-6
Mark 1
Level 1
Qno 156
Question The additional duplicate register used in ARM machines are called as
Sno 1
Type Mcq
A Copied-registers
B Banked registers
C Extra registers
D Extential registers
Answer B
Topic Chapter-6
Mark 1
Level 1
Qno 157
Sno 1
Type Mcq
A 2 byte
B 8 byte
C 3 byte
D 4 byte
Answer D
Topic Chapter-6
Mark 1
Level 1
Qno 158
The effective address of the instruction written in Post-indexed mode,
Question
MOVE[Rn]+Rm is
Sno 1
Type Mcq
A EA = [Rn]
B EA = [Rn + Rm]
C EA = [Rn] + Rm
D EA = [Rm] + Rn
Answer A
Topic Chapter-6
Mark 1
Level 1
Qno 159
Sno 1
Type Mcq
A Machine compiler
B Assembler
C Interpreter
D Converter
Answer B
Topic Chapter-6
Mark 1
Level 1
Qno 160
Sno 1
Type Mcq
A Operators
B OP-Code
C Commands
D Comments
Answer B
Topic Chapter-6
Mark 1
Level 1
Qno 161
Sno 1
Type Mcq
A ADD #5,[R1]
B ADDIME 5,[R1];
C ADDI 5,R1;
D ADD [5],[R1];
Answer C
Topic Chapter-6
Mark 1
Level 2
Qno 162
Question Instructions which won’t appear in the object program are called as
Sno 1
Type Mcq
A Redundant instructions
B Exceptions
C Handler
D Assembler Directives
Answer D
Topic Chapter-6
Mark 1
Level 2
Qno 163
Sno 1
Type Mcq
A End
B Return
C Stop
D Terminate
Answer B
Topic Chapter-6
Mark 1
Level 2
Qno 164
Question Which BUS arbitration approach uses the involvement of the processor.
Sno 1
Type Mcq
A Centralised arbitration
B Distributed arbitration
C Random arbitration
Answer A
Topic Chapter-6
Mark 1
Level 2
Qno 165
Sno 1
Type Mcq
A RAM
B ROM
C Timers
Answer D
Topic Chapter-6
Mark 1
Level 2
Qno 166
Sno 1
Type Mcq
A Sensor
B Processor
C Actuator
D Timer
Answer C
Topic Chapter-6
Mark 1
Level 2
Qno 167
Sno 1
Type Mcq
A MOV A, #6AH
B MOV A, 04H
C MOV A, R4
D All the above
Answer B
Topic Chapter-6
Mark 1
Level 2
Qno 168
Sno 1
Type Mcq
A EQU
B ORG
C END
D START
Answer B
Topic Chapter-6
Mark 1
Level 2
Qno 169
Sno 1
Type Mcq
Answer C
Topic Chapter-6
Mark 1
Level 2
Qno 170
Sno 1
Type Mcq
Answer C
Topic Chapter-6
Mark 1
Level 2
Qno 171
Sno 1
Type Mcq
A Opcode
B Mnemonic
C Both
D None
Answer C
Topic Chapter-6
Mark 1
Level
3
Qno 172
Question Which instruction is used for timing delays to waste clock cycles?
Sno 1
Type Mcq
A NOP
B RETURN
C CLR
D RST
Answer A
Topic Chapter-6
Mark 1
Level
3
Qno 173
Sno 1
Type Mcq
A Compiler
B Cross compiler
C Linker
D Cross linker
Answer B
Topic Chapter-6
Mark 1
Level
3
Qno 174
Sno 1
Type Mcq
A Timeliness
B Concurrency
C Heterogeneity
D All of these
Answer D
Topic Chapter-6
Mark 1
Level
3
Qno 175
To measure dynamic efficiency of a networked embedded system
Question
______is required.
Sno 1
Type Mcq
A Number of PC cycles
Answer B
Topic Chapter-6
Mark 1
Level
3
Qno 176
Sno 1
Type Mcq
A Compiler
B Cross assemblers
C Linker
D Cross linker
Answer B
Topic Chapter-6
Mark 1
Level
3
Qno 177
Sno 1
Type Mcq
Answer C
Topic Chapter-6
Mark 1
Level
3
Qno 178
Sno 1
Type Mcq
Answer A
Topic Chapter-6
Mark 1
Level
3
Qno 179
Question Which of the following is/are the features of high level programming ?
Sno 1
Type Mcq
A Recursion
B Dynamic allocation
C Typing
D All of these
Answer D
Topic Chapter-6
Mark 1
Level
3
Qno 180
Sno 1
Type Mcq
A Static
B Dynamic
C Automatic
D Fixed
Answer C
Topic Chapter-6
Mark 1
Level
3
Section 2
Sno 2
Name SECTION-2
Time 60
Mark 2
Negative 0
Questions - S2
Qno 181
Define Embedded system with examples and List out the types of
Question
embedded systems?
Sno 2
Type Sq
Topic Chapter-1
Mark 2
Level 1
Qno 182
Sno 2
Type Sq
Topic Chapter-1
Mark 2
Level 1
Qno 183
Question List out few differences between Base line PIC and Midrange PIC ?
Sno 2
Type Sq
Topic Chapter-2
Mark 2
Level 1
Qno 184
Sno 2
Type Sq
Topic Chapter-2
Mark 2
Level 1
Qno 185
Sno 2
Type Sq
Topic Chapter-3
Mark 2
Level 1
Qno 186
List out all processor modes of ARM and its corresponding status
Question
registers?
Sno 2
Type Sq
Topic Chapter-3
Mark 2
Level 1
Qno 187
Sno 2
Type Sq
Topic Chapter-4
Mark 2
Level 2
Qno 188
Question Write down the applications and algorithms of Digital Signal Processing ?
Sno 2
Type Sq
Topic Chapter-4
Mark 2
Level 2
Qno 189
Sno 2
Type Sq
Topic Chapter-5
Mark 2
Level 2
Qno 190
Question Write a short note on Embedded system operating system?
Sno 2
Type Sq
Topic Chapter-6
Mark 2
Level 2
Qno 191
Sno 2
Type Sq
Topic Chapter-6
Mark 2
Level 2
Qno 192
Sno 2
Type Sq
Topic Chapter-1
Mark 2
Level 3
Qno 193
Sno 2
Type Sq
Topic Chapter-2
Mark 2
Level 3
Qno 194
Write the instruction format of byte oriented ,bit oriented ,literal and
Question
control instructions?
Sno 2
Type Sq
Topic Chapter-2
Mark 2
Level 3
Qno 195
Sno 2
Type Sq
Topic Chapter-3
Mark 2
Level 3
Qno 196
Sno 2
Type Sq
Topic Chapter-4
Mark 2
Level 2
Qno 197
Sno 2
Type Sq
Topic Chapter-5
Mark 2
Level 2
Qno 198
Sno 2
Type Sq
Topic Chapter-6
Mark 2
Level 2