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15.0. - Fpga
15.0. - Fpga
► "Aprogrammable
Field programmable gate array (FPGA) is a
logic device that supports
implementation of relatively large logic circuits."
Elements of FPGA
► The basic elements of an Field Programmable
Gate Array are:
Configurable logic blocks(CLBs)
e inputs and outputs
Architecture of FPGA
The following figure represents the
architecture of a single CLB.
Transistor Switches
Why FPGA?
Digital Logic Meant:
lnputs Planes of
ANDs, ORs
Predefin ea MD array IN ~ y
w= a&:b&e'
x= abe+ abe'+ ab'e'
y= abe'+ ab'e'
Logic Function
Sums
Sum of Products
"' ;¡ t, ¡; e ¡
'- - - - ' ~
r r ,.lfnlil1,y
,- ..
1-N0~n;,¡ Programmed PLD
w J
W: [A r.r.) 1<6t.Z1
Why FPGA?
► PROM
► The first type of user-programmable chip that could implement
logic circuits was the Programmable Read-Only Memory
(PROM), in which address lines can be used as logic circuit
inputs and data lines as outputs.
Drawbacks:
► Logic functions require more than a few product terms
► A PROM requires a full decoder for its address inputs.
► PROMS are thus an inefficient architecture for realizing logic
circuits -> Hence, they are rarely used in practice for that
purpose.
Why FPGA?
PLAs
► Carne as Replacement to PROMs
► Logically, a PLA is a circuit that allows
implementing Boolean functions in sum-of• Sums
product form.
► The typical implementation consists of input
buffers for all inputs, the programmable AND• ~
l "t ~ rt l ' rul l ; i e
1-.NOA1r1,
►.)'=f.Al.l>&c)
matrix, and output buffers. ,-(.,11 h\~)I $6.CI
► Expensive to manufacture
► offer poor speed-performance.
► Both disadvantages are due to the two levels of configurable
logic, because programmable logic planes are difficult to
manufacture and introduce significant propagation delays.
Why FPGA?
► PALs
► To overcome the weaknesses of PAL, Programmable Array
Logic (PAL) devices were developed.
► PALs provide only a single level of programmability,
consisting of a programmable "wired" AND plane that feeds
fixed OR-gates.
+
* Preaafim,d
IFrn!llalTllmab'le llllilK Un-programmed State
1
WA.
link:
Planes of
AINDs, ORs
:1=(61&b&o)
□ ~ "IC.'.-.::8 3813:
ooooo~
□ i()----11188:
PROGR.41"\(MABLE
! 5 () 00 0 0 0 0 0
JNTERCONNECT
¡oo ooooo 1/0BLOCKS
...
o¡ 11na2:
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Programmable Connections
fnltulti
110 block
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□ 1
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□ 1
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□ □ 1 1
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Simplifled Internal S tructure of FPGA
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FPGA Structural Classification
► Basic structure of an FPGA includes Logic elements,
Programmable interconnects and Memory.
► Arrangement of these blocks is specific to particular
manufacturer.
► On the basis of intemal arrangement of blocks FPGAs can be
divided into three classes:
► Symmetrical arrays
► Row based architecture
► Hierarchical PLDs
Symmetrical arrays
-
□□ □□ □□ □□.. - 7- Logíc
□
block
·-
1 1 1
□ □ □
1/0 b l o c k -0 1
□ 1 1
□
□
□ □ □ 1
□ □ 1 1
□
□
□
□ □ □ 1
□ □ 1 1
□
□
□ □ □ □ □ □
□ 1 1 1
□
□□ □□ □□ □□
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Symmetrical arrays
► This architecture consists of logic elements (called CLBs)
arranged in rows and columns of a matrix and interconnect laid
out between.
► This symmetrical matrix is surrounded by I/O blocks which
connect it to outside world. I/O blocks also control functions
such as tri-state control, output transition speed.
► Each CLB consists of n-input Lookup table and a pair of
programmable flip flops.
► Interconnects provide routing path. Direct interconnects
between adjacent logic elements result smaller delay compared
to general purpose interconnect.
Row based Architecture
1 1/0 Hlocks
1
1111 1111111 111111111 111 11111111 1111111
Logic
1 Hl.ock
Rounng Rows
Cbanuels 1 1 ■■1 ■■■■■■■■■■■■■1 ■■■■■1 ■■1 ■■■■■■■■1 1
1 1/iO :Blocks 1
Row based Archítecture
Row based Architecture
► Row based architecture consists of altemating rows of logic
modules and programmable interconnect tracks.
► I/O blocks is located in the periphery of the rows.
► One row may be connected to adjacent rows via vertical
interconnect.
► Logic modules can be implemented in various combinations.
► Combinatoria! modules contain only combinational elements
while Sequential modules contain both combinational elements
along with flip flops. Thus, sequential module can implement
complex combinatorial-sequential functions.
Hierarchical PLDs
1/0 Block
~ ..:;;:
~ tJ!
,_o
1= -= ~
o~ o
1- .....
......
Hterarchíeal PLD·
Hierarchical PLDs
► This architecture is designed in hierarchical manner with top
level containing only logic blocks and interconnects.
► Each logic block contains number of logic modules. And each
logic module has combinatoria! as well as sequential functional
elements.
► Communication between logic blocks is achieved by
programmable interconnect arrays.
► Input output blocks surround this scheme of logic blocks and
interconnects.
FPGA Classification on user programmable
switch technologies
So far We have understood that,
► FPGAs are based on an array of logic modules and a supply of
uncommitted wires to route signals.
► In gate arrays these wires are connected by a mask design
during manufacture.
► In FPGAs, however, these wires are connected by the user and
therefore must use an electronic device to connect them.
FPGA Classification on User
__Programmable__ Switch_ technologies _
► Three types of devices based on how interconnects are
configured:
, - - - - - .. 1
1 1 1
: ::
1..
1
i 1
---- .
■■■
~ ..
Advantages:
► They are non-volatile so they do not require an extra PROM
for loading.
Disadvantages:
► The EEPROM process is complicated.
FPGA Design Flow
Design Entrv N - - - - - .
Stmulatíon
Desígn
Ceusrratuts Synthesís
Download
FPGA Design Flow
► 1. System Design
At this stage designer has to decide what portian of his
functionality has to be implemented on FPGA and how to
integrate that functionality with rest of the system.
► https://www.youtube.com/watch?v=gUsHwi4M4xE
► https://www.youtube.com/watch?v=CLUoWkJUnNO
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