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Code
--khai bao thu vien
LIBRARY IEEE;
Use IEEE.STD_LOGIC_1164.all;
--khai bao thuc the
ENTITY Botru is
Port( A,B,Cin: in std_logic;
Sub, Cout: out std_logic);
ARCHITECTURE dataflow of Botru is -- dataflow
Begin
Sub <= A xor B xor Cin;
Cout<= (Cin and B) or (not A and B) or (not A and Cin);
End ;
ARCHITECTURE behavioral of Botru is – behavioral
Begin
Process( A,B,Cin)
Begin
If( a=’0’ and

Bài 2:

--khai bao thu vien

LIBRARY IEEE;
Use IEEE.STD_LOGIC_1164.all;
--khai bao thuc the
ENTITY mach_S is
Port( A,B,C: in std_logic;
S: out std_logic);
And Mach_S;
Entity AND2 is
Port( a1,a2: in std_logic;
Y1: out std_logic);
End ADN2;
ARCHITECTURE dataflow of AND2 is
Begin
Y1 <= a1 and a2;
End dataflow;
Entity OR2 is
Port( b1,b2: in std_logic;
Y2: out std_logic);
End OR2;
ARCHITECTURE dataflow of OR2 is
Begin
Y2 <= b1 or b2;
End dataflow;
ARCHITECTURE machtong of mach1 is -- STRUC
Signal s1: std_logic;
Component AND2
Port( a1,a2: in std_logic;
Y1: out std_logic);
END Component;
Component OR2
Port( b1,b2: in std_logic;
Y2: out std_logic);
END Component;
Begin
U1: AND2 port map ( A,B,S1);
U2: OR2 port map (S1, C,S);
And machtong;

Bai 3: mux 4-1

Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_USIGNED.ALL;
Entity mux_4 is
Port( A,B,C,D: in bit;
Sel : in bit_vecter(1 downto 0);
F : out bit);
end entity mux_4to1;
architecture mux_4_arch of mux_4 is
begin
F <=A when Sel=“00” else
B when Sel=“01” else
C when Sel=“10” else
D;
end architecture;