IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO.

2, JUNE 2009 269

On the Way to Zero Defect of Plastic-Encapsulated

Electronic Power Devices—Part I: Metallization
Peter Alpern, Peter Nelle, Endre Barti, Helmut Gunther, Angela Kessler, Rainer Tilgner, and Matthias Stecher

Abstract—Concerning thermomechanically induced failures,

such as metal line deformation and passivation cracks, there
is a practicable way to achieve the zero-defect limit of plastic-
encapsulated power devices. This limit can be reached by eval-
uating the influence of the major components involved and,
consequently, by selecting the appropriate materials and mea-
sures. On the other hand, the interdependence between all compo-
nents must always be kept in mind, i.e., chip and package have to
be regarded as an entity. An important finding was that applying
simply one improvement step will not necessarily lead to the
desired goal. Only the implementation of all improvement steps
considering their interdependence is the key for the perfect overall
system chip and package. In Part I of this series of papers, the yield
stress of the power metallization is shown to play a crucial role for
the generation of metal deformation and passivation cracks. Un-
derstanding the ratcheting mechanism led to the development of a
new layered metallization material with a distinctly increased yield
stress, resulting in a considerably reduced failure generation.
Fig. 1. Typical passivation cracks in the corners of broad Al lines near the
Index Terms—Finite-element-method (FEM) simulation, passi- chip edge (lower right corner) after 1000 TCs between −55 and +150 ◦ C.
vation cracks, power device, ratcheting, thermomechanical stress,
yielding, zero defect.

I. I NTRODUCTION

M ETAL LINE deformations and cracks in brittle passiva-

tion and interlayer dielectrics are still a major reliability
concern in the case of plastic-encapsulated power semiconduc-
tor ICs.
Much work has been done in the past to describe and
understand the failure mechanism and its root cause [1]–[7].
The difference (mismatch) between the coefficient of thermal
expansion (CTE) of a molding compound (MC) and silicon
(Si) was identified as the root cause, which leads to a thermo-
mechanically induced shear stress during, for example, tem-
perature cycling. In the chip edge and corner regions, this Fig. 2. Cross section through a typical power IC (schematic view).
stress reaches its maximum value. If broad metal lines coated The (arrows) shear stress τ is pointing from the chip edge to the chip middle
and induces passivation cracks (see inserted FIB cut).
with brittle passivation like plasma silicon nitride SiNx are
located near the chip edge or corner, metal deformation and pas-
sivation cracks during temperature cycling may be generated (see Figs. 1 and 2). In severe cases, these cracks propagate into
the insulating dielectric layers to the lower metal lines, causing
electric shorts by means of protruded metal as well as corrosion
Manuscript received December 3, 2007; revised February 27, 2008 and if moisture penetrates the MC from outside.
December 5, 2008. First published March 21, 2009; current version published To improve the quality and to minimize reliability jeopardy,
June 5, 2009.
P. Alpern, P. Nelle, H. Gunther, R. Tilgner, and M. Stecher are with the
the failure root cause has to be minimized. This requires
Infineon Technologies AG, 85579 Neubiberg, Germany (e-mail: peter.alpern@ optimizing the statics of the overall system chip and package
infineon.com; peter.nelle@infineon.com; matthias.stecher@infineon.com). (OCP), as well as the deformation behavior of the involved
E. Barti is with the Production Processes Department, Siemens Corporate
Technology, 81730 Munich, Germany (e-mail: endre.barti@siemens.com). components.
A. Kessler is with the Infineon Technologies AG, 93009 Regensburg, To prevent the passivation cracks, some lessons had already
Germany (e-mail: angela.kessler@infineon.com). been learned in the past. One of the most important, for in-
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. stance, was the demand for good adhesion [8] between all parts
Digital Object Identifier 10.1109/TDMR.2009.2018299 of a device (OCP). Whereas coating the chip with polyimide
1530-4388/$25.00 © 2009 IEEE

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270
Fig. 3. Schematic of a typical electronic power device.
(PI) [9]–[11] has strengthened the interface MC/chip, adhesion
between the MC and the lead frame has been improved by
applying a special treatment [12]. In addition to adhesion, the
influence of the mechanical properties of the MC (CTE and
Young’s modulus E) has been investigated, and the superiority
of the “low-stress” (low-CTE) MCs has been found out [13],
[14]. Furthermore, the impact of the chip design [15]–[20] has
been analyzed in more detail. As a result, the advantage of
slotted broad metal lines in the corner and edge regions as
well as of 45◦ inclined lines in the corner region has been
recognized.
The devices investigated in the literature mentioned above
normally had 1-μm-thick Al metallization. In many cases, the
application of one or two improvements described above could
drastically reduce the thermomechanically induced failures.
The situation changes if power devices are considered.
Within a power device, the stress distribution is governed
by two construction features: while the top side of the chip is
conventionally covered by the MC, the back side is attached to
a sturdy Cu heat slug. Fig. 3 shows a schematic illustration of a
typical power device as, for example, in a P-DSO 36 package.
The main features of power ICs are thick and broad metal
plates for the wiring of power double-diffused MOS (DMOS)
transistors, which cover a major part of the chip area. The
thickness of the top metallization, which is also called power
metallization, lies in the range between 3.5 and 5 μm. In the
case of power ICs, it turned out that applying one or two
improvement measures as exemplified above was not enough.
In spite of such precautions, considerable passivation cracks
and metal deformation still occurred after temperature cycling.
The aim of this series of papers is to demonstrate that there
is a practicable way to reach the zero-defect frontier after a
temperature cycling stress: first, by evaluating in detail the
influence of the major components involved and, consequently,
by selecting the appropriate materials and measures, and sec-
ond, by always keeping in mind that chip and package have to
be regarded as an entity (OCP).
This series of papers is organized as follows. In Part I, the
evaluation of the Al metallization is presented. Here, the yield
stress of the power metallization is shown to play a crucial role
for the failure mechanisms metal deformation and passivation
cracking. The influence of the MC and its governing parameters
CTE and Young’s modulus on the one hand, as well as its vis-
coelastic behavior on the other hand, is evaluated and discussed
in Part II. In Part III, the impact of chip coatings like PI and
passivation is studied. Subsequently, the role of the chip design
is discussed, and a design optimization as performed by finite-
element-method (FEM) simulation is proposed. Finally, the
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 2, JUNE 2009
Fig. 4. Principal 2-D setup. (Top) MC surrounding the Si chip and the Cu lead
frame. The package dimensions were 15.9 × 3.25 mm2 , the lead frame size
was 13.7 × 1.3 mm2 , and the die size was 7.3 × 0.38 mm2 . (Bottom) Zoomed
view of the left chip corner with (arrow) highest shear stress τ above an Al
metal plate covered with a SiNx passivation layer of thickness h (dotted arrows:
counterforce to shearing F ).
discussion of the results of Part III and the conclusions resulting
from the whole series of papers (Parts I–III) are presented.
II. A LUMINUM M ETALLIZATION
A. Brittle Passivation Layers Over Ductile Aluminum Plates
In this paper, the theory of Suo [5] and Huang et al. [6],
[7] has been used to describe the mechanisms leading to crack
formation in passivation films. In the following, a digest of
these mechanisms is presented.
Consider a Si chip of length b soldered on a Cu die pad and
assembled in an MC, as indicated in Fig. 4. At the beginning
of the molding process at 175 ◦ C, the MC is in a liquid state.
After subsequent polymerization, the material has a relatively
low Young’s modulus. This will dramatically change when the
device is cooled down to room temperature at the end of the
molding process or to −55 ◦ C during a temperature cycling
stress. Below the glass transition temperature Tg , the MC gains
a high Young’s modulus. Due to shrinking relative to the silicon,
the MC causes a shear stress in the passivation film covering the
metal plates. This shear stress τ caused by the CTE mismatch
between the MC and Si is maximum near the chip edges (x =
±b/2) and decreases in the direction of the chip center (x = 0).
At the chip center, the shear stress vanishes.
Suo [5] and Huang et al. [6], [7] have shown that, after
typically 250 temperature cycles (TCs), the yielded metal layer
that is similar to a liquid does not transfer the shear stress
to the silicon chip anymore. The only balancing force is now
established by the thin brittle passivation layer anchored at the
left- and right-hand sides of the metallization plate (see the dot-
ted arrows in Fig. 4). According to Suo [5, eq. 68], the max-
imum tensile stress σA at the two anchoring points of the
passivation layer is
τ ·L
σA = (1)
2h
where τ is the shear stress, L is the length of the Al plate, and
h is the passivation thickness.
ALPERN et al.: ON THE WAY TO ZERO DEFECT OF PLASTIC-ENCAPSULATED ELECTRONIC POWER DEVICES I
For an aluminum plate of length L ≥ 200 μm, even a moder-
ate shear stress gives rise to tensile passivation stresses that are
beyond the fracture limit of about 1 GPa [6]. The tensile stress
in the passivation can be reduced by reducing the shear stress
τ and the length L of the Al plate, as well as by increasing the
passivation thickness h. The shear stress τ can be influenced
by the mechanical properties of the MC and the metal line
dimensions by the chip design. This will be discussed in more
detail in Parts II and III of this series of papers.
Suo [5] and Huang et al. [6], [7] have developed a theory
describing the basic principles of the stress enhancement in the
dielectric layer. They assumed an ideal elastoplastic behavior
of the metal film (see [5], Fig. 32). During each TC, the CTE
mismatch between the MC and silicon will cause an in-plane
elastic compression followed by a plastic flow of the aluminum
in compression at the high-temperature part of the cycle when
the yield stress of the aluminum is reached. Conversely, the
mismatch will cause an in-plane elastic tensile strain followed
by a plastic strain of the aluminum in tension at the low-
temperature part of the cycle when the yield stress is reached.
However, in addition, a shear stress τ is acting always into the
same direction on top of the aluminum. Independently from
high- or low-temperature excursion, it gives rise to a certain
shear flow or tilting of the metal every time the yield stress is
reached (see [5, Fig. 33]). The multiaxial plastical flow occurs
in the ratio (plastical tilting)/(plastical in-plane strain), which,
according to the plastical flow rules, is proportional to the ratio
(shear stress)/(in-plane stress) (see [5, eq. 78]). As mentioned
above, the shear stress, which, in the theory of Suo [5] and
Huang et al. [6], [7], is set to be constant, is always pointing
into the same direction, namely, from the edge to the middle of
the chip. Consequently, the successive tilting of the aluminum
is also going into the same direction. Therefore, each TC gives
rise to a tilting in the direction to the middle of the chip,
which, for many cycles, sums up to considerable amounts. This
phenomenon is called ratcheting [5]. At the end, the Al film
has totally yielded, being not able to transfer the shear stress to
the underlying layers anymore, similarly to a viscous fluid. The
whole counterforce against the shear stress is now only built up
by the edges of the passivation layer. The tilting δγp of the Al
film for each TC is given by [5]
 
12(1 − νm )τm Em (αm − αs )(TH − TL )
δγp =  − 2 (2)
Em (1 − νm ) Ym2 − 3τm
2
where νm is the Poisson ratio, Em is the Young’s modulus,
Ym is the yield stress, τm is the shear stress, αm is the CTE
of the metal, αs is the CTE of Si, and TH and TL are the
highest and lowest cycle temperatures, respectively. Yielding
and, therefore, ratcheting occur only if the term in the brackets
of (2) is positive. As a consequence, to get thermomechanically
stable structures, this term must be kept zero or negative. Thus,
from (2), one obtains
Em (αm − αs )(TH − TL )
S=  ≤ 2.
(1 − νm ) Ym2 − 3τm
2 TiN (see Fig. 6) was realized. In the following, this setup
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271
Fig. 5. Yield stress of an Al film at room temperature as a function of its
thickness.
The dimensionless quantity S can be interpreted as a “stability
indicator” and (3) as a “stability relation.” If this stability
relation is fulfilled, no yielding and no tilting (ratcheting) takes
place, and the metal film will stay elastic under the temperature
cycling stress. As a result, no stress buildup in the passivation
layer will occur. Now, the counterforce to balance the shear
stress (see Fig. 4) is not formed anymore by the passivation
layer alone; it is also formed by the elastic aluminum layer and
the body of the Si chip. Thus, critical stresses in the passivation
and cracks therein are avoided.
The stability condition as defined by (3) can be fulfilled by
lowering the temperature interval TH − TL or by raising the
metal yield stress so that, during temperature cycling, the yield
limit is not reached. Since lowering of the temperature interval
is not an option, the second possibility will be considered in the
following.
B. Crack Prevention by an Aluminum Multilayer
One possibility is to take other materials for the metal-
lization. Metal layers with a high yield stress like tungsten,
however, would have too high resistivity, and thick electro-
plated power copper layers would mean a profound change of
technology. A simple method to increase the yield stress of
the aluminum metallization is to reduce its thickness. This is
a direct consequence of the effect that a thinner Al layer has
a smaller average grain size. Assuming a Hall–Petch relation
[21] of yield stress versus thickness, the published yield stress
measurements [22], [23] were fitted as a function of different
aluminum thicknesses (see Fig. 5).
According to this curve, the standard aluminum thickness for
a power metal wiring of about 3.5 μm has a low yield stress of
100 MPa. This leads to severe ratcheting and stress buildup in
the passivation layer, as can be seen by applying the criteria of
Suo [5] and Huang et al. [6], [7] and as will be shown below
by a FEM calculation. For a thickness of 500 nm, however,
the aluminum yield stress will increase to 300 MPa. This will
be strong enough to resist yielding during temperature cycling
and, therefore, to prevent metal ratcheting. To maintain the high
yield stress and to achieve the desired low resistivity, a setup
of thin aluminum layers separated by 20-nm-thin conductive
(3)
272
Fig. 6. Al multilayer metallization with four 850-nm layers separated by
20-nm TiN (SEM image).
will be called “Al multilayer.” Each Al layer consisted of a
99.5% Al/0.5% Cu alloy.
The impact of the increasing yield stress on the stability
indicator S [see (3)] is shown in Fig. 7. When the thickness
of the power metallization is kept constant at 3.5 μm, the
yield stress is increased by increasing the number of its layers.
The stability relation is clearly violated by a 3.5-μm-thick
monolayer and fulfilled when at least four Al layers are used
for the power metallization (Al 4× multilayer).
The distinctly increased yield stress of a multilayer relative
to the standard single-layer metallization has been confirmed by
microcompression measurements (see Fig. 8). For this purpose,
the cylindrical columns of aluminum and underlying layers
were cut out from the chip surface by a focused ion beam
(FIB). Afterward, these columns were vertically compressed
in a special nanoindenter equipment, with the possibility to
measure the stress/strain and relieve curves. The SEM images
after compression in Fig. 8 show a slip deformation in the case
of the single layer and a broadening of all part layers in the case
of the 4× Al multilayer. The stress/strain and relieve curves
are presented in Fig. 9. Here, the 4× Al multilayer shows a
significantly higher yield level of about 280 MPa compared
with approximately 150 MPa for the single Al layer.
C. Setup and Material Models for Al
In a first approach, the mechanism of ratcheting of a 3.5-μm-
thick power Al plate was investigated by FEM simulation using
a low yield stress of 100 MPa for the standard metallization
and a higher yield stress of 300 MPa for the multilayer. As
mentioned above, in the theory of Suo [5] and Huang et al.
[6], [7], shear stress τ is considered to be constant. In reality,
however, the shear stress is a function of temperature. During
a TC between −55 and +150 ◦ C, the shear stress reaches its
lowest value at 150 ◦ C. For many modern MCs, this temper-
ature is clearly higher than the glass transition temperature.
On the other hand, the highest shear stress arises at the lowest
temperature of the cycle. This has been taken into account in
the FEM simulations discussed in the following. Here, the 2-D
setup shown in Fig. 4 was used, where the whole system was
considered: a die pad, the MC, Si die, PI coating, dielectric lay-
ers, an Al plate, and a passivation layer. The layer thicknesses,
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 2, JUNE 2009
basic constants, and material models used for the simulations
are shown in Tables I and II.
For the Al metallization, a bilinear kinematic (BKIN) hard-
ening model with similar temperature dependence of the yield
stress as described in [24] was applied. The corresponding
stress/strain curves are shown in Fig. 10(a). A 3.5-μm-thick
multilayer consists of up to seven approximately 500-nm-
thick single Al layers separated by 20-nm conductive TiN.
It is assumed that the whole multilayer has the same yield
stress as each of its single Al components, i.e., 300 MPa at
25 ◦ C compared with 100 MPa for a 3.5-μm Al single layer
(see Fig. 5). In addition, it is supposed that this yield stress
enhancement by a factor of 3 also holds for all yield stresses
at higher temperatures. This way, similar stress/strain curves
for the Al multilayer metallization were obtained and were
implemented in the FEM simulations.
In Part II of this series of papers, another nonlinear kinematic
hardening law following a Chaboche–Armstrong–Frederick
model [25], [26] will be considered, which provides, among
others, a smoother crossover between the elastic and plastic
regions of the stress/strain curves [see Fig. 10(b)]. In addition,
the yield stresses here have been derived from ratcheting exper-
iments [27]. However, for the first approach discussed in this
part, even the simple BKIN model in Fig. 10(a) will turn out to
be sufficient to qualitatively reproduce the effect of ratcheting
mentioned above.
D. FEM Simulation Results
The simulations presented in the following were performed
with ANSYS. Fig. 11(a) shows in a zoomed view of the left chip
corner the shear stress after the first cooling down from 150 to
−55 ◦ C. The shear stress decreases from 60 MPa at the left chip
corner to 30 MPa at a distance of 230 μm away from the corner.
The Al plate was a 200-μm-wide standard 3.5-μm-thick single
layer; the thicknesses of the passivation and PI layers were
800 nm and 5 μm, respectively.
After 62 TCs, the shear stress distribution significantly
changes [Fig. 11(b)]. The metal film has yielded and, therefore,
is not able to transfer the whole shear stress to the underlying
bulk silicon. The change in the stress distribution not only is
limited to the narrow environment of the aluminum plate but
also affects the broad MC neighborhood. This demonstrates that
the shear stress depends not only on the temperature and the
distance from the chip corner but also on the number of TCs.
All these dependencies easily emerge from the FEM simulation
of the overall system (OCP).
Of major interest is the evolution of the stress in the passiva-
tion layer at the edges of a large aluminum plate lying near the
chip edge. Fig. 12(a) and (b) shows the principal stress S1 at
−55 ◦ C after 1 and 62 cycles, respectively. As expected, the
tensile stress in the passivation layer changed from 0.5 GPa
after 1 cycle to a significantly higher value of 4 GPa after
62 cycles, which is well above the fracture limit. In reality,
the simulated deformation of the passivation layer will not be
observed because cracks would have occurred much earlier.
Fig. 13(a) and (b) shows the situation at the right edge of
the metal plate, which is closer to the chip center, after 1 and
ALPERN et al.: ON THE WAY TO ZERO DEFECT OF PLASTIC-ENCAPSULATED ELECTRONIC POWER DEVICES I 273

Fig. 7. Stability indicator S [see (3)] as a function of the number of layers. The power metal thickness was kept constant at 3.5 μm. The yield stress for each
multilayer system was determined from Fig. 5, whereas, for the shear stress, the value τm = 50 MPa was used (see the simulation part below). The temperature
interval was TH − TL = 205 ◦ C; the other parameters were from Table I.

62 TCs, respectively. Again, a strong increase in stress after

Fig. 8. Deformation of a (a) single and a (b) 4× multilayer column (left)
before and (right) after microcompression measurement (SEM images).
62 TCs, together with a strong deformation of the aluminum
and passivation layer, is observed. The simulated deformation
of the passivation is not realistic because, like in the previ-
ous case, shear cracking would have occurred before. This
is demonstrated by the added FIB cut of the right edge of
a passivated aluminum plate after 1000 cycles [see inset in
Fig. 13(b)].
One way to reduce cracking is to introduce slots inside
the aluminum plates [15], [19], [20], limiting, therefore, the
aluminum width L to values that are far below the stress limit
for cracks in (1). In a practical layout, this would mean very
narrow metal stripes near the chip corners and edges. For power
technologies with the need of a very low wiring resistance of
large DMOS transistors, however, the increase in resistivity
would be too high. Therefore, one should primarily look for
other possibilities to reduce the stress in the passivation layer.
As discussed above, an effective way to reduce or to elim-
inate ratcheting is to increase the yield stress of the metal
film using an Al multilayer metallization. Consequently, in a
second approach, simulations were performed with a higher
yield stress, i.e., 300 MPa (instead of 100 MPa), as would be
expected for the case of a 6× or 7× Al multilayer. As a result,
the stress in the passivation layer has not increased anymore
after temperature cycling, confirming the absence of ratcheting
(see Fig. 14).

E. Effect of an Al Multilayer on Surface Damage

Fig. 9. Microcompression stress/strain curve of a single and a 4× Al multi-
layer at room temperature.
The simulation results presented above were checked by
analyzing the chips after the temperature cycling stress. The
thermomechanically induced damage like metal deformation
(wrinkling) and passivation cracks was evaluated for both met-
allization types: standard Al as well as an Al multilayer. The die

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274 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 2, JUNE 2009

TABLE I
LAYER THICKNESSES h, POISSON RATIO ν, YOUNG’S MODULUS E, YIELD STRESS σy , CTE AT ROOM TEMPERATURE ,
AND M ODELS U SED IN THE C ALCULATIONS

TABLE II
YIELD STRESS σy FOR THE Al METALLIZATION AS A FUNCTION OF TEMPERATURE

III. D ISCUSSION AND C ONCLUSION

used for the evaluation of wrinkling and passivation cracks had
the size 7.3 × 4.1 × 0.38 mm3 ; the top Al layer was covered
by a passivation layer consisting of 300 nm silicon oxide and
800 nm silicon nitride. The final die coating was a 5-μm-thick
PI layer.
Wrinkling: Fig. 15 shows the wrinkling of the top Al layer
in one chip corner after 1000 TCs. The amount of wrinkling
correlates to the magnitude of shear forces acting on top of the
aluminum plates.
However, it is also a measure of the plasticity of the alu-
minum. A distinct decrease in the wrinkling from a single layer
over a 4× multilayer to a 6× multilayer is distinctly observable.
The expectation that increasing the metallization yield stress
leads to an increased stability of the metal layer is clearly
demonstrated.
Passivation Cracks: A chip with standard metal showed
the well-known amount of passivation cracks after 1000 TCs
(see Fig. 1). The introduction of the multilayer metallization
drastically improved the quality. The number of cracks in the
sensible edge and corner regions could be distinctly reduced
(see Fig. 16).
The power metallization has been shown to play a crucial role
for the failure mechanism of passivation cracking. Understand-
ing the ratcheting mechanism has led to the introduction of a
layered Al/TiN metallization with a distinctly increased yield
stress. This was a first important step on the way to reach the
zero-defect frontier.
Unfortunately, a multilayer as applied in the simulations
presented above caused some unwanted side effects. In regions
of a high shear stress, i.e., in the corners of very large chips
(e.g., 7.3 × 4.1 × 0.38 mm3 ), cracks were now observed in the
dielectric layers between the underlying Al metallization. Elec-
trical shorts occurred originating from such cracks, which were
filled with an Al material [see Fig. 17(a)]. FEM simulations
showed that, as expected, the shear stress is fully transferred
to the lower metal layers beneath the Al multilayer plate
[see Fig. 17(b)]. Consequently, the shear stress transmitted to
the lower metal lines induced ratcheting there and led to similar
failures as discussed before in the case of passivation. This
effect could be avoided by using a 2× Al multilayer for the
lower metal lines.

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ALPERN et al.: ON THE WAY TO ZERO DEFECT OF PLASTIC-ENCAPSULATED ELECTRONIC POWER DEVICES I
Fig. 10. Stress/strain curves for the 3.5-μm-thick standard single Al layer
at different temperatures. (a) BKIN hardening model [24]. (b) Chaboche–
Armstrong–Frederick model [25], [26].
Fig. 11. Shear stress distribution at −55 ◦ C after (a) 1st and (b) 62nd cooling
down from 150 to −55 ◦ C (1st and 62nd TCs).
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275
Fig. 12. Principal stress S1 at −55 ◦ C at the left edge of a 200-μm-wide
standard 3.5-μm-thick single Al line after (a) 1st and (b) 62nd cooling down
from 150 to −55 ◦ C. (Arrow) Direction of the shear force acting from the chip
edge to the center.
Fig. 13. Principal stress S1 at −55 ◦ C at the right metal edge of a 200-μm-
wide standard 3.5-μm-thick single Al plate after (a) 1st and (b) 62nd cooling
down from 150 to −55 ◦ C. The strong deformation in simulation (b) corre-
sponds to a strong aluminum tilting and passivation cracking, as shown in the
inset (FIB section). (Arrow) Direction of the shear force acting from the chip
edge to the center.
In addition, it turned out that too many layers in the Al power
metallization produced a severe wafer bow, which could not be
handled anymore in production. Therefore, the number of lay-
ers had to be limited to four for the 3.5-μm-thick power metal-
lization and to two for the 0.8-μm-thick lower metal lines. As a
consequence of this compromise, the ratcheting of the 3.5-μm-
thick 4× Al multilayer and the occurrence of passivation cracks
276 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 2, JUNE 2009

Fig. 14. Principal stress S1 in the passivation layer after 1 and 62 TCs (from
−55 to +150 ◦ C) for a standard 3.5-μm-thick single Al layer (yield stress =
100 MPa) and a corresponding Al multilayer (yield stress = 300 MPa). The
temperature was −55 ◦ C.

Fig.16. Passivation cracks after 1000 TCs for the case of a (a) 4× and a
(b) 6× Al multilayer covered by an 800-nm SiNx passivation and a 5-μm PI.

Fig. 17. (a) Cracks in the dielectric layers between the lower Al metallization
beneath an Al multilayer plate. After 1000 TCs, the cracks filled up with an Al
material, leading to an electrical short. (b) FEM simulation revealed the root
cause of this effect. The shear stress is transmitted to the lower metal lines
beneath the Al multilayer (von Mises stress at −55 ◦ C after 60 TCs).

Fig. 15. Al wrinkling of a 3.5-μm-thick Al metallization observed af-
ter 1000 TCs. (a) Single layer. (b) 4× multilayer. (c) 6× multilayer
(Nomarski interference contrast microscopy). The metallization was covered
by an 800-nm SiNx passivation and a 5-μm PI. Because of the small magnifi-
cation, the passivation cracks are not visible here.
were not completely removed. Therefore, the influence of the
MC, PI, passivation, and design must be analyzed in detail to
be able to choose the suitable materials and design. This will be
discussed in Parts II and III of this series of papers.

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ALPERN et al.: ON THE WAY TO ZERO DEFECT OF PLASTIC-ENCAPSULATED ELECTRONIC POWER DEVICES I
ACKNOWLEDGMENT
The authors would like to thank J. Busch for the imple-
mentation and processing of the Al multilayer metallization,
Prof. O. Brüller for the fruitful discussions, C. Bohm for the
Chaboche model of Al, and Dr. E. Lilleodden for the micro-
compression measurements.
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Peter Alpern received the M.S. degree in physics
from Ludwig-Maximilians University, Munich,
Germany, and the Ph.D. degree from the Technical
University Munich, Munich.
In 1984, he was with Siemens AG. In 1987,
he was with the Siemens Semiconductor Division.
He is currently with the Infineon Technologies AG,
Neubiberg, Germany, where he is engaged in quality/
reliability development for the overall system chip
and package.
Dr. Alpern is a member of the German Physical
Society.
Peter Nelle received the B.S. degree in physics from
Rheinische Friedrich-Wilhelms-Universität, Bonn,
Germany, and the Ph.D. degree in physics from
Technische Universität, Berlin, Germany.
In 1985, he was with Siemens AG, Munich,
Germany. Since 2000, he has been with the Infineon
Technologies AG, Neubiberg, Germany. His fields
of activities include the process and device devel-
opment of semiconductor power technologies and
corresponding thermomechanical simulations.
Dr. Nelle is a member of the German Physical
Society.
Endre Barti received the B.S. degree from
Transilvania Technical University, Brasov, Romania,
in 1991 and the Ph.D. degree from the Technical
University, Munich, Germany, in 2003.
Between 1998 and 2003, he was a Scientific
Assistant with the Department of Mechanics and
Material Testing, Technical University Munich,
Munich. Since 2003, he has been with Siemens
Corporate Technology, Munich, where, in the Pro-
duction Processes Department, he has been involved
in several projects with different Siemens divisions
and external companies such as the Infineon Technologies AG.
278 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 2, JUNE 2009
Helmut Gunther received the Ph.D. degree in
physics from the Technical University Munich,
Munich, Germany.
As a member of the University of Giessen,
Giessen, Germany, he worked for several years in
the field of nuclear physics. In 1973, he was with
the Semiconductor Division, Siemens AG, Munich,
where he was engaged in unit process development
as well as process transfer and product qualification.
Since 1983, he has been heading several groups
of equipment engineering, unit process development
and transfer, and production support. In 1998, he became responsible for
the productivity improvement of the Memory Product Group, Siemens Semi-
conductor Division, and, later on, the Infineon Technologies AG, Neubiberg,
Germany. He retired in 2003 and worked afterward as a Consultant in the area
of reliability development for the overall system chip and package until the
beginning of 2008.
Angela Kessler received the M.S. degree in
physical chemistry from Georg-August-University,
Göttingen, Germany, and the Ph.D. degree in phys-
ical chemistry from the University of Regensburg,
Regensburg, Germany, in 1998.
In 2000, she was with Haitec AG, Munich,
Germany, where she performed FEM simulation
and gave CAD training for CATIA. Since 2000,
she has been with the Infineon Technologies AG,
Regensburg, where she has been responsible for
material engineering in the field of power packages,
including the thermomechanical optimization of chip-package systems. Since
2008, she has been a Project Leader in the development of power packages.
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Rainer Tilgner received the Ph.D. degree in atomic
physics from Munich Technical University, Munich,
Germany.
In 1974, he was with Siemens Corporate Devel-
opment Laboratories, where he worked on polymer
physics as well as technology and was concerned
with analytical methods such as thermal waves and
photoacoustics. In 1987, he was with Siemens Semi-
conductor Division. In 1999, he joined the Infineon
Technologies, Neubiberg, Germany, when it sepa-
rated from Siemens Semiconductor Division. Most
of that time, he headed a group concerned with quality and reliability problems
in packaging technology. He retired in August 2008. He is currently a Consul-
tant with Infineon Technologies, where he gives advice as regard to interconnect
problems.
Matthias Stecher received the M.S. degree in elec-
trical and electronic engineering from Virginia Poly-
technic Institute and State University, Blacksburg,
and the Ph.D. degree in electrical and electronic en-
gineering from Rheinisch-Westfälische Technische
Hochschule, Aachen, Germany, in 1994.
Between 1989 and 1994, he was involved in the
development of device and circuit simulation tools.
Since 1994, he has been with the Infineon Technolo-
gies AG, Neubiberg, Germany, where he has been the
Project Manager for several smart power technolo-
gies. Since 2003, he has been involved in the thermomechanical optimization
of chip-package systems and is currently a Technical Advisor in the fields of
power technology and package development. He is the holder of more than
20 patents.