RF High Power Amplifiers For FREIA - ESS: Design, Fabrication and Measurements

FREIA Report 2015/09
October 2015
DEPARTMENT OF PHYSICS AND ASTRONOMY

UPPSALA UNIVERSITY
RF High Power Amplifiers for

FREIA – ESS: design, fabrication
and measurements
Authors: Linus Haapala and Aleksander Eriksson

Supervisor: Dragos Dancila
FREIA, Uppsala University, Uppsala, Sweden
Department of
Physics and Astronomy
Uppsala University
P.O. Box 516
SE – 751 20 Uppsala Papers in the FREIA Report Series are published on internet in PDF format.
Sweden Download from http://uu.diva-portal.org
This report results from a Master thesis conducted at Uppsala University, FREIA Laboratory,
in collaboration with NXP Semiconductors N.V.
F14024
Examensarbete 30 hp
Juni 2014
RF High Power Amplifiers for

FREIA – ESS: design, fabrication
and measurements
Linus Haapala
Aleksander Eriksson
2
Abstract
RF High Power Amplifiers for FREIA – ESS: design,
fabrication and measurements
Linus Haapala, Aleksander Eriksson
Teknisk- naturvetenskaplig fakultet

UTH-enheten The FREIA laboratory is a Facility for
REsearch Instrumentation and
Besöksadress: Acceleratior development at Uppsala
Ångströmlaboratoriet
Lägerhyddsvägen 1 University, Sweden, constructed
Hus 4, Plan 0 recently to test and develop
superconducting accelerating cavities
Postadress: and their high power RF sources.
Box 536
751 21 Uppsala FREIA's activity target initially the
European Spallation Source (ESS)
Telefon: requirements for testing spoke
018 – 471 30 03 cavities and RF power stations,
Telefax: typically 400 kW per cavity. Different
018 – 471 30 00 power stations will be installed at
the FREIA laboratory. The first one is
Hemsida: based on vacuum tubes and the second
http://www.teknat.uu.se/student
on a combination of solid state
modules. In this context, we
investigate different related aspects,
such as power generation and power
combination. For the characterization
of solid state amplifier modules in
pulsed mode, at ESS specifications, we
implement a Hot Sparameter measurement
set-up, allowing in addition the
measurement of different parameters
such as gain and efficiency. Two new
solid state amplifier modules are
designed, constructed and measured at
352 MHz, using commercially available
LDMOS transistors. Preliminary results
show a drain efficiency of 71 % at
1300 W pulsed output power. The
effects of changing quiescent current
(IDq) and drain voltage are
investigated, aswell as the
possibilities to combine several
modules together.
Handledare: Dragos Dancila

Ämnesgranskare: Anders Rydberg
Examinator: Tomas Nyberg
ISSN: 1401-5757, UPTEC F14 024
4
Sammanfattning
Ett av syftena med FREIA-laboratoriet är att utveckla teknik för partikelacceleratorer. I Lund
byggs för tillfället världens ljusaste neutronkälla, den kommer att användas för forskning inom
bl.a. partikelfysik och biologi vilket kan leda till förbättringar inom strålbehandling mot sjukdo-
mar som cancer osv.
Traditionellt så har acceleratorer försetts med effekt från klystronförstärkare, men med stora
framsteg inom högfrekvent LDMOS-teknologi har det de senaste åren blivit möjligt att använda
SSA-förstärkare för att förse acceleratorerna med effekt. En av fördelarna med denna typ av
förstärkare är en minskad risk för att behöva stänga av systemet då reperationer kan göras sam-
tidigt som systemet är operationellt, vilket inte är möjligt med klystroner.
För att maximera effektivitet och minska elkostnader måste LDMOS transistorerna vara matchade
med acceleratorns last. Detta görs med nätverk som kopplas in före och efter LDMOS-transistorerna.
I FREIA-laboratoriet finns en nätverksanalysator som tillåter förstärkarparametrar så som utef-

fekt, effektivitet, linjäritet och förstärkningsfaktor. För att komma upp i samma nivåer på uteffekt
som klystronerna ligger på så kommer flera SSA-förstärkare att behöva kombineras.
Den här rapporten utreder tillvägagångssätt för att designa, tillverka, mäta och kombinera SSA-
förstärkare.
2
Work load
During this thesis work Aleksander Eriksson have worked on design, simulation, construction and
measurement of the R03010 amplifier design, Aleksander have also been in charge of designing
and ordering the heat sinks for all the modules.
Linus Haapala have worked on design, simulation, construction and measurement of the TMM3
amplifier design, Linus have also been in charge of designing and ordering the PCB’s for the com-
bination measurement and the measurement setup.
The 10 kW combined module and perfecting the theory chapter in this report have been a combined
effort from both Aleksander and Linus.
3
4
Contents
1 Introduction 7
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Theory 8
2.1 Microwave Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 The Smith-Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.3 Scattering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 Classes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.2 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.3 Load/Source-Pull Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Simulation and Design 17

3.1 Transistor Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.1 Max Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.2 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.3 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.4 Load-Pull Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.5 Transistor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Designing the TMM3 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1 Smith-Chart Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Momentum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.3 Harmonic Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3 Designing the TMM10i Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3.1 RO3010 - Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3.2 Momentum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3.3 Harmonic Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4 Construction and Setup 30

4.1 Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.1 PCB Manufacturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.2 Heat Sinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.3 Amplifier Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 Hot S-parameter Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.1 External Ports Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.2 DC Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3 Combination Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5 Measurements 36
5.1 The TMM3 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1.1 Hot S22-Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.1.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1.3 Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.4 Different VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2 The TMM10i Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2.1 Hot S22-Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5
5.2.3 Temperatures and Harmonics . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3 Combination Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.1 The 1.25 kW Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.2 The 10 kW Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6 Conclusions and Discussion 48

6.1 Comparing Simulations and Measurements . . . . . . . . . . . . . . . . . . . . . . 48
6.2 Comparing The TMM3, TMM10i and The Modified ESRF Modules . . . . . . . . 49
6.3 The 10 kW Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7 Acknowledgements 50
Acronyms
ADS Advanced Design System
BALUN BALanced to UNbalanced
CST Computer Simulation Technology
CW Continuous Wave
DC Direct Current
DUT Device Under Test
ESRF European Synchrotron Radiation Facility
ESS European Spallation Source
IR Infrared
LDMOS Laterally Diffused Metal Oxide Semiconductor
MTTF Mean Time To Failure
PAE Power Added Efficiency
PCB Printed Circuit Board
PNA Power Network Analyzer
RF Radio Frequency
SSA Solid State Amplifier
UHF Ultra High Frequency
VHF Very High Frequency
6
1 Introduction
1.1 Background
The FREIA laboratory serves as a preliminary evaluation facility for a RF-power system prototype
for the European Spallation Source (ESS). ESS is currently under development in Lund, Sweden.
Once completed, the ESS linear accelerator will generate an average beam power of 5 MW for
acceleration of protons. This proton beam will be used to create the brightest neutron source
ever built, and will provide a research aid in areas such as material science, biology and particle
physics[1]. ESS will use several stages to accelerate the beam, one being a spokes resonator cavity
stage which will be tested at FREIA. The decision of how to power the spokes resonator cavities
is still in process. The choice is between using klystron tubes or Solid State Amplifiers (SSA). The
SSA alternative consists of using many RF-modules in parallel, each delivering roughly 1 kW at
a frequency of 352.2 MHz. To lower the operating costs the RF-modules will need to be reliable
and operate with high efficiency.
FREIA is working in collaboration together with the European Synchrotron Radiation Facility
(ESRF) which is another joint research facility. ESRF is located in France and operates a syn-
chrotron using a very similar SSA system to that which FREIA is designing and testing. The
difference with ESRF’s SSA system is that it runs in Continuous Wave (CW) and each module
delivers 700 W output power instead of ESS’s 1.25 kW. Uppsala University has received one of
ESRFs amplifier PCBs in order to use in the process of learning. The knowledge gained from this
study are used when designing the two in house modules.
1.2 Method
ESRF’s SSA modules operates in a load-pull configuration using NXP’s BLF578 LDMOS transis-
tor, delivering 700 W per module with an efficiency slightly under 70%. ESRF have provided the
PCB’s for one of their SSA modules, these PCB’s are used to reconstruct the ESRF module at
FREIA. The ESRF module is modified to deliver 1.25 kW using NXP’s newer and extra rugged
LDMOS transistor, the BLF188XR.
Two new modules, that unlike the ESRF module operates in common mode are designed in house.
Working in common mode makes the use of BALanaced to UNbalanced converters (BALUNs) un-
necessary, which is good since BALUNs are costly to manufacture and often experience heating
problems. These modules will be designed on Rogers TMM3 and RO3010 substrates. The main
difference between these substrates are the dielectric constant r , which is r = 3.27 for the TMM3
substrate and r = 11.2 for the RO3010 substrate. A higher r value allows the design to be more
compact. These designs, will be referred to as the TMM3-design and the RO3010-design and are
compared to the modified ESRF-module.
During the process of designing a new amplifier, it is important to know the input and output
impedances that the transistor requires for optimal performance. In order to get the transistor to
these impedances, matching networks will be designed and simulated in softwares such as Agilent’s
Advanced Design System (ADS) and Computer Simulation Technology’s (CST’s) Microwave stu-
dio. In FREIA, a Power Network Analyzer (PNA) are available for hot S-parameter measurements
on the modules with capabilities up to 1.5 kW.
7
1.3 Goal
The scope of this thesis is to design, construct and measure the TMM3 and RO3010 designs and
then to compare them against each other as well as the modified ESRF module. To show that
combination is possible, 4 modules using the TMM3 design are constructed and two of them are
combined and measured.
2 Theory
2.1 Microwave Theory
2.1.1 Impedance Matching
When working with high frequencies such as in the Very High Frequency (VHF) and the Ultra
High Frequency (UHF) bands (30 MHz to 3 GHz) the signal wavelength λ is about 0.1 m-10 m.
This means that λ is likely to be as long or even shorter than the system itself. When working with
low frequency voltages, the assumption that the voltage is constant throughout a transmission line
is usually made. But for high frequencies this assumption is no longer valid, as the voltage signal
acts as a wave as it traverses the transmission lines, see figure 1.
Figure 1: When the frequency is high enough and λ ∼ l, the voltage will not be constant throughout
a transmission line. Instead the voltage signal will traverse the transmission line as a wave.
This can cause a variety of phenomenas, depending on the system. For instance, standing waves
can occur throughout the transmission lines. This is a result of the voltage signal being reflected
back from the load. This might cause trouble for any components that aren’t designed to work
with voltages flowing in the reverse direction. Having a part of the voltage reflecting back also
means that this part doesn’t get successfully delivered to the load, which means an overall lowering
of the performance.
The amount of voltage that gets reflected is dependent on the impedance match between the load
and the source. The reflection coefficient is commonly denoted as Γ, and is defined as:
VRef lected
Γ=
VIncident
8
It can be shown that if the load (ZL ) and source (ZS ) impedances are known, Γ can be calculated
by:
ZL − ZS
Γ=
ZL + ZS
To increase efficiency it is important to make sure that as much as possible of the delivered power
is active. It can be shown that, for optimal power transfer to the load, the load impedance should
be ZL = ZS∗ .
It is not always possible to choose the impedance of the load. It is possible to convert the load
impedance using a matching network, which got its name from the fact that its purpose is to match
the load to the source. A matching network consists of components like transmission lines, stubs
and lumped elements. The design process is something that has to be individually performed for
each matching network and the design process is not intuitive.
Designing a matching network with transmission lines, stubs and lumped elements requires un-
derstanding of how they each individually affect the impedance. Using lumped elements is the
most intuitive one, since standard electronic rules apply. Stubs are just a nickname of a shunted
transmission line that branches off from the main transmission line.
Transmission lines however change the impedance of the load just by being there, meaning that
if one would to measure the impedance at the load without. Then measured it again on the same
load with a transmission line in between, the results may differ depending on the dimension and
characteristics of the transmission line, see figure 2.
Figure 2: The impedance, Zin , measured at a load through a transmission line may not be the
same as the impedance measured directly at the load.
If ZL is the impedance of the load connected to one side of the transmission line, and Z0 is the trans-
mission lines characteristic impedance, which can be found in the transmission line’s datasheet,
or calculated using complex formulas. With the wave number β = 2π λ
and the transimission line
length l the resulting Zin can be exactly calculated as:
ZL + jZ0 tan(βl)
Zin = Z0
Z0 + jZL tan(βl)
Knowing this, a skilled engineer can design a matching network that matches the load to any
desired source. But doing it using these formulas would prove to be tedious and time consuming
task. A better alternative when designing a matching network would be to use the Smith-chart,
which gives a graphical interpretation how an impedance changes throughout a matching network.
9
2.1.2 The Smith-Chart
The Smith-chart is a very useful tool when working as a microwave/RF engineer. It allows complex
matching quickly, without requiring any of the complex calculations that otherwise would be
necessary. The Smith-chart might look incomprehensible at first, but it’s all about knowing what
to focus on, and what can be ignored for the moment. The Smith-chart can be seen in figure 3.
Figure 3: The Smith-chart in its full glory.
The Smith-chart can be used to calculate many different things, but for this application it is
sufficient to look at the reflection coefficient Γ and the normalized impedance Z. The reflection
coefficient Γ can be plotted in a complex plane, with the Smith-chart being placed inside the unit
circle |Γ| = 1.
The impedance Z can be read using the lines inside the Smith-chart, with the real part of the
normalized impedance (Re(Z)) being represented by the circles centered on the Im(Z) = 0 axis.
Starting from Re(Z) = 0 for the left part of the Smith-chart and ending with Re(Z) = ∞ at the
right part. The imaginary part (Im(Z)) can be found on the perpendicular semicircles, with the
imaginary part being inductive (Im(Z) > 0) in the top half of the Smith-chart, and capacitive
(Im(Z) < 0) for the lower half. All of this is shown more clearly in figure 4.
10
Figure 4: The Smith-chart and how it can be used to interpret what reflection coefficient Γ and
normalized impedance Z that represent each other.
The Smith-chart is extremely useful for designing a matching network since the impedance seen
when looking into a transmission line moves in a circle in the Smith-chart, centered around the
transmission line’s characteristic impedance. A half signal wavelength ( λ2 ) represent a complete
loop, this is shown in figure 5.
Figure 5: The Smith-chart is very handy if one wish to calculate the impedance at the end of a
transmission line.
In similar fashion, the Smith-chart can be used to see how the line-width, stubs and components
changes the impedance as the voltage is moving throughout the matching network. Once this is
understood, it is possible to plot for example the load impedance ZL of a system and then change
it to whatever impedance that is wanted.
Lets try an example of this, say that we are faced with a load ZL = 50 − j100 Ω that we wish
to match to a source that’s designed to operate optimally when the load is Zs∗ = 12.5 + j5 Ω.
This means that we will need to design a matching circuit that will make ZL look like Zs∗ when
looking from the source. First, lets find both ZL and ZS∗ in the Smith-chart. By normalizing
the Smith-chart around 50 Ω we get a normalized ZL,normalized = 1 − j2 Ω. We then locate the
Re(Z) = 1 circle and the Im(Z) = 2 semicircle in the Smith-chart, ZL will then be found in the
point where these circles intersect, see figure 6.
11
Figure 6: Faced with the task to match ZL to ZS∗ in the Smith-chart, the first thing to do is to
locate these two points in the Smith-chart.
As seen in figure 6, the impedance ZL is located far from the optimal point ZS∗ which the source
requires to operate efficiently. First off, to get to the left side of the Smith-chart a transmission
line can be used. In this case, since we are normalized around 50 Ω and the points are at opposite
sides of the Smith-chart, let’s use a transmission line with an impedance of 50 Ω.
Starting from the ZL point draw a semi circle centered around the 50 Ω point, this will let let us
know how the impedance changes depending on which length of the transmission line we choose.
Lets choose a point Z close to Zs∗ . This will represent the impedance seen at the other side of the
transmission line when looking at the load. Using the Smith-chart in figure 7, we can determine
the length to be l = 0.24 λ. This is done by measuring the angle we have moved on the arc and
remembering that one full circle is equal to l = 0.5 λ
Figure 7: Using the Smith-chart, a graphical representation of how the impedance changes when
adding a transmission line is presented. The impedance of the line determines the center of the
circle arc and the length determines how far on the arc we travel.
The impedance, Z, is much closer to the optimal impedance ZS∗ than our original load impedance
ZL but it is not quite there yet. There is a couple of different ways to move radially in the Smith-
chart, one of these ways is to use an inductor. This report does not explain how the inductor
moves the impedance point in the Smith-chart. However, the interested reader is recommended
to do some research on the admittance circles of the Smith-chart.
12
Figure 8: Using an inductor we can travel the final distance from Z to Zs∗ .
In figure 8 the inductor has been added. The changes in the impedance depends on the value of
the inductor and also how it’s connected. So, by these two steps we have designed a matching
network that makes the load impedance ZL appear as Zs∗ to the source.
2.1.3 Scattering Parameters

Scattering parameters, or [S]−parameters, is a popular way of representing the characteristics of a
system. The [S]−parameters are usually represented as an [m, n]−matrix, with n = m = number
of ports to the system. The [S]−parameters is defined as the relationship between outgoing (Vm− )
and incoming voltage signals (Vn+ ) from the system:
 −    +
V1 S11 S12 · · · S1n V1
V −   S21 S22 · · · S2n  V + 
 2    2 
 ..  =  .. .. ... ..   .. 
 .   . . .  . 
−
Vm Sm1 Sm2 · · · Smn Vn+
Each element of the [S]−parameters is separately calculated as:
Vm− V oltage going out f rom port m

Sm,n = +
=
Vn V oltage going into port n
With Vn+ being the only port with an input signal, and all other ports connected to a matched
load. This is to remove any interference from other ports.
Every system can be described using [S]−parameters and they are also strongly tied to impedances
and reflection coefficients. The Snn −parameter for instance can be related to the reflection coeffi-
cient at port n. In the case of a power transistor, we have a signal entering through port 1, leaving
through port 2. This transition corresponds to S21 which can also be interpreted as the gain of
the system. We also want to avoid any power being reflected at any point, which gives preferably
S11 = 0 and S22 = 0. Since a transistor is an unilateral device (works only in one direction),
there should be no signal going through the transistor in the reverse direction (S12 = 0). So
[S]−parameters for an ideal transistor is:

0 0
[S] = .
S21 0
Balanced [S]−parameters can be introduced to differential systems by defining a differential mode
and a common mode from two unbalanced ports. The differential port is defined as the difference
13
between the two unbalanced ports and the common mode port is defined as the common mode of
the two unbalanced ports, see figure 9.
Figure 9: When working with differential systems, defining balanced ports might be beneficial.
2.2 Power Amplifiers

2.2.1 Classes of Operation
Amplifiers are often divided into different classes of operation with A, AB, B, C being some of
the more common ones. The class of an amplifier is determined from the angle of conduction Θ
which is determined by the transistors bias point, Θ is the time measured in radians for which the
transistor is turned on, see figure 10.
Figure 10: The conduction angle Θ is defined as the part of the voltage signal for which the
transistor is conducting.
14
By lowering the gate bias point VG the conduction angle Θ is decreased. Smaller Θ’s results in
a higher theoretical efficiency for the amplifier, but also less gain. This is because with higher Θ
the longer the transistor’s channel will stay open, leading to higher gain. The losses are increased
because when the channel is open, a DC current related to the bias will flow through, contributing
to the losses but not to the output signal. If the transistor is biased so that the gate voltage
never falls under the threshold voltage (Vth ) an conduction angle Θ = 360◦ is achieved and the
transistor is said to operate in class A. If the gate bias VG is set to be exactly Vth the transistor
only conducts during the positive half of the gate voltage signal, in this case Θ = 180◦ and we
operate in class B. An in between of these two is 180◦ < Θ < 360◦ which is called class AB, this
is what we see in figure 10. If VG < Vth we have Θ < 180◦ and this is class C.
Class B amplifiers have an interesting dynamic where two transistors with reverse polarity can
be used in parallel to complement each other. So each of the two transistors is conducting one
half of the full period each, this is called a push-pull configuration, see figure 11. This is how
many SSA modules operate today , including the ESRF and NXP’s demoboard. This is widely
used because a push-pull configuration obtain the full original wave signal back at the output,
yielding a lower harmonic distortion than a normal class B amplifier. The TMM3 and RO3010
designs that are designed in house doesn’t operate in push-pull, they instead have both transistors
conducting during the same half period. In these designs, harmonic distortion can be a problem,
but if designed correctly, the harmonics can be suppressed in the amplifier’s output network.
Figure 11: Two transistors each operating with close to Θ = 180◦ can complement each very well,
this is known as push-pull configuration.
2.2.2 Stability
A transistor is an active device, which means that it can add power to a signal. Ideally there
shouldn’t be any feedback in a LDMOS transistor, but this isn’t always the truth. Since a tran-
sistor have a high forward gain, having just a small feedback can cause harmful oscillations. This
can potentially damage the transistor or any equipment around it. It is therefore very important
to check for stability when working with any active device.
There are two types of stable devices, conditionally stable and unconditionally stable. A transistor
is said to be unconditionally stable if it’s stable for all load/source impedances where the real part
is positive[3]. When the transistor’s stability depends on the load/source impedances it is said to
be conditionally stable. The transistor is unconditionally stable if K > 1 and |∆| < 1, where K
and |∆| are defined by the transistors S-parameters:
1 − |S11 |2 − |S22 |2 + |∆|2

K=
2|S21 S12 |
∆ = S11 S22 − S21 S12
15
Note that K and |∆| needs to be calculated for all frequencies where an oscillation could occur. If
these criteria aren’t meet for a frequency, the device is conditionally stable for that frequency and
further investigation need to be done to determine which load or source impedances an oscillation
may happen. For a load and source with reflection coefficients ΓS and ΓL the stable area for a
conditionally stable device can be calculated as the load/source impedances for which |Γin | < 1
and |Γout | < 1, where Γin and Γout is defined by:
S12 S21 ρL
Γin = S11 +
1 − S22 ΓL
S12 S21 ρs
Γout = S22 +
1 − S11 Γs
This is usually done by calculating the boarder between the stable and unstable regions, |Γin | = 1
and |Γout | = 1 and determining which region is which by calculation the stability for one impedance
in one or the other. The impedance points that give |Γin | = 1 and |Γout | = 1 will always form a
circle in the Smith-chart, with radius rL for |Γin | = 1 and rs for |Γout | = 1 centered around cL and
cs :
S12 S21
rL =

|S22 |2 − |∆|2

∗ ∗
(S22 − ∆S11 )
cL =
|S22 |2 − |∆|2
and:
S12 S21
rs =

|S11 |2 − |∆|2

∗ ∗
(S11 − ∆S22 )
cs =
|S11 | − |∆|2
2
2.2.3 Load/Source-Pull Analysis

A LDMOS transistor’s characteristics such as gain, efficiency and linearity is highly dependent on
which load (ZL ) and source (Zs ) impedances it is connected to, see figure 12.
Figure 12: A transistors performance will depend on what load and source impedances of the load
and source networks it is connected to.
The load impedance that corresponds to the most beneficial operation conditions (regarding gain or
efficiency e.g.), can be found by sweeping a complex load impedance and then for each impedance,
record the gain, efficiency and other parameters. This process is called a load-pull, the same can
be done by sweeping a complex source impedance, it is then called a source-pull. In power am-
plifiers the load impedance (ZL ) is often the biggest factor to the amplifiers performance, hence
more effort should be given towards the load-pull analysis.
16
Often the load-pull will show that the transistor e.g. will operate with optimal gain for one load
impedance, and optimal efficiency at another load impedance. In this case the engineer should
consider what weight the two performance parameters require for his or hers specific design goal,
then pick a impedance that is suitable for the application.
3 Simulation and Design

Agilent’s Advanced Design System (ADS) is capable of simulating microwave structures. By using
the encrypted BLF188XR transistor model provided by NXP, simulations on the transistor’s be-
havior is possible[5]. Computer Simulation Technology (CST) are used to simulate more complex
structures such as the BALUNs on the ESRF module. One advantage of using CST is that the
S-parameters that you get from CST can be exported to ADS, and then perform simulations on
amplifier level.
3.1 Transistor Level

3.1.1 Max Gain
For S-parameter simulations, ADS comes with a predefined MaxGain tool, which calculates the
maximum gain that can be achieved from the transistors S-parameters. The max gain at 352
MHz are simulated as the total quiescent drain current is swept, see figure 13. As expected the
transistor can operate with a higher gain when the quiescent drain current is increased, explained
in section 2.2.1.
Figure 13: The maximum gain of the transistor is dependent of the quiescent drain current. The
BLF188XR contains two transistors, the IV-characteristics for one of them are plotted above.
3.1.2 Biasing
In order to find good working conditions for the BLF188XR, a study of the biasing is needed.
According to the data sheet, a drain current of 40 mA per drain is recommended, which add up to
80 mA for the whole BLF188XR. In the IV-characteristic of the transistor this current is achieved
17
very close to the threshold voltage, which means the BLF188XR will operate in class B. In figure
13, the maximum gain for this quiescent drain current is found to be roughly 22 dB. In order to
find the gate voltage needed to achieve this, the model of the transistor was studied in ADS. In
figure 14, the drain current IDS is plotted against the gate voltage VGS .
Figure 14: The drain current plotted against the gate voltage with using drain voltage VDS = 50 V .
Here the quiescent drain current is probed for the whole module, with half of that for each drain.
As seen in the figure 14 a gate voltage of 1.508 V is needed to get 40 mA drain current for
the simulations. However when it comes to the physical transistor, this voltage will probably be
different due to the fact that these transistor models often does not include thermal effects. And
of course, there are always deviations in each component.
3.1.3 Stability
The K and |∆| stability factors are simulated in ADS and presented in figure 15. We see that
K > 1 and |∆| < 1 for high frequencies. Lower frequencies below 15 MHz, does not satisfy these
criterias, making the transistor conditionally stable for these frequencies.
Figure 15: The BLF188XR is unconditionally stable for all frequencies higher than 15 MHz.
18
The input and output stability circles are simulated for the conditionally stable region 0-15 MHz
to determine what load and source impedances might cause oscillations, see figure 16.
Figure 16: The stability circles are plotted in a Smith-chart normalized to 50 Ohm for the fre-
quencies for which the transistor is conditionally stable. The largest circles are 1 MHz and the
smallest ones are 16 MHz, the stable region are the one outside the circles. The two curves in the
lower part of the Smith-chart are the simulated impedances of the TMM3 design, located far into
the stable region. The RO3010 have similar impedance values.
Because the change in impedance for a transmission line and capacitor is proportional to λ1 the
matching networks of the TMM3 and RO3010 designs will not transform these low frequencies
far from the outer 50 Ω impedance. Since the characteristic impedance of the transmission lines
is less than 50 Ω the impedance will travel downwards in the Smith-chart, the same goes for the
capacitors. This brings the transistor far into its stable region. The load and source impedances
presented to the transistor are simulated using the TMM3 design, which is plotted as the two curves
in the lower half of the Smith-chart in figure 16, the RO3010 design have similar impedance values.
3.1.4 Load-Pull Analysis

In order to find the source and load impedances that needs to be presented to the transistor for
optimal working conditions load-pull and source-pull simulations are performed. In later versions
of ADS (v2011 or higher) pre made setups are available for these simulations, documentations on
how to use these setups can be found at Agilent’s support center[6].
In LoadP ull ConstP del the delivered power is kept constant, this is done by finding the input
power required for each separate load impedance. This proves to be very useful in our case, since
we aren’t limited to a specific input power and may fine tune it using the pre-amplifier. For a
schematic view of the constant output power load-pull setup, see figure 17.
19
Figure 17: The constant output power load-pull setup determines the optimal load impedance with
the transistor operating in unbalanced mode.
Since the RF-power of the amplifier is higher after the transistor, a well matched output is more
important than a well matched input. Less time will therefor be spent on finding the optimal
match for the input, instead the focus from now on will be on the load side. A rough source-pull
simulation showed that the input impedance of the transistor is roughly ZIN = 0.36 − j0.72 Ω,
this value was later used in the load-pull simulations, the result can be seen in figure 18.
20
Figure 18: The simulation shows the constant Power Added Efficiency (PAE) and constant gain
circles in the Smith-chart for 61 dBm delivered power. From this it is seen that the load impedance
for optimal efficiency at 61 dBm (1.3 kW) delivered power is 0.389 + j0.411 Ω, which yields slightly
above 78 % PAE.
In this application, efficiency is valued higher than gain, so the optimal PAE impedance is selected
as our design impedance. When the amplifiers are being constructed and matched, small changes
can be made to find a preferable impedance with both high gain and efficiency. The optimal
source and load impedances for the BLF188XR for maximum PAE, as well as the PAE at these
loads for a range of output powers according to the simulations can be found in table 1.
PDelivered [W] Optimal ZSource [Ω] Optimal ZLoad [Ω] Maximum PAE [%]
600 0.376 + j0.709 0.271 + j0.599 74.43
700 0.361 + j0.709 0.250 + j0.534 75.78
800 0.329 + j0.712 0.329 + j0.554 76.78
900 0.365 + j0.714 0.338 + j0.509 77.70
1000 0.363 + j0.716 0.341 + j0.464 78.35
1100 0.361 + j0.718 0.338 + j0.419 78.80
1200 0.360 + j0.719 0.336 + j0.397 78.90
1350 0.362 + j0.720 0.353 + j0.368 79.20
1500 0.363 + j0.721 0.457 + j0.338 79.40
Table 1: The optimal load and source impedances for maximum PAE using the BLF188XR in
ADS at different output powers.
The entire process are remade using differential mode operation for the transistor, see table 2. In
differential mode the signal is divided into two transmission lines and the signals are phase shifted
21
by 180 degrees. In this way the two transistors that are in the BLF188XR work one half period
each. One advantage of the differential mode is that the harmonic distortion is lowered by the
fact that even harmonics are canceled which is not the case in a common mode setup. If harmonic
distortions are too high, a harmonic filter could be applied.
Pdelivered [W] Optimal ZSource [Ω] Optimal ZLoad [Ω] Maximum PAE [%]
600 0.729 + j1.413 0.976 + j2.340 74.73
700 0.735 + j1.418 1.150 + j2.296 76.34
800 0.729 + j1.422 1.168 + j2.134 77.42
900 0.726 + j1.425 1.150 + j1.972 78.23
1000 0.731 + j1.430 1.335 + j1.939 78.81
1100 0.728 + j1.434 1.261 + j1.761 79.39
1200 0.724 + j1.436 1.284 + j1.640 79.57
1350 0.723 + j1.439 1.397 + j1.455 79.93
1500 0.727 + j1.440 1.592 + j1.309 79.95
Table 2: The optimal load and source impedances for maximum PAE using a differential setup
simulated using the BLF188XR in ADS at different output powers.
Note that the differential output impedances are roughly four times as large as the one for the
common mode case. This is an expected relationship between differential/common mode that can
be derived using Ohm’s laws.
Most of the times it’s easier to match two impedances if they are close to each other in magnitude
and phase. This could lead one to think that differential mode is better since the load is usually
50 Ω. However, since common mode is so much simpler because a BALUN isn’t needed, it is
commonly preferred. Another advantage is that the use of only one transmission line allows the
matching network to fit on a smaller Printed Circuit Board (PCB) area.
3.1.5 Transistor Waveforms

A harmonic balance simulation was performed on an amplifiers operation at high power. This is
used to simulate the transistor’s voltage and current waveforms when operating at 1 kW output
power directly after the transistor’s drains, in figure 19 simulation results are presented.
22
Figure 19: The voltage and current waveforms simulated at the transistor’s drains.
Since the transistor is operating in class B, the voltage waveform is expected to take the shape of
the upper half of the sinusoidal input signal. However, since transistors are very non linear devices
something else is observed. The voltage signal in figure 19 have a big third harmonic component
which distorts the expected upper half sinusoidal waveform. The current is a clean sinusoidal. The
instantaneous current can reach negative values because of stored charges in parasitic inductances
and capacitances, which make the current flow in opposite direction when they are discharging.
3.2 Designing the TMM3 Module

The TMM3 module are designed on Roger corp’s TMM3 substrate which has a dielectric process
constant of 3.27, dielectric design constant of 3.45, substrate thickness 0.76 mm and copper thick-
ness 70 µm[7]. The design operate in common mode and the biasing are applied via an inductor
which are handmade from copper wire.
3.2.1 Smith-Chart Design

From the impedances that are found in the load-pull analysis, matching networks can be designed
in several ways. As mentioned earlier, the Smith-chart and especially the Smith-chart tool in
ADS is an excellent help when performing this. The impedances that have to be matched are
normalized and plotted in the Smith-chart, and with various components like stubs, inductors and
capacitors, the impedances are matched. In figure 20, the Smith-chart tool in ADS is shown with
an rough version of the output matching network for the TMM3.
23
Figure 20: The Smith-chart in ADS is great when a rough network design is wanted.
However this isn’t very exact and further tuning to the dimensions will be done in later simulations.
The Smith-chart tool should only serve to check what overall structure and dimensions. Once this
is done the networks are rebuilt in an ADS schematic where the dimensions are optimized. This
optimization process can be very time consuming, as it requires many iterations. Luckily, in newer
versions of ADS, there is a optimization tool that addresses this issue. With the optimization tool,
ADS iteratively finds a solution for you, given user specified constraints and goals. In figure 21 a
optimizations setup is shown.
24
Figure 21: Once a rough network design is found by using the Smith-chart tool, the dimensions
are optimized iteratively in a ADS schematic using the optimize tool.
In figure 21, the optimization tool (Optim) is setup to adjust the dimensions of the matching net-
works to achieve the best match (low reflection coefficient S11 ) at a narrow band around the center
frequency (OptimGoal4). A constraint (OptimGoal3) was made for the total length (L1+L2+L4)
to stay under 100 mm. Once the dimensions have been optimized it is recommended to also try
the performance in a harmonic balance simulation, before going any further.
3.2.2 Momentum
In order to validate the networks and its dimensions given by the optimizations, it is realized and
simulated in ADS’s Momentum. Here the micro strips are drawn piece by piece, substrate layers
are defined, and ports are placed. This gives a more realistic simulation of the network than
if transmission line components such as ”MLIN” in figure 21 are used. When the simulation is
done, the network can be exported as a component back to an ADS schematic in order to perform
harmonic balance again, which can be seen in figure 22.
25
Figure 22: After the design has been implemented and simulated in ADS’s momentum, it can be
exported back to an ADS schematic as a component for final harmonic balance simulation. The
figure shows the layout of the new design using the TMM3 substrate.
3.2.3 Harmonic Balance

In the momentum simulations, the feeding networks and DC-blocking capacitors are taken into
account. If they affect the matching network notably, minor adjustments to the dimensions can
be made in a iterative fashion. In figure 23 the harmonic balance simulation results are shown for
the design in figure 22. Simulations show that a P AE = 75.7% is achieved for 1250 W delivered
power.
26
Figure 23: The final designs were simulated in the harmonic balance setup, the new amplifier
designs all simulated more 75 % PAE at 1250 W.
A disadvantage of using lower dielectric constant is that the effective wavelength in the micro
strip becomes large and thus the PCB’s will be larger then with a substrate of higher dielectric
constant. Another way to achieve smaller area is to use lumped components in the matching net-
work. Components however are always in the risk of failure due to heating, which can cause very
costly downtime. The Mean Time To Failure (MTTF) is proportional to the temperature, and a
rule of thumb is that a decrease in the temperature by 10◦ C doubles the MTTF. It is preferred
that the components in the module operate at a temperature of at most 100◦ C.
With a harmonic balance simulation, the voltage and current waveforms at different points in the
design can be plotted. Examples of this behaviour is presented in figure 24.
27
Figure 24: The voltage and current waveforms at the load are in phase with each other when the
design are simulated at 1250 W output power. As the matching network transforms the impedance,
the voltages and currents are also transformed, much like a transformer. This explains why we
see higher voltages than are supplied.
3.3 Designing the TMM10i Module

The RO30130 laminate was used since it has r = 11.2 which is really high. This gives the
opportunity to make really small matching networks which is useful if space is a constraint. The
substrate is provided by Roger Corporation. However, the RO3010 substrate is very soft and since
the PCBs are made by hand, it is hard to construct it without bending it somehow. So after a few
failed attempts of creating an amplifier from the RO3010 substrate, the substrate was changed to
a more stiff substrate. The TMM10i is another Rogers Corporation substrate, it has r = 9.9 and
is very rigid.
3.3.1 RO3010 - Design

The idea behind the design is to have a single transmission line that transforms the impedance
without the use of lumped components. The dimension of the transmission line was found through
using the tuning and optimization tools in ADS. When the optimal dimension where found, the
length and width of the transmission line was rounded to millimeter precision. It was also necessary
to include a DC-block, the transmission line was cut and three DC-block capacitors was put there
so that RF could pass while DC was blocked.
3.3.2 Momentum
The matching network was implemented in Momentum to get more realistic results. The trans-
mission line was widened on one the side closest to the transistor so that the transistor could be
soldered, see figure 25.
28
Figure 25: The RO3010 design of the input and output matching network. The output network is
slightly wider and the input network is longer.
3.3.3 Harmonic Balance

The simulated network from momentum is exported back to ADS and the harmonic balance
simulation gives the following results, see figure 26. The efficiency is 73 % at 1250 W.
Figure 26: A harmonic balance simulation using the RO3010 substrate. The matching networks
are taken from the momentum simulations.
However, since the accordance of simulation and reality isn’t very good, the design was in reality
matching the transistor for too low frequencies and the whole design had to be shortened. The
main fault is probably from the encrypted model of the transistor. And because of the problems of
constructing the matching networks with the RO3010 substrate the TMM10i substrate was used
29
instead.
Because of time constraints, only the output matching network was made with the TMM10i
substrate. For input matching the input network from the TMM3 design is used since this was
known to work properly.
4 Construction and Setup

4.1 Construction
4.1.1 PCB Manufacturing
The costs of ordering a PCB is rather high and and takes a long time to receive an order, instead
a simple technique is used to prototype the designs. First the design is printed on photo paper
which then is laminated onto the substrate. It is is important to clean the substrate thoroughly
in order to get the ink from the photo paper to stick. When the ink is stuck on the substrate, the
remaining photo paper is removed by soaking it in water and soap.
After this is done, the PCB is put into a iron-chloride-liquid which dissolves the copper that isn’t
protected by the ink. When this is done, the ink is removed by using acetone. The remaining part
of the PCB construction is then to make via connections to the ground planes and to add holes
for screws that will be used to attatch the PCB to a heat sink.
4.1.2 Heat Sinks

The PCBs that are constructed needs a heat sink in order to test them. The amplifiers are sim-
ulated to operate with 70-75 % efficiency at 1250 W. During operation they will work with a
duty cycle of 5 %, implying that there is at most 20 W of power dissipated in the amplifier while
running. So in order to keep the temperature of the amplifier at a reasonable level the dissipated
power is cooled off by the water flowing trough the heat sink.
The heat sink also act as a support structure for the PCB so that screws and other components can
be firmly attached where needed. In order to try many different PCB designs without having to
make a new heat sink every time, the heat sink for the TMM3 and R03010 designs is constructed
in a way that allows different sizes of PCBs to be attached. In figure 27 the heat sink is displayed.
30
Figure 27: The heat sink is designed so that different PCBs can be tested.
For the combination measurements, a special heat sink is ordered so that eight amplifiers can be
attached to the same heat sink. The heat sink is constructed so that walls can be added on in
the future to the sides and in between the modules to shield the EM-waves radiating from the
amplifiers, see figure 28.
Figure 28: The 10 kW heat sink is designed to hold 4 modules on each side. With the possiblity
to add walls between the modules for EM-sheilding.
The heat sinks are constructed by the mechanical workshop at Ångström and at Dione Kullager
AB in Uppsala.
4.1.3 Amplifier Modules

Screws are used to attach the PCBs and transistor to the heat sink. The lumped components on
the amplifier is soldered by hand using regular soldering equipment. Screws are used since it is
easy to remove or change parts of the amplifier which is not the case if the PCBs and transistors
are soldered onto the heat sink.
Once the transistor and PCB have been firmly attached to the heat sink with screws, connectors
for the input and output, biasing and as well as the water hoses are attached to the module. The
two complete amplifier modules can be seen in figure 29 and figure 30.
31
Figure 29: The TMM3 module once everything is mounted together.
Figure 30: The TMM10i design. For the input part it’s utilizing a copy of the TMM3’s input
network.
4.2 Hot S-parameter Measurement Setup

4.2.1 External Ports Setup
To measure S-parameters a Power Network Analyzer (PNA) is used, this is a sensitive equipment
which would brake from the high power it would receive if its ports would be directly connected to
the amplifier modules. To circumvent this, external ports are used, adding plenty of attenuation
to any power signal before it enters the PNA’s ports. The setup used to achieve this is presented
in figure 31.
32
Figure 31: A network of passive components forms external ports which are used to measure high
power signals.
The network utilizes three different kinds of passives: the Directional Coupler are used to create
external ports and allows measurement of the power entering and exiting the amplifier ports,
Circulators are used as protection to make sure that reflections do not go back and destroy any
sensitive components such as the pre-amplifier. Attenuators are used to lower the power of any
high power signal before it enters the PNA’s ports.
In figure 31, S3 supplies through the pre-amplifier the desired input power at the drive frequency
352 MHz. S1 and S2 is attached at the amplifier input and output such that the S-parameters S12
and S22 can be measured between 340 and 365 MHz. The network analyzers (R1) measures the
power going into the amplifier, (A) measures the reflection back from the amplifier. (B) measures
the power out from the amplifier and port 4 (R2) measures the power going into the amplifier
(from the alternative source). The four physically measured ports can then be combined to calcu-
late the S-parameters of the amplifier, with R1 & A representing port 1, and B & R2 representing
port 2.
Before any high power measurements were made all the passive component’s S-parameters were
measured and imported into ADS. Simulations on the output and input passives networks were
performed as confirm that no more than <0 dBm enters the network analyzers ports. Figure 32
dispalys the input passive network with the applied port definitions.
Figure 32: The port placement that was used during the simulations of the input passives network.
Given the port definitions in figure 32, the simulation results in figure 33 can be interpreted.
33
Figure 33: The vital S-parameters of the input passives network.
The S-parameters at 352 MHz in figure 33 show that there is very little losses going through the
network (S11 close to 0 dB), which is a good sign. But more interesting is the S31 and S42 , which
both simulate to be -55 dB. Since the total input power used will be roughly 40 dBm, we can
conclude that p3 and p4 (which goes to the network analyzers ports 1 & 2) will at most receive
-15 dBm. Since S41 and S32 are negligible small (<-80 dB) we know that the directional coupler
is doing its intended purpose, and making sure that p3 and p4 only measures the powers in the
intended directions.
The same investigation were also made for the output passives circuit, in this case the port
definitions in figure 34 were used.
Figure 34: The port placement that was used during the simulations of the output passives network.
Simulations were made and the S-parameters are presented in figure 35. The most important
S-parameters are the SX1 ones, this is because there will be a lot of power at the amplifier output
(port 1), which could easily cause harm if misdirected. The SX1 parameters are presented in a
separate graph in figure 35.
34
Figure 35: The interesting S-parameters of the output passives network is presented. S21 is close
to 0 dB while the SX1 parameters are less than -60 dB.
The S-parameters at 352 MHz in figure 33 shows that most of the power entering at p1 will be
delivered to p2. This is favorable, since we want the power coming from the amplifier to get
delivered to the load, and the reason we have the alternative source attached at p5 is for S22
measurements. There will be roughly 60 dBm at the amplifier output (port 1), and with at least
60 dB attenuation to all PNA ports, at most 0 dBm, or 1 mW of power will be entering its ports.
Which is low enough for the PNA not to take any damage.
4.2.2 DC Current Measurement

To get an accurate reading of the drain efficiency, an accurate measurement of the DC-current
at the drain(s) are needed. Two 60 A/60 mV current shunts are connected in series on each of
the drain voltage cables (only one is used for the modules operating in common mode). A pair of
tabletop multimeter are used to measure the average voltage drop over the shunts, see figure 36.
Figure 36: A picture of the current shunts on the left and the table top multimeters used to measure
the voltage drop over each of them in the right most picture.
The voltage drop over the shunts are then used to calculate the currents flowing through them
using Ohm’s law.
35
The drain efficiency ηD inside the pulse is calculated from the measured DC currents by
100 × PLoad
ηD = h i ,
IDC −IDq
D
+ IDq VD
where D is the duty cycle, VD the drain voltage, IDq the total quiescent drain current for both
transistor drains, and PLoad the power delivered to the load. This formula only works when
the drain currents are equal to each other in magnitude, which they are for the AN10967 mod-
ule. If the two drain currents differ more than a couple of percent (5-10 %) from each other the
amplifier probably isn’t very well balanced, which will decrease the amplifiers overall performance.
4.3 Combination Measurement Setup

An alternative setup is used for measuring combination of the modules. Instead of using the
PNA’s internal source, a signal generator is used. Power meters are connected before and after
the amplifier to measure input and output power. A big attenuator of 30 dB attenuation is
connected at the output to lower the power level before the output power meter, see figure 37.
The input signal is split equally just before the amplifiers and similarly combined just after the
amplifiers. The components that splits and combine were bought online since it would have been
to time consuming too build our own.
Figure 37: An alternative measurement setup are used for the combined measurements.
It was noted that the power splitters and combiners that are used have a lot of losses, roughly
30 % power loss when measuring through it without the amplifier modules. The measurements
done are only to show that combination of the modules is possible, for any practical application
an improvement in the splitter and combiner is recommended.
5 Measurements
5.1 The TMM3 Module
The first measurements of the TMM3 module are far from the simulation results. Changes had
to be made on the matching networks, mainly the matching capacitors. The simulations are still
36
usable for understanding and to find trends, but any value and position in this simulated network
may not be an accurate representation of its real life counterpart. The output matching network
for instance, had 2x20 pF located 48 mm from the transistor during simulations. For real mea-
surements however, this had to be changed to a single capacitor of 27 pF roughly 18 mm from
the transistor, measuring to the center point of the capacitor. The cause of these differences is
probably due to the encrypted BLF188XR transistor model that are used in the simulations.
5.1.1 Hot S22-Parameters

The hot S22 and S11 are measured with a 25 MHz frequency sweep around the drive frequency for
each of the output powers, see figure 5.1.1.
Figure 38: A frequency sweep of the hot S22 and S11 parameters of the TMM3 design when it’s
delivering 600 W, 1050 W and 1250 W to the load plotted into the Smith-chart. In the bottom
right Smith-chart, the S22 -parameter at 352 MHz is plotted for every measured power, as to present
its path through the Smith-chart.
The input S11 parameter is well matched with a input reflection coefficient of roughly -18 dB for
all measured powers. The input impedance of the transistor does not vary much with the output
power, which is seen by the fact that S11 only changes slightly, staying matched for all output
powers. The S22 -parameter however changes alot when power is increased. It starts close to the
outer circle Re(Z) = 0 in the Smith-chart for low powers, when the power is increased S22 starts
37
moving through the Smith-chart, passing through the center. As it passes through the center of
the Smith-chart the amplifier starts entering compression, this is when the amplifier is operating
at its highest efficiency.
If the matching capacitor in the output matching network is moved away from the transistor, the
S22 -parameter will move quicker through the Smith-chart and the amplifier will reach compression
for lower output powers. In a similar manner the amplifier will be matched for even higher output
powers if the matching capacitor is instead moved towards the transistor. This can be used to
tune the amplifier to a desired output power.
5.1.2 Performance
The TMM3 module are measured with output powers up to 1300 W. In figure 5.1.2 the measured
gain and efficiency are presented for all measured power levels.
Figure 39: The efficiency and gain as a function of output power for the TMM3 module. It
operates at 71 % efficiency with 2 dB gain compression at 1250 W output power.
The amplifier’s temperature is measured using an IR camera[8]. This showed that the tempera-
tures only increases by a couple degrees celsius higher than room temperature, reaching 30 ◦ C.
A water flow of roughly 8 l/min are used to keep the heat sink from heating up. The thermal
resistance is calculated to roughly Rth = 0.25 ◦ C/W. An IR-image of the TMM3 module at 1250
W output power with IDq = 40 mA is presented in figure 5.1.2.
38
Figure 40: An IR camera are used to monitor the temperatures of the transistor, bias inductor
and the matching capacitors. For the TMM3 module, temperatures due to heating peaked at 30 ◦ C
at the transistor.
5.1.3 Harmonic Distortion

If the amplifier has a high harmonic distortion in the output signal, a big part of the power is
lost to the higher harmonic which lowers the overall efficiency of the amplifier. This is highly
noticeable while the final fine tuning of the output matching capacitor are being made, as a small
change in position/capacitance will not affect matching of the fundamental 352 MHz tone. A
larger difference will be made for the matching of higher frequencies, and when these become
unmatched the efficiency is observed to increase. In figure 5.1.3 the spectrum of the TMM3’s
output power signal is presented.
39
Figure 41: A picture of the spectrum of the output power signal shows a low second harmonic 38
dB below the fundamental.
Normally the first harmonics are the strongest ones, meaning usually only the first and second
harmonics are taken into consideration. The spectrum analyzer only provide the spectrum up
to 1 GHz, so only the power of the first harmonic are measured to 38 dBr. But given the high
efficiency of the device, the third harmonic (at 1056 MHz) should be very low as well.
5.1.4 Different VD
Measurements are also made using alternative drain voltages VD . 50, 52 and 55 V are measured
up to 1300 W output power, in figure 5.1.4 the gain and efficiency of these measurements are
presented.
40
Figure 42: The TMM3 module are measured with VD set to 50, 52 and 55 V.
The module reaches higher powers before entering compression when higher VD ’s are used. This
also lowers the efficiency slightly for lower powers. This characteristic can be understood by re-
membering that the output power can be written as Pout = VD ID , which makes it clear that if VD
is increased, Pout will increase proportionally.
Possible usages for this could be to implement a variable VD , which would allow the amplifier to
operate at high efficiency for a wider range of output powers. This would be a big advantage for
systems with a big peak-to-average ratio, as the amplifier will operate with highest efficiency only
when pushed into saturation. A variable VD would allow the system to change for which output
power the amplifier reaches saturation. However, what effects this might have on the transistor is
unknown and further investigation would have to be done before any conclusions can be drawn.
5.2 The TMM10i Module

The TMM10i module was designed to use without lumped components but since simulations
didn’t match reality, two capacitors had to be used in order to match the amplifier. The sizes of
the capacitors are 33 and 8.2 pF, and the brand is ATC800B.
5.2.1 Hot S22-Parameters

The hot S-parameters were measured with an IDq of 40 mA. In figure 5.2.1, the hot S11 and S22
parameters are plotted in the Smith chart for different output powers of the module. Note how
much the biasing affect the S-parameters. With the drain voltage on, impedance travels almost λ4
in the Smith chart.
41
Figure 43: A frequency sweep of the hot S22 and S11 parameters when the amplifier is delivering
700 W, 1100 W and 1250 W plotted into the Smith-chart. The effect of biasing on the S-parameters
is also shown in the upper Smith charts. In the lower right Smith chart, S22 ’s movement for 352.2
MHz is plotted. As S22 passes close to the matched middle the gain reaches maximum and when
it passes the amplifier starts to go into gain compression.
When the amplifier reaches the 1 kW level the S22 passes trough the middle of the Smith chart.
S11 is a fairly good match for lower output powers and at 1250 W it reaches -30 dB return loss.
5.2.2 Performance
The TMM10i design achieved an output power of 1250 W with an efficiency of 69.1 % at IDq =
40 mA. This result together with the effects of changing IDq is presented in figure 5.2.2. The gain
increases and efficiency decreases if IDq is increased, with a gain compression of roughly 2 dB at
42
1250 W output power.
Figure 44: The performance of the TMM10i design with different IDq values.
The decrease in efficiency is because of the fact that the amplifier moves closer to class A when
the IDq is increased since the conduction angle is increased.
5.2.3 Temperatures and Harmonics

It is important that the amplifier does not get too hot during operation. The temperatures of
the amplifier is studied with a IR-camera and an IR picture of the amplifier can be seen in figure 45.
Figure 45: An IR-picture of the TMM10i amplifier, the part that gets most heated are the capacitors
in the output matching network.
The capacitors in the output matching network are the components that get most heated, reach-
ing a temperature of 58◦ C. This temperature is higher than expected since the amplifier is only
43
running at a duty cycle of 5 %. However, the capacitors are rated for more than 100 ◦ C so for
this pulsed application the temperature is acceptable.
With a spectrum analyzer, the power in the second harmonic can be studied. The second har-
monic is at 704 MHz and is preferably very low since efficiency is lost otherwise. According to the
spectrum analyzer that was used, the second harmonic was at -50 dB relative to the first harmonic
which is enough for not affecting the efficiency.
5.3 Combination Measurement

5.3.1 The 1.25 kW Modules
For the combination measurements to work, a requirement is that all amplifier modules have close
to the same gain and phase, which practically means you can not mix different amplifier designs.
Instead of the TMM3 substrate, the more common RO4350B substrate by Rogers is used. The
only difference is the increase in the drain voltage to 55 V instead of 50 V. The combination
measurements starts with two modules, although 9 are manufactured. PCB’s are manufactured
by Cogra Pro and the components are soldered by hand at FREIA and attached to the heat sink,
see figure 5.3.1.
44
Figure 46: The combination measurement PCB’s are manufactured by Cogra Pro, heat sink by
Dione, while soldering and mounting is done by hand in FREIA.
Before any combination measurements are done, each amplifier module are measured separately
to check the performance of the four best modules. The modules differ roughly 2 % -units from
each other in efficiency and roughly 0.6 dB in gain, see figure 5.3.1.
45
Figure 47: Four 1.25 kW modules are constructed and mounted onto the 10 kW heat sink. They
are measured separately and the variations regarding gain, efficiency and phase is monitored.
The phase of S21 now needs to be taken into consideration. Even if the modules use an identical
design, variations are still possible. These variations are compensated for by adding cable length
to add phase for some of the modules. The measured phase of the four modules is presented in
figure 5.3.1.
Figure 48: The phase difference of the four best amplifier that were constructed for combination.
46
The four module differ with less then 5◦ at full power, which is better than expected. But there
is more variance for lower output powers, with as much as 15◦ phase difference. This will cause
a slight decrease in output power and therefore an overall decrease in efficiency at these power
levels.
5.3.2 The 10 kW Module

The heat sink have capabilities to hold 8 amplifiers, which together should be able to reach 10
kW output power. To run the module at full power a pre-amplifier that can provide 100-150 W
is needed to supply the input power. Low loss eight way power splitters and combiners will be
developed in the future to maximize the modules efficiency, for this first combined measurement
only a two way power splitter and one two way power combiner were available. The power splitter
combiner are measured using the PNA and they have roughly 1.5 dB insertion loss, meaning
roughly 30 % of all power will be lost in the combination. The power splitter and combiner
are only used to show that the amplifier modules can be combined to reach higher power. The
combination result of module 8 and 9 is shown in figure 5.3.2.
Figure 49: Module 8 and 9 are combined and the gain and efficiency are measured up to 1700 W.
The high losses in the combination is the main cause for the low efficiency and power.
In figure 5.3.2 the modules are measured together up to 1700 W output power with an efficiency
of slightly below 50 %. The main reason for this low output power and efficiency is the very high
insertion loss in the power combiner. If you account for these losses and calculate the expected
results using an ideal combiner you get 2.4 kW output power with 70 % efficiency, which is what
two modules is expected to deliver.
47
6 Conclusions and Discussion
It has been presented to be possible to eliminate the even harmonics which was one of the concerns
when using single ended designs. The advantage of having single ended designs is the simplicity
that is obtained, neither BALUNs and few lumped components are needed. The BLF188XR has
demonstrated to be able to deliver more than 1300 W of power while maintaining roughly 70 %
efficiency.
6.1 Comparing Simulations and Measurements

Simulations and reality never yield the same results, in this case the difference is big enough that
the matching capacitors in the input and output matching network needs to be changed both
in size and position. The culprit for this inaccuracy is assumed to be the encrypted BLF188XR
model, which seems not to be very accurate for these powers and frequency. However, once the
matching capacitors are adjusted similar performance is seen, see figure 6.1 for a comparison in
gain and efficiency between simulations and reality for the TMM3 design.
Figure 50: Measurements of the TMM3 module compared to the harmonic balance simulation.
In simulations, slightly higher efficiency is achieved at full power, roughly 75 % compared to

the measured 72 %. The simulations also show roughly 2 dB lower gain. This pattern can
be explained by observing the constant gain and constant efficiency circles in figure 18. In the
simulations, the load impedance presented by the output matching network is probably slightly
closer to the efficiency maximum, hence further away from the maximum gain.
48
6.2 Comparing The TMM3, TMM10i and The Modified ESRF Mod-
ules
The two in house amplifiers are compared to the modified ESRF amplifier in figure 6.2. The
TMM3 amplifier achieved the best efficiency and also had low temperatures when operated at full
power. The TMM10i amplifier had a reasonable efficiency at 69.1 % at full power, however the
operating temperatures are more than wanted. One advantage of the TMM10i amplifier is that
it’s much smaller than the rest.
Figure 51: The two in house designed amplifiers are compared to the modified ESRF amplifiers.
6.3 The 10 kW Module

In figure 5.3.2 two modules are combined and measured up to 1700 W combined output power.
For the combination a combiner with very high insertion loss are used (1.5 dB or 30 %). New
power combiners will be designed by FREIA, aiming towards 0.1-0.2 dB (or 5 %) insertion loss.
Once the improved combiner have been developed the 10 kW module will be able to deliver its
full 10 kW output power.
In the future, even higher power measurements can be foreseen as multiple 10 kW modules that
can be combined to 400 kW which will be the full power of one of the RF-towers at ESS once
construction is complete. The effects of running the amplifiers a long time will also have to be
examined as there are possibilities the performance will change over time.
49
7 Acknowledgements
We would like to take this space to thank the people involved. Vitaliy Goryashko, Maja Olvegård,
Roger Ruber, Anders Rydberg, Rolf Wedberg, Lars Hermansson and everyone else at the FREIA
group for the support and help received while working with this project as well as allowing us
access to their facilities. ESRF’s Michel Langlois and Jorn Jacob for providing the ESRF module’s
PCB as well as some feedback. A big thanks to Sone Södergren at the Ångström workshop for
all of his help during the heat sink construction. We want to thank Uwe Zimmermann for all the
help with pcb-construction and much more, and of course a special thanks goes out to Dragos
Dancila who provided us with excellent support during this project.
References
[1] S. Peggs, “Conceptual Design Report, ESS-2012-001, 2012.
[2] http://europeanspallationsource.se/30-times-brighter-today
[3] http://www.microwaves101.com/encyclopedia/kfactor.cfm
[4] Anritsu, “Hot S22 and Hot K-factor Measurements”, Application Note 11410-00295.
[5] http://www.nxp.com/products/mosfets/rf_power_transistors_ldmos/broadcast_ism/
0_500_mhz_hf_vhf_ism/BLF188XR.html
[6] http://edocs.soco.agilent.com/display/ads2011/About+Load+Pull+DesignGuide
[7] http://rogerscorp.com/documents/728/acm
[8] FLIR, “FLIR i-Series”

http://www.flir.com/uploadedFiles/Thermography_USA/Products/Product_
Literature/flir-i-series-datasheet.pdf
50

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FREIA Report 2015/09

DEPARTMENT OF PHYSICS AND ASTRONOMY

RF High Power Amplifiers for

Authors: Linus Haapala and Aleksander Eriksson

RF High Power Amplifiers for

Teknisk- naturvetenskaplig fakultet

Handledare: Dragos Dancila

I FREIA-laboratoriet finns en nätverksanalysator som tillåter förstärkarparametrar så som utef-

3 Simulation and Design 17

4 Construction and Setup 30

6 Conclusions and Discussion 48

BALUN BALanced to UNbalanced

CST Computer Simulation Technology

DUT Device Under Test

ESRF European Synchrotron Radiation Facility

ESS European Spallation Source

LDMOS Laterally Diffused Metal Oxide Semiconductor

MTTF Mean Time To Failure

PAE Power Added Efficiency

PCB Printed Circuit Board

PNA Power Network Analyzer

SSA Solid State Amplifier

UHF Ultra High Frequency

VHF Very High Frequency

Figure 3: The Smith-chart in its full glory.

2.1.3 Scattering Parameters

Vm− V oltage going out f rom port m

2.2 Power Amplifiers

1 − |S11 |2 − |S22 |2 + |∆|2

∆ = S11 S22 − S21 S12

2.2.3 Load/Source-Pull Analysis

3 Simulation and Design

3.1 Transistor Level

3.1.4 Load-Pull Analysis

3.1.5 Transistor Waveforms

3.2 Designing the TMM3 Module

3.2.1 Smith-Chart Design

3.2.3 Harmonic Balance

3.3 Designing the TMM10i Module

3.3.1 RO3010 - Design

3.3.3 Harmonic Balance

4 Construction and Setup

4.1.2 Heat Sinks

4.1.3 Amplifier Modules

4.2 Hot S-parameter Measurement Setup

4.2.2 DC Current Measurement

4.3 Combination Measurement Setup

5.1.1 Hot S22-Parameters

5.1.3 Harmonic Distortion

5.2 The TMM10i Module

5.2.1 Hot S22-Parameters

5.2.3 Temperatures and Harmonics

5.3 Combination Measurement

5.3.2 The 10 kW Module

6.1 Comparing Simulations and Measurements

In simulations, slightly higher efficiency is achieved at full power, roughly 75 % compared to

6.3 The 10 kW Module

[8] FLIR, “FLIR i-Series”

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