IIU SERVICE MANUAL

GENESIS II /MEGA DRIVE II

(PAL-B/1/G, RGB)

NO. 001-1

ISSUED AUGUST, 1993

SUPPLEMENT
The specifications of IC1 on page 16
are corrected as follows.

Sega Enterprises, Ltd.

IC1 16/32-Bit Microprocessor
IC MC68HCOOOFN8 IC HD68HCOOOCP8
• Top View & Pin Layout • Signal Description

~lmlm
l< 0 0 ICI'J o - C\1 M -.::- !,() CQ ,.... en "' o-N
- - -
~~~~0000000000000
ADDRESS BU s
VCC(2)
.)A2 3-Al
OATCK 013 GND(2)
BG 014 DATA BUS
CLK
BGACK 015 Dl 5-DO
BR GNO
V,-
AS
CLK
GND FCO R/W
GNO
NC
HALT
RESET
PROCESSOR
STATUS
{ FCl
FC2
UDS
IDs
DTACK j
ASYNCHRONOUS
>BUS CONTROL
MC68HCOOO
VMA
E
VPA ,._ E BR .....
M6800 BUS
PERIPHERAL VMA BG ARBITRATION
CONTROL VPA BGACK CONTROL

BERR IPLO
SYSTEM
CONTROL
{ RESET
HALT
IPLl
IPL2 } INTERRUPT
CONTROL

• Description

No.jPin Name! 1/0 I Function No.!Pin Namejl/0 I Function No. Pin Name 1/0 J Function
' '
1 I D, I
23 YPA I Vaild Peripheral Address 46 A,5
2 i D3 24 I BERR I I Bus Error 47 A,s
3 i Dz I/0 Data Bus 25 IPL, 48 A!7
4 ! 0 Address Bus
' D, i 26 IPL '
I Interrupt Control 49' A,s
5 I Do 27 IP"'Lo so Arg
6 AS IO Address Strobe 28 FC2 51 Azo
7 I UDS 0 Upper Data Strobe 29 FC 1 0 Processor Status 52 Yee - Power Supply
8 LDS .0 Lower Data Strobe 30 FC0 53 Az1
9 II R/W iO Read/Write 31 N.C - 54 Azz 0 Address Bus
Data Transfer 32 AI 55 AZ3
IO DTACK I Acknowledge 33 Az 56 Yss - GND
11 BG .o I Bus Grant 341 A3 57 Yss
12 BGACK i I Bus Grant Acknowledge 35 A4 58 DJ5
13 I BR I I Bus Request 36 A5 59 DJ4
14 Vee - IPower Supply 37 As 60 DJ3
1s I CLK I Clock 38 A7 61 DJz
16 i Yss_j _
GND
39 As
0 Address Bus
62 Dll I
17 Yss I 40 Ag 63 Dw I/0 Data Bus
18 NC - Not Connected 41 Aw 64 Dg
19 HALT 1!0 Halt 421 All 65 Ds
20 RES II!O Reset 43 A12 66 D7
21 YMA 10 Vaild Memory Address 44 AJ3 67 Ds
22 E iO Enable 45 A14 I 68 D5

2
 Differences between MEGA DRIVE and MEGA DRIVE 2
e Electrical Components Note: For components marked 0~), components equivalent to those listed and made
by other companies can also be used.

Component MEGA DRIVE MEGA DRIVE2 I Remarks

I
MAIN CPU MC68000 DIP C*) HC68HCOOOFN8PLCC(*) Package changed.

SUB CPU Z80A DIP Z84C0006 QFP ( *) Package changed.

VIDEO DISPLAY PROCESSOR CUSTOM CHIP YM7101

BUS ARBITER CUSTOM CHIP

CUSTOM CHIP FC!OOI Integrated into one chip.
UPD92271 GD-00 I

FMSOUNDSOURCE YM2612
RGB ENCODER MB3514 Same as on left
REGULATORIC MA7805UC C*) UPC7805HF C*)
OPAMP LM358 DIP
LM324 SOP C*)
HEADPHONE AMP CXAI034P Integrated with op amp.
MEMORY FOR MAIN CPU TC51382-12 DIP C*) TC51832AFL-IO SOP<*) Package changed.
MEMORY FOR SUB CPU KM6264BL-12 DIP600 <*) KM6264BLG-10 SOP C*) Package changed.
MEMORY FOR VDP UPD41264V-12 C*) Same as on left
OSCILLATOR OSC 53. 203424M20PPM (*) Same as on left
SUB BOARD FOR DC JACK Yes No Integrated into main board.
SUB BOARD FOR Yes No As the headphone jack is
HEADPHONE JACK omitted.

e Features
Item MEGA DRIVE MEGADRIVE2 Remarks
HEADPHONE JACK Yes No
HEADPHONE VOLUME Yes No
RF OUT/CH SWITCH Yes No Integrated with RF unit.
POWER SWITCH Slide switch Push-button
DC JACK Pin plug for DC/NP CONN DC JACK Changed as the AC adapter
EIAJ 3 HEC31 00 has been changed.
RESET SWITCH Tact push buuon Same as on left
AC ADAPTER 1.2 A 0.85A Same as for MASTER
SYSTEM II.
 Differences between GENESIS and GENESIS 2
e Electrical Components Note: For components marked (*).components equivalent to those listed and made
by other companies can also be used.

I
Component I GENESIS GENESIS 2 Remarks
MAIN CPU MC68HCOOOFN8 C*) Same as on left(*)
SUB CPU Z80ADIP Z84C0006 QFP Package changed.
VIDEO DISPLAY PROCESSOR
BUS ARBITER CUSTOM CHIP FC1004 Same as on left Integrated into one chip.
FM SOUND SOURCE
RGB ENCODER CXA1145M-16 Same as on left
REGULATORIC UPC7805HF Same as on left
OPAMP LM324 Same as on left
HEADPHONE AMP LM324 Same as on left Integrated with op amp.
MEMORY FOR MAIN CPU TC51832FL-IO C*) Same as on left
MEMORY FOR SUB CPU MB8464A-80 C*) Same as on left
MEMORY FOR VDP UPD41264V-12 C*) Same as on left
OSCILLATOR XTAL OSC 53.693175 (l~() Same as on left
SUB BOARD FOR I Yes No I As the headphone jack is
HEADPHONE JACK omitted.

e Features
Item GENESIS GENESIS 2 Remarks
HEADPHONE JACK Yes No
HEADPHONE VOLUME Yes No
RF OUT/CH SWITCH Yes No Integrated with RF unit.
POWER SWITCH Slide switch Push-button
DC JACK Pin plug for DC/NP CONN DC JACK Changed as the AC adapter
EIAJ 3 HEC31 00 has been changed.
RESET SWITCH Tact push button Same as on left
ACADAPTER 1.2 A 0.85A Same as for MASTER
SYSTEM II.
 D I F FERENCE S BETWEEN V e r . 0 AND V e r . 1
FOR MEGA DRIVE 2/GENE SIS 2

1) Schematic Diagram
ME G A DR I V E 2 I G E N E S I S 2 (Ver. 0) ME G A DR I V E 2 I G E N E S I S 2 (Ver .1)
( IC2&3 )
r--' ( IC2 )
..,
.,. .. Tr.l>
v

..••
•o
IIOI' 101
v v v A1 102
.,AO 00 AO 00

..••••
103

.. Y--
01 01
••
., 02
03
v v ••
., 02
03 A4
104
lOIS
4
:r- 04 AIS toe

..••
04
v oo oo All 107
••A7·~
.....
Ae
08
07 A7

....,•••
OB
07
.7
••
""
••o
toe
108
1010

....., AlO 1011

AtO

..."'"
•u
Atl 1012
ua 1013
1014
10111

.-
IU.SO RO. ...., "0 10111
~1':0. C[
C[
.
~
~ ...
11£. ~
"-
UliS. I.Um/IU.IJ.
LWR L.O~/Rfi'SH
~
....... LHI>8:!1!3

~o•••,.-•
y~:c
~uno
~~
~>
,, 3

HOT l:.,llO

~
(IC7&8) I
(I C 7 )

;
IC7
AO I/01 11 ADO
A1 I/02 ;'"
...
A2
A3
I/03
I/04
II BOO
. A~
AS
•7
BI/01
BI/02
SI/03
SI/04
IC7
ac_ AD BIOi
B&lL
~OE
"-
SCI!:
~ ..
u
••
.3

•II
••A7
SI02
SI03
SI04
SIOII
sroe
SI07 t: f-- ~
UPD41264 ZIP sroe
c4 AAS:
ICII Wl/I01 iii
AD
At
A2
I/01
I/02
I/03
..
Arl4 W2/I02
W3/I03
WA/I04
N!l/1011
___$;&a_
EU/~
W!I/W!
"
A3
44
Al5
I/04
BI/01 " .,,.
Nll/1011
N7/I07
>fll/108
...
&. ""
3lf iEO
All III/02
A7 SI/03 M!IHIIAC8S4
SI/OA

r~
UPDA12e4 ZIP

2) Circuit Board Diagram

·See the attached.

(J (VL '--;

r/;~ I;/) r0/L!-j

 ----~-----

MEGA DRIVE 2/GENE.S IS 2 (Ve r. 0 )

c._··
~ ''
,;.~,:;,l'

~··~~0

PC BQ-,MD2 VAO PAL

u
 i) (\·.·.~-
, .·. e 1"" . 1)

( l j /// l r 1' · J >t; '

. :...:.--
Flat Package IC Removal

(1) Use a hot-air IC unsolderlng machineto remove the flat package lC.

Pin of flat
~ Nozzle
packaQe IC

Circuit
board
(2) Keep a space of approx. 1-2 mm between the lC remover's nozzle and flat package lC.

1 mm- 2 mm

(3) After 20-30 seconds, the solder starts to melt; use tweezers to remove the IC.

* The time required to melt the solder depends on the diameter of the
nozzle.

(4) After removing the lC, use the soldering iron and solder removal mesh wire to absorb the solder remaining on the circuit
board.

Soldering
iron

* Do not apply force to the solder removal mesh wire and soldering iron
when removing the solder since the pattern is likely to peel off.
Flat Package JC Installation

(1) Coat the circuit board from which the flat package IC has been removed with flux.

(2) Place the good flat package IC to match the pattern on the board.

(3) Temporarily fix the flat package IC at the four corners so it does not move.

(4) Solder all pins of the flat package IC.

* Be careful not to short the pins since the spaces between the pins are
very narrow.

(5) After soldering, use thinner to rinse away the remaining flux.

(6) Use a magnifying glass to check that there is no short-circuit.