1. c) Bistable 17.

 c) NOR or NAND 31. a) Q(n+1) = (S +

multivibrator gates Q(n))R’

2. b) Two stable 18. . b) Sequential 32. c) Latches has

state circuits one input but
flip-flop has two
3. c) It can store 19. a) Combinational
one bit of data circuits 33. c) 4

4. c) High output & 20. a) 2 34. b) Two

low output additional AND
21. b) Latch gates
5. a) 4
22. a) Two inverters 35. d) Invalid State
6. a) System rated 36. c) Binary storage
23.  b) Reset register
7. b) 2 inputs
24. a) The trigger 37. b) When the Q
8. d) q and q’ pulse is given to output follows
9. b) label outputs change the state the input

10. c) s and r 25. a) A pulse that 38. c) The clock

starts a cycle of pulse transitions
11. c) Metastable operation from LOW to
HIGH
12. d) Cross coupling 26. c) Because of
13. c) Switch cross-coupled 39. b) No active S or
debouncer connection R input

14. c) 3 27. d) S’=0, R’=0 40. b) RESET

28. a) No change
15. c) Not change 41. a) Edge-
29. d) Both a D latch detection circuit
16. a) The Q output and an inverter
is either SET or at its input 42. d) Gated D-latch
RESET as soon as 30. a) The inputs of 43. a) S-R flip-flop
the D input goes NOR latch are 0
HIGH or LOW but 1 for NAND 44. a) Two AND
latch gates
45. d) J = 1, K = 1 inventory of the
46. b) Ones catching integrated
circuit
47. d) J = 0, K = 0
48. d) A 10 kHz 63. a) J = 0, K = 0
square wave
49. c) The letters 64. a) 00
were chosen in
honour of Jack 65. b) 2 kHz
Kilby, the
inventory of the
integrated
circuit

50. a) J = 0, K = 0

51. a) 00

52.  b) 2 kHz

53. b) 5 kHz

54. c) 4

55. d) Gated D-latch

56. a) S-R flip-flop

57. a) Two AND

gates

58. d) J = 1, K = 1
59. b) Ones catching

60. d) J = 0, K = 0
61. d) A 10 kHz
square wave
62. c) The letters
were chosen in
honour of Jack
Kilby, the