1
Selective Harmonic Elimination Modulation for
HVDC Modular Multilevel Converter
Concettina Buccella
University of L’Aquila -DISIM Maria Gabriella Cimoroni
and DigiPower Ltd. University of L’Aquila - DISIM
67100 L’Aquila, Italy 67100 L’Aquila, Italy
2021 AEIT HVDC International Conference (AEIT HVDC) | 978-1-6654-4981-6/20/$31.00 ©2021 IEEE | DOI: 10.1109/AEITHVDC52364.2021.9474620
concettina.buccella@univaq.it mariagabriella.cimoroni@univaq.it
Abstract—This paper proposes the application of a mixed
selective harmonic elimination mitigation modulation algorithm
to three-phase HVDC modular multilevel converters. Defining l
the number of levels, two cases have been considered: l=65 and
l=257. While operating at the fundamental switching frequency,
the algorithm returns those solutions, expressed in terms of
switching angles to be applied to power devices, which allow
complete elimination of a subset of low order harmonics and the
mitigation of others. Simulation results show harmonic analysis
graphs and total harmonic distortion at different modulation
indexes and demonstrate the feasibility of the proposed system.
Index Terms—HVDC, Modular Multilevel Converters (MMC),
l-level cascaded H-bridge converters (CHB), Selective Harmonics
Elimination (SHE), Total Harmonic Distortion (THD).
I. I NTRODUCTION
The increasing demand of electrical energy in urban as well
as in rural areas require the availability of huge amounts of
stable and constant power flows. Electrical energy is often pro-
duced in remote locations, therefore significant power losses
and grid instabilities affect trasmission lines. High Voltage
Direct Current (HVDC) systems using line-commutated con-
verter (LCC) systems are employed in bulk power transmission
systems, featuring power transmission capability up to 10 GW
at 1.1 MV [1], [2]. However, these systems are prone to
commutation failures, generate a large amount of harmonics,
and require reactive power compensation systems.
Voltage source converters-based (VSC) HVDC represent a
feasible alternative to traditional LCC HVDC systems. They
offer significant advantages such as: (i) independent control
of active and reactive power, (ii) faster dynamic response, (iii)
improved reliability and black start capabilities, as they do not
rely on the ac grid voltage to inject power, (iv) reduced har-
monic generation, (v) power reversal with constant DC voltage
polarity, thus making DC multiterminal networks easier to be
implemented [3]. However, their losses, due to high–frequency
operations limit their use in high power level systems. Modular
multilevel converters (MMC) can overcome these issues offer-
ing: (i) high voltage operations without power transformer, (ii)
modularity, (iii) reduced switching losses due to low switching
frequency operations, and (iv) improved power quality, due to
pseudo-sinusoidal voltage operations. Typical MMCs consist
of identical submodules (SMs) connected in series and capa-
ble to manage high voltages while keeping high conversion
978-1-6654-4981-6/21/$31.00 ©2021 IEEE
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Carlo Cecati
DISIM - University of L’Aquila
and DigiPower srl
L’Aquila, Italy
carlo.cecati@univaq.it
efficiency, additionally their structure is scalable in power
[4]. A replacement of conventional VSCs employing lumped
distributed capacitors with MMCs improves the resilience of
the transmission systems [4], moreover, the use of MMC in
large-scale HVDC links and in DC microgrids ensures safe and
reliable operations in case of AC and DC grid disturbances.
Simulation of HVDC links that use modular multilevel
converters with hundreds cells per arm is computationally
intensive, requires computers with high computing power and
large memory, and takes long simulation times. An averaged
model of the MMC-based HVDC link is often used to reduce
the simulation time. The AC component of the upper and
lower arm modulation function is obtained directly from the
inner current controller, then, appropriate DC offsets are added
as described in [5], [6]. An electro-magnetic transient (EMT)
approach for full-scale modeling of the MMC-based HVDC
link is proposed in [7], where a simple Thevenin equivalent
circuit is extracted. This model cannot reproduce dynamic
interaction between AC and DC sides during DC network
fault, but significantly reduces computation burden that arises
from solution of the power circuit, while, due to modulation
and capacitor voltage balancing, is retained as in detailed
switching models.
In [8] the accelerated model of the MMC is presented.
Theoretical background is similar to that in [7] but each
individual MMC cell is a primitive circuit that shares the
same current injection equal to the arm current, allowing the
application of the generalized circuit theory [8], [9] and the
Kron connection matrix.
This paper considers a modular multilevel converter for
HVDC transmission systems with a large number of cells
and proposes a fundamental frequency modulation algorithm.
The numerous switching angles computed for the modulation
of the power converter produce high quality output voltage
waveforms and ensure very low losses. The angles are obtained
by the solution of a high degree equations system obtained
by applying a fundamental switching frequency modulation
technique.
II. M ATHEMATICAL MODEL
The considered system is depicted in Fig. 1 and consists of
two back–to–back–connected MMCs.
 VDC/2 +∞
 sin(kωt− 23 χΓ π )
West
Converter
East
Converter
vΓN (ωt) = Hk k (1)
VDC/2 k=1, 5, 7,...
West Grid Transformer Transformer East Grid
Γ = a, b, c, χa = 0, χb = 1, χc = 2
Fig. 1. MMC based tie. where Hk is the k th harmonic amplitude
 s 
4Vdc 
The MMC internal scheme is shown in Fig. 2. Hk = cos (kαi ) (2)
πk i=1
The basic element of the MMC is the submodule (SM) or
cell, which is a simple half–bridge converter with a parallel a, b, c are the phases and the unknown switching angles
capacitor. α1 ,... αs have to satisfy the following conditions:
The SM can handle bidirectional current; its terminal volt-
π
age can be turned on and off between zero or the voltage of 0 ≤ α1 < α2 ... < αs < . (3)
the capacitor. 2
Proposed fundamental frequency SHE-SHM procedure is
TABLE I
applied to a MMC having s = 2n modules; it imposes
the amplitude of the fundamental harmonic, puts to zero the
IEEE Std 519-1992 Harmonic Voltage Limits amplitudes of the first n low order harmonics and it limits the
Individual Voltage Total Voltage amplitude of the others high order harmonics in compliance
Bus Voltage at PCC
Distortion (%) (lk %) Distortion (%) with code requirements. Therefore it solves the following
V ≤ 1 kV 5 8 trascendental system
1 kV < V ≤ 69 kV 3 5
⎧
69 kV < V ≤ 161 kV 1.5 2.5 ⎪
⎪ cos (α1 ) + cos (α2 ) + ... + cos (αs ) = sm
161 kV < V ⎪
⎪ cos (5α1 ) + cos (5α2 ) + ... + cos (5αs ) = 0
1 1.5 ⎪
⎪
⎪
⎪ cos (7α1 ) + cos (7α2 ) + ... + cos (7αs ) = 0
⎪
⎪
The series connection of “s” submodules makes up an arm. ⎪
⎪ cos (11α1 ) + cos (11α) + ... + cos (11αs ) = 0
⎪
⎪
The number of levels made available to synthesize the ac ⎪
⎪ .. .. ..
⎨
voltages is l = 2s + 1. . . .
⎪
⎪ cos (rn α1 ) + cos (rn α2 ) + ... + cos (rn αs ) = 0
The capacitor in each SM can be charged or discharged ⎪
⎪
⎪
⎪ |cos ((rn + 1) α1 ) + cos ((rn + 1) α2 ) + . . . +
depending on the direction of the arm current. A converter leg ⎪
⎪
⎪
⎪ + cos ((rn + 1) αs )| ≤ lr+1
is made up of an upper and a lower arm, and each converter ⎪
⎪
⎪
⎪ .. .. ..
has three legs, one for each phase. ⎪
⎪ . . .
There is also an inductor Larm in each arm in order to ⎩
|cos (rf α1 ) + cos (rf α2 ) + ... + cos (rf αs )| ≤ lf
take up the voltage difference that results when a module is (4)
connected or disconnected. where: m = 4·sV πH1
dc
is the modulation index, r n is the order of
A mixed selective harmonic elimination (SHE)- selective the latest harmonic to be deleted, rf is the order of the latest
harmonic mitigation (SHM) algorithm, working at fundamen- harmonic to be mitigated, H1 is the fundamental harmonic
tal switching frequency is applied. amplitude and Vdc is the rated voltage. The quantities lk , k =
r + 1, . . . f represent the limits imposed by the selected code
SMa1 SMb1 SMc1 requirements (IEEE Standard 519 limits) and are expressed in
SM
percentage in respect to the fundamental frequency component
SM SM
upper arm

as shown in the Table I [10]. The solution of system (4) returns

SMa32 SMb32 SMc32 SM =
= the switching angles capable to minimize the THD%, defined
SM SM SM as
Larm Larm

Larm 151 2
k=5, 7... Hk
Larm Larm THD% = 100 (5)
Larm H1
SMa1 SMb1 SMc1
lower arm

SM SM
SM
SM
III. S IMULATION RESULTS
a32 SMb32 SMc32

SM
Two cases have been considered, which differ on the number
SM SM
s of modules:
Case#1 s = 32, n = 5 corresponding to l = 65;
Fig. 2. MMC scheme. Case#2 s = 128 corresponding to l = 257.
The method has been applied to obtain the solution ex-
The Fourier series expansion of output phase voltage vΓN pressed in terms of switching angles and exists only in some
is: intervals of modulation index.

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A. Case#1 2.5

2
The applied method returns the solution within the modu-

THD %
lation index interval I1 = [0.71, 0.901]. Table II shows the
computed switching angles in rad, depending on m. 1.5

1
0.71 0.73 0.75 0.77 0.79 0.81 0.83 0.85 0.87 0.89
TABLE II m
S WITCHING ANGLES IN RAD FOR THE C ASE #1.
Fig. 3. THD% depending on m.




















































 0.7










  0.6

m = 0.805























 0.5















Hk / H1 %











 0.4











 0.3












 












 0.2





 







 








 0.1

 


 







0

 


 





 3 11 19 27 35 43 51 59 67 75 83 91 99 107115123131139147





 


 




 k

















 


 
Fig. 4. Harmonic analysis for m = 0.805.













 

 





 


 








 


 
0.7


























   0.6
m = 0.75









 















 0.5












 
Hk / H1 %

0.4

























0.3

















 





 0.2












0.1

























 0

 









3 11 19 27 35 43 51 59 67 75 83 91 99 107115123131139147
k




 






Fig. 5. Harmonic analysis for m = 0.75.

1.6
m = 0.901
Figure 3 shows the obtained THD% as a function of cthe 1.4

modulation index m and Figs. 5, 4 and 6 show the harmonic 1.2

analysis obtained for m = 0.75, m = 0.805 and m = 0.901, 1
Hk / H1 %

respectively. Fig. 7 shows the amplitude of the 19th harmonic,

0.8
in percentage respect to the fundamental one. Notice that the
19th harmonic represents the first not eliminated harmonic. 0.6

0.4

Considering the whole modulation index interval in which 0.2

the solution exists, the procedure deletes the 5th, 7th, 11th, 0
13th and 17th harmonics and their multiples and mitigate 3 11 19 27 35 43 51 59 67 75 83 91 99 107115123131139147
k
the other harmonics, according the code requirements for bus
voltage at PCC V ≤ 69 kV [10]. Fig. 6. Harmonic analysis for m = 0.901.

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B. Case#2 0.6

m = 0.85
0.5

0.4

Hk / H1 %
The modulation index interval in which the solution exists is
I2 = [0.781, 0.901]. Table III shows the computed switching 0.3

angles, in rad, for the values of m in which the solution 0.2

exists. In the whole modulation index interval in which the
solution exists, the 5th, 7th, 11th, 13th, 17th, 19th and 23th 0.1

harmonics and their multiples are deleted and the others are 0
mitigated according the code requirements for any bus voltage 3 11 19 27 35 43 51 59 67 75 83 91 99 107115123131139147153
k
at PCC (see Table I) [10].
Fig. 9. Harmonic analysis for m = 0.8.
Figure 8 shows the obtained THD% as a function on m. The
corresponding harmonic analysis when m = 0.8, 0.85, 0.901
is shown in Figs. 9, 10 and 11, respectively. 0.6

m = 0.85
The percentage values of the first not eliminated harmonic, 0.5

that is the 29th, respect to the fundamental one, depending on 0.4

m, is shown in Fig. 12. Since for any values of the considered

Hk / H1 %
m, THD% value is less than 0.9, also any H H1 % is less than
k 0.3

0.9. 0.2

0.1

0
3 11 19 27 35 43 51 59 67 75 83 91 99 107115123131139147153
0.35 k

0.3
Fig. 10. Harmonic analysis for m = 0.85.
0.25
H19 / H1 %

0.2
0.6
0.15 m = 0.901
0.5
0.1
0.4
H k / H1 %

0.05
0.3
0
0.71 0.73 0.75 0.77 0.79 0.81 0.83 0.85 0.87 0.89
0.2
m
0.1
Fig. 7. Percentage amplitude of H19 /H1 .
0
3 11 19 27 35 43 51 59 67 75 83 91 99 107115123131139147153
k

Fig. 11. Harmonic analysis for m = 0.901.

0.6
0.9
0.5
0.8
0.4
H29 / H1 %

0.7
0.3
THD %

0.6
0.2

0.5
0.1

0.4
0
0.781 0.8 0.82 0.84 0.86 0.88 0.9
0.78 0.8 0.82 0.84 0.86 0.88 0.9 m
m
Fig. 12. Percentage amplitude of H29 /H1 .
Fig. 8. THD% depending on m.

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 TABLE III
S WITCHING ANGLES IN RAD FOR THE C ASE #2.
















































































































































































































































 






 






 




















 

















 



















































































 



 






 

















 


 






































 



 







 









 










 
 









  


































 

































 





































 





























 
 


 

























 





 
 


 


















 
 














 





































 







































 





























 






 





























 


































 










 








 



 


























































 


 





 



























 





 











 


























 





































 


 































 























 









 




 






































































 







 



















































 


































 












 



















 
















 














































 











































 







































 




 







 











 









 





 

























 





 
























 








 

 


 


 






















 








 






















 










 


 


 



 




















 


 







 


 











 







 

 


 









 







 


 











 




IV. H ARDWARE I MPLEMENTATION Sensors provide to measure voltages and currents. The
DSP can be used as a local computational engine capable to
To practically validate the proposed modulation algorithm, implement control as well as fault detection and diagnosis
a modular multilevel converter (MMC) has been designed algorithms. The measured voltages and currents are converted
and realized by DigiPower [11]. The MMC consists of an in digital signals using the A/D converters internal to the DSP
array of H-bridges and a control board with 5CEBA7F31 and sent to FPGA using SPI. An additional external analog
Cyclone V FPGA, 10M16DAF484 CPLD from Intel and
TMS320F28377SPTP from Texas Instruments. Such a board
communicates with each H-bridge through SPI (serial periph-
eral interface) point-to-point bidirectional channel, which is
capable to exchange both command signals and analog inputs
i.e. voltages and currents measured on each H-bridge. The
complex computational board is completed by additional local
ADC channels, serial communication channels (USB, RS232,
UART), 1 Gb/s Ethernet port, three separate JTAG inputs (one
for each digital processor), and LCD display. The total number
of input/output pins is 480. The board is shown in Fig. 13.
Each H-bridge includes four 30N120L IGBTs with
anti−parallel diodes, 900 μF , 800 V polipropylene capacitor
and is controlled by a local TMS320F28377SPTP digital
signal processor, which provides to apply the gate signals
received by the dedicated SPI channel of the main control
board to IGBTs through ad-hoc drivers. Fig. 13. Control board architecture

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signals board measures voltage and currents and communicates
with the control board through SPI channel. Figure 14 shows
a detail of the H-Bridges. The real-time modulation software
is under development using VHDL.
Fig. 14. Detail of the prototype showing H-Bridges
V. C ONCLUSION
A mixed selective harmonic elimination- mitigation algorithm
operating at fundamental switching frequency has been pro-
posed for three phase HVDC converters. The procedure is
capable to compute switching angles capable to deleting the
first n (s = 2n ) low order harmonics and their multiples and
to mitigate the other harmonics in compliance with the code
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requirements. Two cases have been considered for the number
of levels: l = 65 and l = 257. It has been shown that:
• in the first case, the mitigated harmonics verify the code
limits for bus voltage at PCC V ≤ 69 kV and THD% as
a function of m remains less than 2.5%
• in the second case, the mitigated harmonics respect the
code limits for any values of bus voltage at PCC and the
THD% is less than 0.9% for any m.
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