5 4 3 2 1

REV Description DATE BY

A3 Production release. 10/21/2011 GC

Updated in conjunction with the release of the SRM. Typos and naming changes. No change
A3A in design. 11/5/2011 GC PAGE NO. SCHEMATIC PAGE
D D

1. Changed supplier for the SD card connector due to availability issue. Created a dual footprint
for two differrent parts. SD connector is now reversed, so label down is the new orientation. 1 COVER PAGE
2. Changed R76 from a 50 ohm to 49.9 ohm. Smaller package and lower cost. Changed
footprint to 0402. 2 POWER MANAGEMENT
A4 3. Changed C99 termination to DGND. 12/1/2011 GC
3 PROCESSOR 1 OF 3
4. Added 10K pulldown to fix link speed LED.
5. Changed C7 to a 0805 package in PCB layout. 4 PROCESSOR 2 OF 3
1. Changed R219 to DNI. It was causing issues with Ethernet DHCP IP address 5 PROCESSOR 3 OF 3
aquisition. Will be added back in on revision A6.
A5 2/3/2012 GC
6 LED, CONFIGURATION AND BUTTON
2. Removed the connection of the VPP to VDD_CORE as suggested by TI.
7 MEMORY
1. Changed R219 to installed.
2. Added R220 , a 10K pulldown to pin 18 of the SMSC PHY to allow R219 addition to work as 8 ETHERNET AND USB HOST
C C
expected..
3. Removed the connection to the VPP pin on the processor.
4. Added R221, R218, R217, R202 to facilitate the addition of two signals, GPIO3_18 and 9 USB CONCENTRATOR
A6 GPIO3_19 to the expansion bus header to provide two more signals for the PRU access..
5. Changed R210 to installed and added test point to allow the EEPROM to be programmed 10 SERIAL AND JTAG
but with added protection to prevent corruption. Added Test Point to enable programming. 5/10/2012 GC
6. Moved Resistors R189 and R150 to provide more clearence around mounting hole. 11 EXP CONN, uSD, AND LDO
7. PCB revision was changed to C2.
8. Change pullups on the boot pins to 42.2K per AM335x design team.
9. Rewired the JTAG reset signal from the optional JTAG connector.
10. R122 was removed becasue it was connectd to the wrong pin on the SMSC LAN8710.
11. R172 was removed due to a spurious reset generated by the FT2232 when under CCS, the
target was connected. NOTE: PCB Revision for this board is Rev C2.
1. Corrected typo on page 8 for correct pin on LAN8710A for MODE2 function.
A6A 6/28/2012 GC

B B

This schematic is *NOT SUPPORTED* and DOES NOT constitute

a reference design. Only “community” support is allowed
via resources at BeagleBoard.org/discuss.

THERE IS NO WARRANTY FOR THIS DESIGN , TO THE EXTENT

PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED
IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
PROVIDE THE DESIGN “AS IS” WITHOUT WARRANTY OF ANY KIND,
EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE
QUALITY AND PERFORMANCE OF THE DESIGN IS WITH YOU. SHOULD
A THE DESIGN PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL A

NECESSARY SERVICING, REPAIR OR CORRECTION.

Title
BeagleBone Cover Page
Size Document Number Rev
B A6A
450-5500-001
Date: Thursday, June 28, 2012 Sheet 1 of 11
5 4 3 2 1
 5 4 3 2 1

VDD_5V
VDD_3V3B
5V DC POWER SYS_VOLT
U1 SYS_5V
P5 7 5

8
1 1 IN0 OUT1 4 R1 R2 R3 .1,0805 VDD_3V3B U14A
1 IN1 OUT0 4.75K,1% 12.1K,1% 1
3 6 3 7 PMIC_INT_PU 0,1% 3
3 EN FLAG PMIC_INT
R203 2 R28
2 DGND U2

GND
2 DC_IN 10 7 100K,1% SN74LVC2G00DCU

4
D NCP349 AC SYS1 8 D

2
PJ-200A SYS2
USB_DC 12
DGND USB
4 BAT DGND
17 BAT1 5
VDD_3V3A C1 C2 15 NC1 BAT2 6 BAT_SENSE
DGND NC BAT_SENSE 11 BAT_TEMP C3 R10
4.7uF,6.3V 4.7uF,6.3V TS 0,DNI
10uF,10V

R7
R4
C4 10uF,10V P_INT_LDO 48
INT_LDO VDD_3V3A
AIN7 4
DGND DGND C5 10uF,10V P_BYPASS 47 DGND
BYPASS

1.5K,5%
1.5K,5%
P_MUXIN 14 16 P_MUXOUT R8 100K,1% R9 100K,1% DGND
DGND MUX_IN MUX_OUT

4 PMIC_POWR_EN 9 18
44 PWR_EN VIO 26
RESET PGOOD PMIC_PGOOD 3
11 25 46 3
PWR_BUT PB_IN LDO_PGOOD LDO_PGOOD
4,7 28 13 P_W AKEUP R11 0,1% WAKEUP 4
I2C0_SCL SCL WAKEUP
4,7 27 45 PMIC_INT_SRC
I2C0_SDA SDA INT
34 BL_SINK1
ISINK1 33 BL_SINK2
BL_ISET2 36 ISINK2
ISET2
C C
38 BL_OUT
FB_WLED
BL_ISET1 35
ISET1 C7
37 BL_IN 4.7uF,50V
L4
TESTPT1 VDD_1V8 VDDS_DDR
P6 DGND TP15
DGND C8 10uF,10V 21 L1
BAT 2 1 BAT VIN_DCDC1 20 P_L1 1 2 R12
BAT_TEMP 4 3 BAT_SENSE L1 2.2uH,2.6A 0,1% R14 0,1%
BL_ISET1 6 5 BL_ISET2 19 VDCDC1 VDD_MPU
BL_IN 8 7 BL_OUT C9 10uF,10V 22 VDCDC1 L2
BL_SINK2 10 9 BL_SINK1 VIN_DCDC2 23 P_L2 1 2 R204 0,1%
L2 2.2uH,2.6A TP18
24 VDCDC2 TP17TESTPT1 TESTPT1
C10 10uF,10V 32 VDCDC2 L3 VDD_CORE
HDR5x2 VIN_DCDC3 31 P_L3 1 2 R13
L3 2.2uH,2.6A 0,1% C14 C15 C16
29 VDCDC3 VDD_3V3A
EXPANSION HEADER VDCDC3 10uF,10V 10uF,10V 22uF,6.3V
C18 10uF,10V 39 40 LDO3 R19 3.25V
LDO3_IN LDO3 0,1% VDD_3V3B
B B
C19 10uF,10V 42 43 LDO4 R121 C165
LDO4_IN LDO4 0,1% 10uF,10V
VRTC DGND
C17 10uF,10V 2 3 1.8V@100mA C135
VINLDO VLDO1
10uF,10V DGND
1
VLDO2 C20
DGND
2.2uF,6.3V POWER LED
MTG1
TP1 R6 GRN
MHOLE DGND PWR_LED PWR_LEDR D1 DGND
AGND
PGND
PPAD

TESTPT1
MTG2 TPS65217b
470,5% 598-8170-107F
41
30
49

R15
MHOLE 0,1% TP14
TESTPT1
MTG3
DGND AGND DGND
MHOLE AGND

MTG4
DGND
A MHOLE A

Title
BeagleBone Power Management
Size Document Number Rev
B A6A
450-5500-001
Date: Thursday, June 28, 2012 Sheet 2 of 11
5 4 3 2 1
 5 4 3 2 1

VRTC
C21
LDO_PGOOD 2
VRTC R141 10K,1%

0.01uf,16V,DNI

8
8
U17A DGND U17B
1 5 R143
7 VRTC_DET R17 VRTC_DETB 3 VRTC_DET_OUT RTC_PORZ
C23 25pF,50V 2 1.1K,1%,DNI 6
SN74AUP2G08,DNI 0,1%,DNI
SN74AUP2G08,DNI

4
4
Y1
2
OSC1_OUT1 1 C22 R18
25pF,50V C24 0.01uf,16V,DNI
DGND
D D
32.768KHz MC-306 DGND 2 PMIC_PGOOD
12.1K,1% R20

DGND C25
0.01uf,16V
Y2 24MHz,DNI
Y3 24MHz DGND 100K,1% VDD_3V3A

3
3
R21 R22
4 2 4 2 1M,1% 0,1% DGND
C26
R23

1
1
SYS_RESETn 11,8
18pF,50V OSC0_OUT1 R24 U5A DGND 10K,1%
OSC0_IN V10 B15
C27 OSC0_IN PORZ A10 R27
0,1% NRESET_INOUT SYS_WARMRESETn 10,6
18pF,50V OSC0_OUT U11 B5 0,1%
GND_OSC0 V11 OSC0_OUT RTC_PORZ
VSS_OSC0 B18
NNMI PMIC_INT 2
OSC1_IN A6 A15 10
OSC1_IN EVENT_INTR0/TIMER4/CLKOUT1/SPI1_CS1/PR1PRU1R31_16/EMU2/GPIO0_19 D14 XDMA_EVENT_INTR0
CLKOUT_SRC R218
EVENT_INTR1/TCLKIN/CLKOUT2/TIMER7/PR1PRU0_PRUR31_16/EMU3/GPIO0_20 CLKOUT2 10,11
GND_OSC0 OSC1_OUT A4 0,1%
GND_OSC1 A5 OSC1_OUT B10
VSS_RTC NTRST JTAG_TRSTn 10
C11 R221
TMS JTAG_TMS 10 GPIO3_20 3
DDR_A[13..0] B11 0,1%
7 DDR_A[13..0] TDI JTAG_TDI 10
DDR_A0 R29 33,0402 PDDR_A0 F3 A12
DDR_A0 TCK JTAG_TCK 10
DDR_A1 R25 33,0402 PDDR_A1 H1 A11
DDR_A1 TDO JTAG_TDO 10
DDR_A2 R30 33,0402 PDDR_A2 E4 C14
DDR_A2 EMU0/GPIO3_7 JTAG_EMU0 10
DDR_A3 R26 33,0402 PDDR_A3 C3 B14
DDR_A3 EMU1/GPIO3_8 JTAG_EMU1 10
DDR_A4 R31 33,0402 PDDR_A4 C2
DDR_A5 R32 33,0402 PDDR_A5 B1 DDR_A4 V12
DDR_A5 GPMC_CLK/LCD_MEM_CLK/GPMC_WAIT1/MMC2_CLK/PRT1_MII1_TXEN/MCASP0_FSR/GPIO2_1 GPIO2_1 11
DDR_A6 R33 33,0402 PDDR_A6 D5 V6
DDR_A6 GPMC_CSN0/GPIO1_29 GPIO1_29 11
DDR_A7 R34 33,0402 PDDR_A7 E2 U9
DDR_A7 GPMC_CSN1/GPMC_CLK/MMC1_CLK/PRT1EDIO_DATA_IN6/PRT1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_12/PR1_PRU1_PRU_R31_12/GPIO1_30 GPIO1_30 11
DDR_A8 R35 33,0402 PDDR_A8 D4 V9
DDR_A8 GPMC_CSN2/GPMC_BE1N/MMC1_CMD/PR1_EDIO_DATA_IN7/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_13/PR1_PRU1_PRU_R31_13/GPIO1_31 GPIO1_31 11
DDR_A9 R36 33,0402 PDDR_A9 C1 T13
DDR_A10 R37 33,0402 PDDR_A10 F4 DDR_A9 GPMC_CSN3/MMC2_CMD/PR1_MDIO_DATA/GPIO2_0 U6
DDR_A10 GPMC_WEN/TIMER6/GPIO2_4 TIMER6 11
DDR_A11 R38 33,0402 PDDR_A11 F2 T7
DDR_A11 GPMC_OEN_REN/TIMER7/EMU4/GPIO2_3 TIMER7 11
DDR_BA[2..0] DDR_A12 R39 33,0402 PDDR_A12 E3 R7
7 DDR_BA[2..0] DDR_A12 GPMC_ADVN_ALE/TIMER4/GPIO2_2 TIMER4 11
DDR_A13 R40 33,0402 PDDR_A13 H3 T6
DDR_A13 GPMC_BE0N_CLE/TIMER5/GPIO2_5 TIMER5 11
H4 U18 11
D3 DDR_A14 GPMC_BE1N/GMII2_COL/GPMC_CSN6/MMC2_DAT3/GPMC_DIR/PR1_MII1_RXLINK/MCASP0_ACLKR/GPIO1_28 T17 GPIO1_28
C UART4_RXD 11 C
DDR_BA0 R41 33,0402 PDDR_BA0 C4 DDR_A15 GPMC_WAIT0/GM112_CRS/GPMC_CSN4/RMII2_CRS_DV/MMC1_SDCD/PR1_MII1_RXDV/UART4_RXD/GPIO0_30 U17
DDR_BA0 GPMC_WPN/GMII2_RXERR/GPMC_CSN5/RMII2_RXERR/MMC2_SDCD/PR1_MDIO_MDCLK/UART4_TXD/GPIO0_31 UART4_TXD 11
DDR_BA1 R42 33,0402 PDDR_BA1 E1
DDR_D[15..0] DDR_BA2 R43 33,0402 PDDR_BA2 B3 DDR_BA1 U7
7 DDR_D[15..0] DDR_BA2 GPMC_AD0/MMC1_DAT0//////GPIO1_0 GPIO1_0 11
V7 11
DDR_D0 PDDR_D0 M3 GPMC_AD1/MMC1_DAT1//////GPIO1_1 R8 GPIO1_1
R44 33,0402 11
DDR_D0 GPMC_AD2/MMC1_DAT2//////GPIO1_2 GPIO1_2
DDR_D1 R45 33,0402 PDDR_D1 M4 T8
DDR_D1 GPMC_AD3/MMC1_DAT3//////GPIO1_3 GPIO1_3 11
DDR_D2 R46 33,0402 PDDR_D2 N1 U8
DDR_D2 GPMC_AD4/MMC1_DAT4//////GPIO1_4 GPIO1_4 11
DDR_D3 R47 33,0402 PDDR_D3 N2 V8
DDR_D3 GPMC_AD5/MMC1_DAT5//////GPIO1_5 GPIO1_5 11
DDR_D4 R48 33,0402 PDDR_D4 N3 R9 11
DDR_D5 PDDR_D5 N4 DDR_D4 GPMC_AD6/MMC1_DAT6//////GPIO1_6 T9 GPIO1_6
R49 33,0402 11
P3 DDR_D5 GPMC_AD7/MMC1_DAT7//////GPIO1_7 U10 GPIO1_7
DDR_D6 R50 33,0402 PDDR_D6 11
P4 DDR_D6 GPMC_AD8/LCD_DATA23/MMC1_DAT0/MMC2_DAT4/EHRPWM2A/PR1_MII_MT0_CLK//GPIO0_22 T10 EHRPWM2A
DDR_D7 R51 33,0402 PDDR_D7 11
J1 DDR_D7 GPMC_AD9/LCD_DATA22/MMC1_DAT1/MMC2_DAT5/EHRPWM2B/PR1_MII0_CRS//GPIO0_23 T11 EHRPWM2B
DDR_D8 R52 33,0402 PDDR_D8 11
K1 DDR_D8 GPMC_AD10/LCD_DATA21/MMC1_DAT2/MMC2_DAT6/EHRPWM2_TRIPZONE_INPUT/PR1_MII0_TXEN//GPIO0_26 U12 GPIO0_26
DDR_D9 R53 33,0402 PDDR_D9 11
K2 DDR_D9 GPMC_AD11/LCD_DATA20/MMC1_DAT3/MMC2_DAT7/EHRPWM2_SYNCI_O/PR1_MII0_TXD3//GPIO0_27 T12 GPIO0_27
DDR_D10 R54 33,0402 PDDR_D10
DDR_D10 GPMC_AD12/LCD_DATA19/MMC1_DAT4/MMC2_DAT0/EQEP2A_IN/PR1_MII0_TXD2/PR1_PRU0_PRU_R30_14/GPIO1_12 GPIO1_12 11
DDR_D11 R55 33,0402 PDDR_D11 K3 R12
DDR_D11 GPMC_AD13/LCD_DATA18/MMC1_DAT5/MMC2_DAT1/EQEP2B_IN/PR1_MII0_TXD1/PR1_PRU0_PRU_R30_15/GPIO1_13 GPIO1_13 11
DDR_D12 R56 33,0402 PDDR_D12 K4 V13
DDR_D12 GPMC_AD14/LCD_DATA17/MMC1_DAT6/MMC2_DAT2/EQEP2_INDEX/PR1_MII0_TXD0/PR1_PRU0_PRU_R31_14/GPIO1_14 GPIO1_14 11
DDR_D13 R57 33,0402 PDDR_D13 L3 U13
DDR_D13 GPMC_AD15/LCD_DATA16/MMC1_DAT7/MMC2_DAT3/EQEP2_STROBE/PR1_ECAP0_ECAP_CAPIN_APWM_O/PR1_PRU0_PRU_R31_15/GPIO1_15 GPIO1_15 11
DDR_D14 R58 33,0402 PDDR_D14 L4
DDR_D15 R59 33,0402 PDDR_D15 M1 DDR_D14 R13
DDR_D15 GPMC_A0/GMII2_TXEN/RGMII2_TCTL/RMII2_TXEN/GPMC_A16/PR1_MII_MT1_CLK/EHRPWM1_TRIPZONE_INPUT/GPIO1_16 GPIO1_16 11
V14
GPMC_A1/GMII2_RXDV/RGMII2_RCTL/MMC2_DAT0/GPMC_A17/PR1_MII1_TXD3/EHRPWM1_SYNCI_O/GPIO1_17 GPIO1_17 11
R60 33,0402 PDDR_CLK D2 U14
7 DDR_CLK DDR_CK GPMC_A2/GMII2_TXD3/RGMII2_TD3/MMC2_DAT1/GPMC_A18/PR1_MII1_TXD2/EHRPWM1A/GPIO1_18 EHRPWM1A 11
R61 33,0402 PDDR_CLKn D1 T14
7 DDR_CLKn DDR_NCK GPMC_A3/GMII2_TXD2/RGMII2_TD2/MMC2_DAT2/GPMC_A19/PR1_MII1_TXD1/EHRPWM1B/GPIO1_19 EHRPWM1B 11
R62 33,0402 PDDR_CKE G3 R14
7 DDR_CKE DDR_CKE GPMC_A4/GMII2_TXD1/RGMII2_TD1/RMII2_TXD1/GPMC_A20/PR1_MII1_TXD0/EQEP1A_IN/GPIO1_20
R63 33,0402 PDDR_CSn H2 V15
7 DDR_CSn DDR_CSN0 GPMC_A5/GMII2_TXD0/RGMII2_TD0/RMII2_TXD0/GPMC_A21/PR1_MII1_RXD3/EQEP1B_IN/GPIO1_21 USR0 6
R64 33,0402 PDDR_CASn F1 U15
7 DDR_CASn DDR_CASN GPMC_A6/GMII2_TXCLK/RGMII2_TCLK/MMC2_DAT4/GPMC_A22/PR1_MII1_RXD2/EQEP1_INDEX/GPIO1_22 USR1 6
R65 33,0402 PDDR_RASn G4 T15
7 DDR_RASn DDR_RASN GPMC_A7/GMII2_RXCLK/RGMII2_RCLK/MMC2_DAT5/GPMC_A23/PR1_MII1_RXD1/EQEP1_STROBE/GPIO1_23 USR2 6
R66 33,0402 PDDR_WEn B2 V16
7 DDR_WEn DDR_WEn GPMC_A8/GMII2_RXD3/RGMII2_RD3/MMC2_DAT6/GPMC_A24/PR1_MII1_RXD0/MCASP0_ACLKX/GPIO1_24 USR3 6
U16
R67 33,0402 PDDR_DQM0 M2 GPMC_A9/GMII2_RXD2/RGMII2_RD2/MMC2_DAT7/GPMC_A25/PR1_MII_MR1_CLK/MCASP0_FSX/GPIO1_25 T16
7 DDR_DQM0 DDR_DQM0 GPMC_A10/GMII2_RXD1/RGMII2_RD1/RMII2_RXD1/GPMC_A26/PR1_MII1_CRS/MCASP0_AXR0/GPIO1_26 USB1_OC 8
R68 33,0402 PDDR_DQS0 P1 V17
7 DDR_DQS0 DDR_DQS0 GPMC_A11/GMII2_RXD0/RGMII2_RD0/RMII2_RXD0/GPMC_A27/PR1_MII1_RXER/MCASP0_AXR1/GPIO1_27
R69 33,0402 PDDR_DQSN0 P2
7 DDR_DQSN0 DDR_DQSN0
R70 33,0402 PDDR_DQM1 J2
7 DDR_DQM1 DDR_DQM1
7 R71 33,0402 PDDR_DQS1 L1 G17 11
DDR_DQS1 L2 DDR_DQS1 MMC0_CLK/GPMC_A24/UART3_CTSN/UART2_RXD/DCAN1_TX/PR1_PRU0_PRU_R30_12/PR1_PRU0_PRU_R31_12/GPIO2_30 G18 MMC0_CLKO
R72 33,0402 PDDR_DQSN1
7 DDR_DQSN1 DDR_DQSN1 MMC0_CMD/GPMC_A25/UART3_RTSN/UART2_TXD/DCAN1_RX/PR1_PRU0_PRU_R30_13/PR1_PRU0_PRU_R31_13/GPIO2_31 MMC0_CMD 11
G16
MMC0_DAT0/GPMC_A23/UART5_RTSN/UART3_TXD/UART1_RIN/PR1_PRU0_PRU_R30_11/PR1_PRU0_PRU_R31_11/GPIO2_29 MMC0_DAT0 11
R73 33,0402 PDDR_ODT G1 G15
B 7 DDR_ODT DDR_ODT MMC0_DAT1/GPMC_A22/UART5_CTSN/UART3_RXD/UART1_DTRN/PR1_PRU0_PRU_R30_10/PR1_PRU0_PRU_R31_10/GPIO2_28 MMC0_DAT1 11 B
DDR_RESETN G2 F18
DDR_RESETN MMC0_DAT2/GPMC_A21/UART4_RTSN/TIMER6/UART1_DSRN/PR1_PRU0_PRU_R30_9/PR1_PRU0_PRU_R31_9/GPIO2_27 MMC0_DAT2 11
TP3 TESTPT1 J3 F17
DDR_VTP MMC0_DAT3/GPMC_A20/UART4_CTSN/TIMER5/UART1_DCDN/PR1_PRU0_PRU_R30_8/PR1_PRU0_PRU_R31_8/GPIO2_26 MMC0_DAT3 11
R74 2.2K,1% J4
VDDS_DDR VREFSSTL
AM335X_ZCZ
7 DDR_VREF

DDR_VTP
R75
2.2K,1%

R76
49.9,1%
DGND

DGND

A A

Title
BeagleBone Processor 1 of 3
Size Document Number Rev
C A6A
450-5500-001
Date: Thursday, June 28, 2012 Sheet 3 of 11
5 4 3 2 1
 5 4 3 2 1

VRTC

R77
4.75K,1%

U5B
K18 8
C6 GMII1_TXCLK/UART2_RXD/RGMII1_TCLK/MMC0_DAT7/MMC1_DAT0/UART1_DCDN/MCASP0_ACLKX/GPIO3_9 K17 RMII1_TXCLK
VDD_ADC 8
2 PMIC_POWR_EN
C5 PMIC_POWER_EN GMII1_TXD0/RMII1_TXD0/RGMII1_TD0/MCASP1_AXR2/MCASP1_ACLKR/EQEP0B_IN/MMC1_CLK/GPIO0_28 K16 RMII1_TXD0
2 WAKEUP EXT_WAKEUP GMII1_TXD1/RMII1_TXD1/RGMII1_TD1/MCASP1_FSR/MCASP1_AXR1/EQEP0A_IN/MMC1_CMD/GPIO0_21 RMII1_TXD1 8
K15
D GMII1_TXD2/DCAN0_RX/RGMII1_TD2/UART4_TXD/MCASP1_AXR0/MMC2_DAT2/MCASP0_AHCLKX/GPIO0_17 RMII1_TXD2 8 D
J18
GMII1_TXD3/DCAN0_TX/RGMII1_TD3/UART4_RXD/MCASP1_FSX/MMC2_DAT1/MCASP0_FSR/GPIO0_16 RMII1_TXD3 8
11 B6 J16 8
AIN0 C7 AIN0 GMII1_TXEN/RMII1_TXEN/RGMII1_TCTL/TIMER4/MCASP1_AXR0/EQEP0_INDEX/MMC2_CMD/GPIO3_3 H17 RMII1_TXEN
R78 11 8
AIN1 B7 AIN1 GMII1_CRS/RMII1_CRS_DV/SPI1_D0/I2C1_SDA/MCASP1_ACLKX/UART5_CTSN/UART2_RXD/GPIO3_1 H16 RMII1_CRS_DV
0,1% 11 8
AIN2 A7 AIN2 GMII1_COL/RMII2_REFCLK/SPI1_SCLK/UART5_RXD/MCASP1_AXR2/MMC2_DAT3/MCASP0_AXR2/GPIO3_0 RMII1_COL
11 AIN3 AIN3
C8 L18
11 AIN4 AIN4 GMII1_RXCLK/UART2_TXD/RGMII1_RCLK/MMC0_DAT6/MMC1_DAT1/UART1_DSRN/MCASP0_FSX/GPIO3_10 RMII1_RXCLK 8
11 B8 M16 8
AIN5 A8 AIN5 GMII1_RXD0/RMII1_RXD0/RGMII1_RD0/MCASP1_AHCLKX/MCASP1_AHCLKR/MCASP1_ACLKR/MCASP0_AXR3/GPIO2_21 L15 RMII1_RXD0
11 AIN6 AIN6 GMII1_RXD1/RMII1_RXD1/RGMII1_RD1/MCASP1_AXR3/MCASP1_FSR/EQEP0_STROBE/MMC2_CLK/GPIO2_20 RMII1_RXD1 8
C9 L16
2 AIN7 AIN7 GMII1_RXD2/UART3_TXD/RGMII1_RD2/MMC0_DAT4/MMC1_DAT3/UART1_RIN/MCASP0_AXR1/GPIO2_19 RMII1_RXD2 8
C28 L17
GMII1_RXD3/UART3_RXD/RGMII1_RD3/MMC0_DAT5/MMC1_DAT2/UART1_DTRN/MCASP0_AXR0/GPIO2_18 RMII1_RXD3 8
0.01uf,16V VREFP_ADC B9 J15
VREFP GMII1_RXERR/RMII1_RXERR/SPI1_D1/I2C1_SCL/MCASP1_FSX/UART5_RTSN/UART2_TXD/GPIO3_2 RMII1_RXERR 8
VREFN_ADC A9 J17 8
VREFN GMII1_RXDV/LCD_MEMORY_CLK/RGMII1_RCTL/UART5_TXD/MCASP1_ACLKX/MMC2_DAT0/MCASP0_ACLKR/GPIO3_4 RMII1_RXDV
A17 H18 U5_H18 R201 33,0402
11 UART2_RXD SPI0_SCLK/UART2_RXD/I2C2_SDA/EHRPWM0A/PR1_UART0_CTS_N/PR1_EDIO_SOF/EMU2/GPIO0_2 RMII1_REFCLK/XDMA_EVENT_INTR2/SPI1_CS0/UART5_TXD/MCASP1_AXR3/MMC0_POW/MCASP1_AHCLKX/GPIO0_29 RMII1_REFCLK 8
B17 M18
11 UART2_TXD SPI0_D0/UART2_TXD/I2C2_SCL/EHRPWM0B/PR1_UART0_RTS_N/PR1_EDIO_LATCH_IN/EMU3/GPIO0_3 MDIO_CLK/TIMER5/UART5_TXD/UART3_RTSN/MMC0_SDWP/MMC1_CLK/MMC2_CLK/GPIO0_1 MDIO_CLK 8
C29 C30 B16 M17
11 I2C1_SDA SPI0_D1/MMC1_SDWP/I2C1_SDA/EHRPWM0_TRIPZONE_INPUT/PR1_UART0_RXD/PR1_EDIO_DATA_IN0/PR1_EDIO_DATA_OUT0/GPIO0_4 MDIO_DATA/TIMER6/UART5_RXD/UART3_CTSN/MMC0_SDCD/MMC1_CMD/MMC2_CMD/GPIO0_0 MDIO_DATA 8
11 A16
I2C1_SCL C15 SPI0_CS0/MMC2_SDWP/I2C1_SCL/EHRPWM0_SYNCI_O/PR1_UART0_TXD/PR1_EDIO_DATA_IN1/PR1_EDIO_DATA_OUT1/GPIO0_5
0.01uf,16V 0.001uf,50V 10,11 CD/EMU4 SPI0_CS1/UART3_RXD/ECAP1_IN_PWM1_OUT/MMC0_POW/XDMA_EVENT_INTR2/MMC0_SDCD/EMU4/GPIO0_6 R1
LCD_DATA0/GPMC_A0//EHRPWM2A//PR1_PRU1_PRU_R30_0/PR1_PRU1_PRU_R31_0/GPIO2_6 GPIO2_6 11,6
E16 R2
10 UART0_RX UART0_TXD/SPI1_CS1/DCAN0_RX/I2C2_SCL/ECAP1_IN_PWM1_OUT/PR1_PRU1_PRU_R30_15/PR1_PRU1_PRU_R31_15/GPIO1_11 LCD_DATA1/GPMC_A1//EHRPWM2B//PR1_PRU1_PRU_R30_1/PR1_PRU1_PRU_R31_1/GPIO2_7 GPIO2_7 11,6
GNDA_ADC E15 R3
10 UART0_TX UART0_RXD/SPI1_CS0/DCAN0_TX/I2C2_SDA/ECAP2_IN_PWM2_OUT/PR1_PRU1_PRU_R30_14/PR1_PRU1_PRU_R31_14/GPIO1_10 LCD_DATA2/GPMC_A2//EHRPWM2_TRIPZONE_INPUT//PR1_PRU1_PRU_R30_2/PR1_PRU1_PRU_R31_2/GPIO2_8 GPIO2_8 11,6
10 E18 R4 11,6
UART0_RTS E17 UART0_CTSN/UART4_RXD/DCAN1_TX/I2C1_SDA/SPI1_D0/TIMER7/PR1_EDC_SYNC0_OUT/GPIO1_8 LCD_DATA3/GPMC_A3//EHRPWM2_SYNCI_O//PR1_PRU1_PRU_R30_3/PR1_PRU1_PRU_R31_3/GPIO2_9 T1 GPIO2_9
GNDA_ADC 10 11,6
UART0_CTS UART0_RTSN/UART4_TXD/DCAN1_RX/I2C1_SCL/SPI1_D1/SPI1_CS0/PR1_EDC_SYNC1_OUT/GPIO1_9 LCD_DATA4/GPMC_A4//EQEP2A_IN//PR1_PRU1_PRU_R30_4/PR1_PRU1_PRU_R31_4/GPIO2_10 T2 GPIO2_10
LCD_DATA5/GPMC_A5//EQEP2B_IN//PR1_PRU1_PRU_R30_5/PR1_PRU1_PRU_R31_5/GPIO2_11 GPIO2_11 11,6
T3
LCD_DATA6/GPMC_A6/PR1_EDIO_DATA_IN6/EQEP2_INDEX/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_6/PR1_PRU1_PRU_R31_6/GPIO2_12 GPIO2_12 11,6
T4
LCD_DATA7/GPMC_A7/PR1_EDIO_DATA_IN7/EQEP2_STROBE/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_7/PR1_PRU1_PRU_R31_7/GPIO2_13 GPIO2_13 11,6
U1 11,6
D15 LCD_DATA8/GPMC_A12/EHRPWM1_TRIPZONE_INPUT/MCASP0_ACLKX/UART5_TXD/PR1_MII0_RXD3/UART2_CTSN/GPIO2_14 U2 UART5_TXD
11 UART1_TXD UART1_TXD/MMC2_SDWP/DCAN1_RX/I2C1_SCL//PR1_UART0_TXD/PR1_PRU0_PRU_R31_16/GPIO0_15 LCD_DATA9/GPMC_A13/EHRPWM1_SYNCI_O/MCASP0_FSX/UART5_RXD/PR1_MII0_RXD2/UART2_RTSN/GPIO2_15 UART5_RXD 11,6
D16 U3
11 UART1_RXD UART1_RXD/MMC1_SDWP/DCAN1_TX/I2C1_SDA//PR1_UART0_RXD/PR1_PRU1_PRU_R31_16/GPIO0_14 LCD_DATA10/GPMC_A14/EHRPWM1A/MCASP0_AXR0//PR1_MII0_RXD1/UART3_CTSN/GPIO2_16 UART3_CTSN 11,6
D18 U4
11 I2C2_SDA UART1_CTSN/TIMER6/DCAN0_TX/I2C2_SDA/SPI1_CS0/PR1_UART0_CTS_N/PR1_EDC_LATCH0_IN/GPIO0_12 LCD_DATA11/GPMC_A15/EHRPWM1B/MCASP0_AHCLKR/MCASP0_AXR2/PR1_MII0_RXD0/UART3_RTSN/GPIO2_17 UART3_RTSN 11,6
D17 V2
11 I2C2_SCL UART1_RTSN/TIMER5/DCAN0_RX/I2C2_SCL/SPI1_CS1/PR1_UART0_RTS_N/PR1_EDC_LATCH1_IN/GPIO0_13 LCD_DATA12/GPMC_A16/EQEP1A_IN/MCASP0_ACLKR/MCASP0_AXR2/PR1_MII0_RXLINK/UART4_CTSN/GPIO0_8 UART4_CTSN 11,6
V3 11,6
C16 LCD_DATA13/GPMC_A17/EQEP1B_IN/MCASP0_FSR/MCASP0_AXR3/PR1_MII0_RXER/UART4_RTSN/GPIO0_9 V4 UART4_RTSN
2,7 I2C0_SCL I2C0_SCL/TIMER7/UART2_RTSN/ECAP1_IN_PWM1_OUT////GPIO3_6 LCD_DATA14/GPMC_A18/EQEP1_INDEX/MCASP0_AXR1/UART5_RXD/PR1_MII_MR0_CLK/UART5_CTSN/GPIO0_10 UART5_CTSN 11,6
C17 T5
2,7 I2C0_SDA I2C0_SDA/TIMER4/UART2_CTSN/ECAP2_IN_PWM2_OUT////GPIO3_5 LCD_DATA15/GPMC_A19/EQEP1_STROBE/MCASP0_AHCLKX/MCASP0_AXR3/PR1_MII0_RXDV/UART5_RTSN/GPIO0_11 UART5_RTSN 11,6
N17 V5
9 USB0_DP USB0_DP LCD_PCLK/GPMC_A10//PR1_EDIO_DATA_IN4/PR1_EDIO_DATA_OUT4/PR1_PRU1_PRU_R30_10/PR1_PRU1_PRU_R31_10/GPIO2_24 GPIO2_24 11
9 N18 U5 11
USB0_DM M15 USB0_DM LCD_VSYNC/GPMC_A8//PR1_EDIO_DATA_IN2/PR1_EDIO_DATA_OUT2/PR1_PRU1_PRU_R30_8/PR1_PRU1_PRU_R31_8/GPIO2_22 R5 GPIO2_22
C 11 C
P16 USB0_CE LCD_HSYNC/GPMC_A9//PR1_EDIO_DATA_IN3/PR1_EDIO_DATA_OUT3/PR1_PRU1_PRU_R30_9/PR1_PRU1_PRU_R31_9/GPIO2_23 R6 GPIO2_23
USB0_ID 11
F16 USB0_ID LCD_AC_BIAS_EN/GPMC_A11//PR1_EDIO_DATA_IN5/PR1_EDIO_DATA_OUT5/PR1_PRU1_PRU_R30_11/PR1_PRU1_PRU_R31_11/GPIO2_25 GPIO2_25
TP4 TESTPT1
P15 USB0_DRVVBUS/GPIO0_18
9 USB0_VBUS USB0_VBUS A14 11
R17 MCASP0_AHCLKX/EQEP0_STROBE/MCASP0_AXR3/MCASP1_AXR1/EMU4/PR1_PRU0_PRU_R30_7/PR1_PRU0_PRU_R31_7/GPIO3_21 A13 GPIO3_21
8 USB1_DP USB1_DP MCASP0_ACLKX/EHRPWM0A//SPI1_SCLK/MMC0_SDCD/PR1_PRU0_PRU_R30_0/PR1_PRU0_PRU_R31_0/GPIO3_14 SPI1_SCLK 11
R18 B13
8 USB1_DM USB1_DM MCASP0_FSX/EHRPWM0B//SPI1_D0/MMC1_SDCD/PR1_PRU0_PRU_R30_1/PR1_PRU0_PRU_R31_1/GPIO3_15 SPI1_D0 11
P18 D12
USB1_CE MCASP0_AXR0/EHRPWM0_TRIPZONE_INPUT//SPI1_D1/MMC2_SDCD/PR1_PRU0_PRU_R30_2/PR1_PRU0_PRU_R31_2/GPIO3_16 SPI1_D1 11
P17 C12
8 USB1_ID USB1_ID MCASP0_AHCLKR/EHRPWM0_SYNCI_O/MCASP0_AXR2/SPI1_CS0/ECAP2_IN_PWM2_OUT/PR1_PRU0_PRU_R30_3/PR1_PRU0_PRU_R31_3/GPIO3_17 SPI1_CS0 11
F15 B12
8 USB1_DRVVBUS
T18 USB1_DRVVBUS/GPIO3_13 MCASP0_ACLKR/EQEP0A_IN/MCASP0_AXR2/MCASP1_ACLKX/MMC0_SDWP/PR1_PRU0_PRU_R30_4/PR1_PRU0_PRU_R31_4/GPIO3_18 C13
8 USB1_VBUS USB1_VBUS MCASP0_FSR/EQEP0B_IN/MCASP0_AXR3/MCASP1_FSX/EMU2/PR1_PRU0_PRU_R30_5/PR1_PRU0_PRU_R31_5/GPIO3_19 GPIO3_19 11
D13
MCASP0_AXR1/EQEP0_INDEX//MCASP1_AXR0/EMU3/PR1_PRU0_PRU_R30_6/PR1_PRU0_PRU_R31_6/GPIO3_20

R217 GPIO0_7SRC C18

11 GPIO0_7 ECAP0_IN_PWM0_OUT/UART3_TXD/SPI1_CS1/PR1_ECAP0_ECAP_CAPIN_APWM_O/SPI1_SCLK/MMC0_SDWP/XDMA_EVENT_INTR2/GPIO0_7 GPIO3_20 3
0,1%
AM335X_ZCZ

R202 GPIO3_18
0,1%

B B

A A

Title
BeagleBone Processor 2 of 3
Size Document Number Rev
C A6A
450-5500-001
Date: Thursday, June 28, 2012 Sheet 4 of 11
5 4 3 2 1
 5 4 3 2 1

VDD_3V3A

VDD_CORE

C42 C51
VDD_CORE 0.01uf,16V 0.01uf,16V
DGND
C31 C32 C33 C34 C35 C49 C36 C37 C38 C39 C40 C41 C53 C54 C55 C48 C50 U5C
F6 P7 C43 C52
10uF,10V 10uF,10V F7 VDD_CORE1 VDDSHV1 P8 0.01uf,16V 0.01uf,16V
D VDD_CORE2 VDDSHV1 D
G6
G7 VDD_CORE3
G10 VDD_CORE4 P10

10uF,10V
VDD_CORE5 VDDSHV2

0.01uf,16V
0.01uf,16V
0.01uf,16V
0.01uf,16V
0.01uf,16V
0.01uf,16V
0.01uf,16V
0.01uf,16V
0.01uf,16V
0.01uf,16V
0.01uf,16V
0.01uf,16V
0.01uf,16V
0.01uf,16V
H11 P11
J12 VDD_CORE6 VDDSHV2 C56 C57
DGND K6 VDD_CORE7
K8 VDD_CORE8 P12 0.01uf,16V 0.01uf,16V
K12 VDD_CORE9 VDDSHV3 P13
VDD_CORE10 VDDSHV3 DGND
L6
L7 VDD_CORE11 C58 C59
L8 VDD_CORE12
VDD_MPU L9 VDD_CORE13 H14 0.01uf,16V 0.01uf,16V
M11 VDD_CORE14 VDDSHV4 J14
M13 VDD_CORE15 VDDSHV4
N8 VDD_CORE16
N9 VDD_CORE17
C44 C45 C46 C47 N12 VDD_CORE18 K14
VDD_MPU N13 VDD_CORE19 VDDSHV5 L14
10uF,10V VDD_CORE20 VDDSHV5 C60 C61
F10
F11 VDD_MPU1 0.01uf,16V 0.01uf,16V
F12 VDD_MPU2 E10
VDD_MPU3 VDDSHV6 DGND

0.01uf,16V
0.01uf,16V
F13 E11
VDD_MPU4 VDDSHV6

0.01uf,16V
G13 E12 C70 C62 C63 C64 C65 C66 C67 C68 C69
DGND H13 VDD_MPU5 VDDSHV6 E13 C71
VDD_PLL J13 VDD_MPU6 VDDSHV6 F14 0.01uf,16V 0.01uf,16V 0.01uf,16V 0.01uf,16V0.01uf,16V0.01uf,16V 0.01uf,16V 0.01uf,16V 10uF,10V
TP5 VDD_MPUON A2 VDD_MPU7 VDDSHV6 G14 0.01uf,16V
TESTPT1 VDD_MPU_MON VDDSHV6 N5
FB1 CAP_VDD_SRAM_CORE D9 VDDSHV6 P5
1 2 H15 CAP_VDD_SRAM_CORE VDDSHV6 P6
VDD_1V8 VDDS_PLL_MPU VDDSHV6
150OHM800mA D10
CAP_VDD_SRAM_MPU D11 VDDS_SRAM_MPU_BB
C72 C73 CAP_VBB_MPU C10 CAP_VDD_SRAM_MPU E6
CAP_VBB_MPU VDDS VDD_1V8
E9 E14
VDD_1V8 VDDS_SRAM_CORE_BG VDDS
0.01uf,16V 0.01uf,16V F9 C74 C75 C76 C77 C78 C79
VDDS K13
N15 VDDS N6 0.01uf,16V 0.01uf,16V 0.01uf,16V 0.01uf,16V 0.01uf,16V 0.01uf,16V
C VDD_3V3A C
DGND DGND N16 VDDA3P3V_USB0 VDDS P9
VDD_1V8 VDDA1P8V_USB0 VDDS P14
VDDS

C83
C84
C85
C80 C82 M14
C81 VSSA_USB VDD_ADC DGND
R15 FB2
R16 VDDA3P3V_USB1 D8 1 2
VDDA1P8V_USB1 VDDA_ADC VDD_1V8
FB3

1uF,10V
1uF,10V
1uF,10V
N14 E8 150OHM800mA 1 2
VSSA_USB VSSA_ADC

0.01uf,16V
0.01uf,16V
0.01uf,16V
M5 150OHM800mA
DGND E7 VPP R10
VDD_1V8 VDDS_PLL_DDR VDDS_PLL_CORE_LCD VDD_PLL
DGND GNDA_ADC DGND
E5
C86 F5 VDDS_DDR D7 C87 C88
VDDS_DDR VDDS_RTC VRTC
0.01uf,16V G5 D6 VDD_RTC 0.01uf,16V 0.01uf,16V
H5 VDDS_DDR CAP_VDD_RTC B4 ENZ_KALDO_1P8V
J5 VDDS_DDR ENZ_KALDO_1P8V
K5 VDDS_DDR GNDA_ADC DGND
VDDS_DDR DGND L5 VDDS_DDR R11
VDDS_DDR VDDS_OSC VDD_PLL
TP6
A3 TESTOUT
TESTOUT

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C89 C90 C91 C92 C93 C94 C95 C96 TESTPT1 R79 C97 C98 C99
AM335X_ZCZ

J6
J7
J8
J9

F8

A1
K7
K9
V1

H6
H7
H8
H9
N7

G8
G9
M6
M7
M8
M9
10uF,10V 0.01uf,16V 0.01uf,16V 0.01uf,16V 0.01uf,16V 0.01uf,16V 0.01uf,16V 0.01uf,16V 1uF,10V 0.01uf,16V 0.01uf,16V

J10
J11
L10
L11
L12
L13

A18
K10
K11
V18

H10
H12
N10
N11

G11
G12
M10
M12
10K,1%

DGND DGND

DGND DGND

B B

A A

Title
BeagleBone Processr 3 of 3
Size Document Number Rev
C A6A
450-5500-001
Date: Thursday, June 28, 2012 Sheet 5 of 11
5 4 3 2 1
 5 4 3 2 1

VDD_3V3A SYS_5V

2
FB4
150OHM800mA

R80
R81
R82
R83
R84
R85
R86
R87
R88
R89
R90
R91
R92
R93
R94
R95
VDD_LED

1
D D

100K,1%
100K,1%
100K,1%
100K,1%,DNI
100K,1%
100K,1%,DNI
100K,1%,DNI
100K,1%,DNI
100K,1%,DNI
100K,1%,DNI
100K,1%,DNI
100K,1%,DNI
100K,1%,DNI
100K,1%,DNI
100K,1%
100K,1%,DNI
R97 R98 R99
SYS_BOOT0 11,4 R96 470,5% 470,5% 470,5%
GPIO2_6
SYS_BOOT1 11,4 C100 470,5%
GPIO2_7
SYS_BOOT2 11,4 4.7uF,6.3V
GPIO2_8
SYS_BOOT3 GPIO2_9 11,4
SYS_BOOT4 GPIO2_10 11,4
SYS_BOOT5 GPIO2_11 11,4
SYS_BOOT6 GPIO2_12 11,4 DGND USR0 USR1

LEDAA
LEDBA
LEDCA
LEDDA

SYS_BOOT7 GPIO2_13 11,4

USR2 USR3
SYS_BOOT8 UART5_TXD 11,4
SYS_BOOT9 UART5_RXD 11,4
SYS_BOOT10 11,4 TP10 TESTPT1 TP11 TESTPT1 TP12 TESTPT1 TP13 TESTPT1
UART3_CTSN
SYS_BOOT11 UART3_RTSN 11,4
SYS_BOOT12 UART4_CTSN 11,4
SYS_BOOT13 11,4 D2 D3 D4 D5
UART4_RTSN
SYS_BOOT14 UART5_CTSN 11,4

GRN
GRN
GRN
GRN

SYS_BOOT15 UART5_RTSN 11,4

598-8170-107F
LEDDC

598-8170-107F 598-8170-107F

R100
R101
R102
R103
R104
R105
R106
R107
R108
R109
R110
R111
R112
R113
R114
R115
LEDAC
LEDBC
LEDCC

C
Boot Configuration 598-8170-107F C

3
6
3

User LED's

6
Q1B Q2A Q2B

10k
10k
10k

Q1A 5 2 5

10k
2 DMC56404 DMC56404 DMC56404
3 USR0 DMC56404

42.2K,1%,DNI
42.2K,1%,DNI
42.2K,1%,DNI
42.2K,1%
42.2K,1%,DNI
42.2K,1%
42.2K,1%
42.2K,1%
42.2K,1%
42.2K,1%
42.2K,1%
42.2K,1%
42.2K,1%
42.2K,1%
42.2K,1%,DNI
42.2K,1%
47k
47k
47k

47k
R116 R117 R118
4
1
4

DGND 100K,1% 100K,1% 100K,1% R119

1
100K,1%

BOOT ORDER....MMC....SPI....UART....USB......24MHZ DGND DGND DGND

DGND DGND
DGND DGND DGND
3 USR1
3 USR2
3 USR3

B B

RESET BUTTON
S1
B3U-1100
1 2 10,3
SYS_WARMRESETn
C101

3
1uF,10V,DNI

DGND DGND

A A

Title
BeagleBone LED, Configuration and Reset
Size Document Number Rev
B A6A
450-5500-001
Date: Thursday, June 28, 2012 Sheet 6 of 11
5 4 3 2 1
 5 4 3 2 1

DDR_A[13..0] 3
U6
3 J8 M8 DDR_A0
DDR_CLK CK A0
3 K8 M3 DDR_A1
DDR_CLKn CKn A1
3 K2 M7 DDR_A2
DDR_CKE CKE A2
3 L8 N2 DDR_A3
DDR_CSn CSn A3
3 K7 N8 DDR_A4
DDR_RASn RASn A4
3 L7 N3 DDR_A5
DDR_CASn CASn A5
3 K3 N7 DDR_A6
D DDR_WEn WEn A6 D
3 P2 DDR_A7
DDR_D[15..0] A7
DDR_D0 G8 P8 DDR_A8
DDR_D1 G2 DQ0 A8 P3 DDR_A9
DDR_D2 H7 DQ1 A9 M2 DDR_A10
DDR_D3 H3 DQ2 A10 P7 DDR_A11
DDR_D4 H1 DQ3 A11 R2 DDR_A12
DDR_D5 H9 DQ4 A12 R8 DDR_A13R 0,1% DDR_A13
DDR_D6 F1 DQ5 (RFU)A13 R120
DQ6 DDR_BA[2..0] 3
DDR_D7 F9 L2 DDR_BA0
DDR_D8 C8 DQ7 BA0 L3 DDR_BA1 Variable & MAC Memory
DQ8 BA1 VDD_3V3B
DDR_D9 C2 L1 DDR_BA2
DDR_D10 D7 DQ9 BA2 U7
DDR_D11 D3 DQ10 6 8
DQ11 2,4 I2C0_SCL SCL VCC
DDR_D12 D1 K9 3 2,4 5
DQ12 ODT DDR_ODT I2C0_SDA SDA
DDR_D13 D9 C102
DDR_D14 B1 DQ13 A9 4 0.1uf,16V
DDR_D15 B9 DQ14 VDDQ C1 1 VSS
DQ15 VDDQ VDDS_DDR A0
C3 2
B7 VDDQ C7 3 A1 7 WP
3 DDR_DQS1 UDQS VDDQ A2 WP
3 A8 C9 R210 10K,1% DGND
DDR_DQSN1 UDQSn VDDQ
3 B3 E9 CAT24C256W
DDR_DQM1 UDM VDDQ
3 E8 G1 256KX8
DDR_DQSN0 LDQSn VDDQ
3 F7 G3 DGND
DDR_DQS0 LDQS VDDQ
C 3 F3 G7 C
DDR_DQM0 LDM VDDQ VDDS_DDR
G9
VDDQ TP2
TESTPT1
VDDS_DDR A1 H8
E1 VDD VSSQ B2 C103 C104 C105 C106 C107 C108 C109 C110 C111
M9 VDD VSSQ D2
R1 VDD VSSQ F2 0.01uf,16V 0.01uf,16V 0.01uf,16V 0.01uf,16V 0.01uf,16V 0.01uf,16V 0.01uf,16V 0.01uf,16V 0.01uf,16V
J9 VDD VSSQ H2
VDD VSSQ A7
VSSQ E7
E3 VSSQ B8
P9 VSS VSSQ D8 DGND
VDDS_DDR VSS VSSQ
J3 F8
N1 VSS VSSQ
A3 VSS J1
VSS VDDL VDDS_DDR
R7
C112 C113 C114 C115 C117 R3 RFU2 J7
C116 E2 RFU1 VSSDL
0.01uf,16V
0.01uf,16V 0.01uf,16V0.01uf,16V0.01uf,16V A2 NC1 J2
NC2 VREF DDR_VREF 3
22uF,6.3V
MT47H128M16RT-25E:C
C118
DDR2 SDRAM 0.01uf,16V
B DGND DGND B
DGND DGND

A A

Title
BeagleBone DDR2 Memory
Size Document Number Rev
B A6A
450-5500-001
Date: Thursday, June 28, 2012 Sheet 7 of 11
5 4 3 2 1
 5 4 3 2 1

VDD_PHYA

VDD_3V3B C119 C120 C121

0.1uf,16V 0.1uf,16V 4.7uF,6.3V
1 2
150OHM800mA FB5
DGND DGND
DGND
C122
0.1uf,16V NOTE: There are two different configuration
PHY_VDDCR VDD_PHYA connectors used for P10. The difference is
DGND C124 that the TX and RX pairs are swapped.
C123 470pF C125
0.1uf,16V 50V 1uF,10V
Either of these can be used as the ETHERNET
5%

R131
R129
R130
R133
R134
D
AUTO_MDIX feature in the LAN8710A will D
compensate by swapping the TX and Rx on CONNECTOR

12
1
27
6
DGND DGND
the LAN8710.

49.9,1%
49.9,1%
49.9,1%
49.9,1%
P10
R209 10,1%,DNI 5
4 RMII1_REFCLK TCT
29 TXP 3

VDDIO
VDD2A
VDD1A

1.5K,5%
TXP TD+

VDDCR
16 28 TXN 6
4 MDIO_DATA MDIO TXN TD-
17 1 7
4 MDIO_CLK MDC RD+ NC
R205 100,1% RXD3/PHYAD2 8 2
4 RMII1_RXD3 RXD3/PHYAD2 RD-
R153 100,1% RXD2/RMIISEL 9 31 RXP 4 8
4 RMII1_RXD2 RXD2/RMIISEL RXP RCT GND
4 R132 100,1% RXD1/MODE1 10 30 RXN
RMII1_RXD1 RXD0/MODE0 11 RXD1/MODE1 RXN YEL_C 11 13
4 R135 100,1% R16 470,5%
RMII1_RXD0 26 RXD0/MODE0 12 YELC SHD1 14
4 R208 100,1% RXDV C126 C127 C128 C129 YELA
RMII1_RXDV 7 RXDV 10 YELA SHD2
4 R136 100,1% REFCLKO R128 470,5% GRN_C DGND
RMII1_RXCLK 13 RXCLK/PHYAD1 9 GRNC
4 R137 100,1% RXER/PHYAD0 15pF,DNI 15pF,DNI 15pF,DNI GRNA
RMII1_RXERR RXER/RXD4/PHYAD0 GRNA
15pF,DNI
R206 100,1% TXCLK 20 U15 WE_7499010211A
4 RMII1_TXCLK TXCLK
21 DGND DGND DGND DGND DGND R138
4 RMII1_TXEN TXEN
22 R219
4 RMII1_TXD0 TXD0 LAN8710A ESD_RING
23 10K,1% TCT_RCT
4 RMII1_TXD1 TXD1
4 24
RMII1_TXD2 25 TXD2
4 R142 .1,0805
RMII1_TXD3 15 TXD3
4 R207 100,1% COL/CRS_DV/MODE2 C130 0,1%
RMII1_COL 14 COL/CRS_DV/MODE2 VDD_3V3B VDD_PHYA
4 R139 100,1% CRS_DV/MODE2 ACTIVE WHEN LINK PRESENT. DGND
RMII1_CRS_DV CRS 3 BLINKS OFF DURING ACTIVITY. 0.022uF,10V DGND
R200 0,1%,DNI LED1/REGOFF 2 LED2 ACTIVE WHEN AT 100MB
19 LED2/nINTSEL
11,3 SYS_RESETn nRST PHYAD0 MODE2 MODE1 MODE0 RMISEL PHYAD1 PHYAD0
18 DGND
R140 PHY_XTAL1 R199 0,1% 5
RCLKIN nINT/TXER/TXD4
1M,1%,DNI XTAL1/CLKIN

R126
R123
R124
PHY_XTAL2 4 32 RBIAS

R211
R213
R215
XTAL2 RBIAS

GND_EP
R220

10K,1%R122
R144 QFN32_5X5MM_EP3P3MM R145 10K,1%

10K,1%

33
10,1% 12.1K,1%

10K,1%
RXD0/MODE0
Y4
C C

10K,1%,DNI
10K,1%,DNI

PHYX 2 1 RXD1/MODE1

10K,1%,DNI
10K,1%,DNI

25.000MHz CRS_DV/MODE2
C131 XTAL2_5X3P2_SMD C132 DGND DGND
DGND RXER/PHYAD0
30pF,50V 30pF,50V
RXD2/RMIISEL
This mode pin setting connects to the wrong pin
RXD3/PHYAD2
DGND DGND on the LAN8710. It should go to pin 15 instead.
For this revision R122 is not installed as it does nINT/RXCLK/PHYAD1

not do what it is intended to do. This removes the

pullup from pin 14. This will be addressed on the
R5

next revision of the board.

R125
R127
R198
R212
R214
R216

10K,1%
10K,1%
10K,1%
10K,1%

10K,1%,DNI
10K,1%,DNI

10K,1%,DNI

P2
USB1_VBUS 4 USB-A Conn. - 87520-xx1xx
DGND
1 VBUS SHIELD
5
2 D-
4 USB1_DM
3 D+
4 USB1_DP
4 GND SHIELD
6
4 USB1_ID
SYS_5V

U9 DGND
B B
2 8
3 IN OUT 7
4 IN OUT 6
4 USB1_DRVVBUS EN OUT VDD_3V3B
USB HOST CONNECTOR
1 5 R146 U10
GND OC 9 0,1% 1 6
PAD D+ VBUS C134
R147 + TPS2051 (DGN) R148 2 0.01uf,16V
10K,1% C133 10K,1% D- 5
100uF,6.3V 3 NC
DGND ID 4
GND
DGND 3 TPD4S012
USB1_OC
DGND DGND
DGND DGND

A A

Title
BeagleBone Ethernet and USB Host
Size Document Number Rev
C A6A
450-5500-001
Date: Thursday, June 28, 2012 Sheet 8 of 11
5 4 3 2 1
 5 4 3 2 1

USB_DC

USB_DC

9
8
G4
G5
R149 U11 USB2412_QFN28 5
100K,1% 4 G1 SYS_5V
Upstream ID USB PC
22 USBDP_UP 3
VBUS_DET 18 USBDP_UP 21 USBDM_DN 2 D+
VBUS_DET USBDM_UP 1 D- CONNECTOR
VB

G2
G3
D R151 D
100K,1% DGND P3 mini USB-B

7
6
1 10 R152
Downstream 1 USBDP_DN1 FT_DP
4.75K,1%
28 10
USBDM_DN1 FT_DM
DGND 8
OCS1 7 U16B
PRTPWR1 FT_VBUS 10
3 4 4
USB0_VBUS
2 3 4 SN74LVC2G07DCK
DownstreamUSBDP_DN2 USB0_DP
12 2 VDD_3V3B
OCS2 USBDM_DN2 USB0_DM 4
11 USB0_VBUS_PWR
PRTPWR2
R154 R155
VDD_3V3B NON_REM[0:1]/nc 5 10K,1%,DNI 10K,1%,DNI
NC
TP7
13 NON_REM1
R156 NON_REM1 19 NON_REM2
100K,1% SUSP_IND/NON_REM0

RESETn 17 26 HUB_BIAS R157 12.1K,1% R158 R159 TESTPT1

RESET RBIAS DGND
C
10K,1% 100K,1% C
Common VDD_3V3B
6
C136 TEST 14
0.1uf,16V VDD33 10 DGND
DGND VDDCRREF/VDD33 DGND
DGND C138 C139 C140
C137
XTALIN 24 0.1uf,16V 4.7uF,6.3V 0.1uf,16V
XTALIN/CLKIN
4
18pF,50V Y5 24MHz VDD33 20 DGND DGND DGND

3
R160 VDD33 27
4 2 VDDPLLREF/VDD33
1M,1%,DNI
C141 C142 C143

1
C144
0.1uf,16V 0.1uf,16V 0.1uf,16V
XTALOUT 23
XTALOUT
TP8
9 CRFILT
18pF,50V HS_IND 16 CRFILT
HS_IND DGND

DGND TESTPT1
B R161 rsvd3 15 25 PLLFILT B
0,1% VSS PLLFILT
29 C145 C146
VSS(FLAG)

0.1uf,16V,DNI 0.1uf,16V,DNI
DGND

DGND DGND

A A

Title
BeagleBone USB Concentrator
Size Document Number Rev
B A6A
450-5500-001
Date: Thursday, June 28, 2012 Sheet 9 of 11
5 4 3 2 1
 5 4 3 2 1

C161 0.1uf,16V DGND

C158 0.1uf,16V VDD_3V3B VDD_3V3B VDD_3V3B
VDD_3V3B

1 2 FB6 VDD_FTVPLL R162 C157 0.1uf,16V C149 0.1uf,16V

150OHM800mA VDD_3V3B

D 1 2 FB7
VDD_FTVPHY D
150OHM800mA C147 0.1uf,16V DGND DGND
1 2 FB8 VDD_FTREGIN 4.75K,1%
150OHM800mA
C148 0.1uf,16V

8
5
U14B U16A
5
C150 0.1uf,16V 3 FT_SRESETn R172 0,1% 1 6 FT_SRESETB 0,1%
SYS_WARMRESETn 3,6
FT_VBUS 6 SN74LVC2G07DCK R163
SN74LVC2G00DCU
C151 0.1uf,16V

4
2
C152 C162 C163 C164
DGND

4
9
12
37
64
20
31
42
56
4.7uF,6.3V 0.1uf,16V 0.1uf,16V 0.1uf,16V U12

50 VDD_3V3B DGND DGND

VREGIN

VPLL
VPHY
VDD_1V8FT 49

VCCIOA
VCCIOB
VCCIOB
VCCIOD

VCOREB
VCOREA

VCOREC
VREGOUT 16 F_ADBUS0 R164 0,1%
ADBUS0 JTAG_TCK 3
DGND 17 F_ADBUS1 R165 0,1% 3
ADBUS1 JTAG_TDI
18 F_ADBUS2 R166 0,1% 3
R167 12.1K,1% FT_REF 6 ADBUS2 19 F_ADBUS3 R168 0,1% JTAG_TDO
DGND REF ADBUS3 JTAG_TMS 3
C
21 F_ADBUS4 R169 0,1% 3 C
ADBUS4 JTAG_TRSTn
22
7 ADBUS5 23 F_ADBUS6 R170 0,1%
9 FT_DM USBDM ADBUS6 JTAG_EMU0 3
9 8 24
FT_DP USBDP ADBUS7
JTAG_EMU1 3
26 FT_SRESET
ACBUS0 27 REMU_RSTn
ACBUS1 28
ACBUS2 29 VDD_3V3B
ACBUS3 30 F_ADBUS7 R171 0,1%
C153 27pF,50V XTIN 2 ACBUS4 32 VDD_3V3B
DGND OSCIN ACBUS5 33
ACBUS6 34 R179
Y6 ACBUS7 4.75K,1%
12.000MHz 38 VDD_3V3B C154
BDBUS0 UART0_TX 4
50ppm 39 4
BDBUS1 UART0_RX
40 4 0.01uf,16V
VDD_3V3B BDBUS2 UART0_CTS
DGND C155 27pF,50V XTOUT 3 41 4
OSC0 BDBUS3 UART0_RTS OPTIONAL JTAG
43
BDBUS4 44 R176 DGND P7
BDBUS5 45 DGND 1 2
R175 FT_RESETn 14 BDBUS6 46 3 TMS TRSTn 4 TDIS
R174 10K,1% 2.2K,1% RESET BDBUS7 5 TDI TDIS 6 R177 0,DNI
R173 10K,1% 48 VDD_3V3B 7 TVDD NC 8
U13 BCBUS0 52 4.75K,1% R178 0,DNI RTCK 9 TDO GND 10
B B
6 5 F_EECS 63 BCBUS1 53 R180 0,DNI TCK 11 TCKRTN GND 12
VCC CS 4 F_EESK 62 EECS BCBUS2 54 R181 13 TCK GND 14 DGND
SK 3 F_EEDATA 61 EECLK BCBUS3 55 10K,1%,DNI EMU_RSTn 15 EMU0 EMU1 16
2 DIN 1 EEDATA BCBUS4 57 R182 100,1%,DNI EMU2R 17 SRST GND 18 EMU3R R184
GND DOUT BCBUS5 3XDMA_EVENT_INTR0 EMU2 EMU3 CLKOUT2 11,3
58 11,4 R183 0,DNI EMU4R 19 20 0,DNI
93LC56B_SOT23-6 BCBUS6 59 CD/EMU4 R185 0,DNI EMU4 GND
BCBUS7 FT_VBUS 9
CTI JTAG,DNI R186
13 4.75K,1%
TEST

F_EEDOUT
DGND C156
60
PWREN 0.1uf,16V
R188
R187 10K,1% 2.2K,1% 36 DGND DGND
DGND SUSPEND DGND

AGND
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
FT2232LQFN64

1
5

10
11
15
25
35
47
51
A DGND A

Title
BeagleBone Serial and JTAG
Size Document Number Rev
B A6A
450-5500-001
Date: Thursday, June 28, 2012 Sheet 10 of 11
5 4 3 2 1
 5 4 3 2 1

P8 P9

1 2 DGND 1 2 DGND
3 3 4 3 VDD_3V3EXP 3 4 VDD_3V3EXP
GPIO1_6 GPIO1_7
3 5 6 3 VDD_5V 5 6 VDD_5V
GPIO1_2 GPIO1_3
3 7 8 3 SYS_5V 7 8 SYS_5V
TIMER4 TIMER7
3 9 10 3 2 9 10 3,8
D TIMER5 TIMER6 PWR_BUT SYS_RESETn D
3 11 12 3 3 11 12 3
GPIO1_13 GPIO1_12 UART4_RXD GPIO1_28
3 13 14 3 3 13 14 3
EHRPWM2B GPIO0_26 UART4_TXD EHRPWM1A
3 15 16 3 3 15 16 3
GPIO1_15 GPIO1_14 GPIO1_16 EHRPWM1B
3 17 18 3 4 17 18 4
GPIO0_27 GPIO2_1 I2C1_SCL I2C1_SDA
3 19 20 GPIO1_31 3 4 19 20 4
EHRPWM2A I2C2_SCL I2C2_SDA
3 21 22 GPIO1_5 3 4 21 22 4
GPIO1_30 UART2_TXD UART2_RXD
3 23 24 GPIO1_1 3 3 23 24 4
GPIO1_4 GPIO1_17 UART1_TXD
3 25 26 GPIO1_29 3 4 25 26 4
GPIO1_0 GPIO3_21 UART1_RXD
4 27 28 4 4 27 28 4
GPIO2_22 GPIO2_24 GPIO3_19 SPI1_CS0
4 29 30 4 4 SPI1_D0 29 30 4
GPIO2_23 GPIO2_25 SPI1_D1
4,6 31 32 4,6 4 31 32 VDD_ADC
UART5_CTSN UART5_RTSN SPI1_SCLK
4,6 33 34 4,6 4 33 34
UART4_RTSN UART3_RTSN AIN4
4,6 35 36 4,6 4 35 36 4
UART4_CTSN UART3_CTSN AIN6 AIN5
4,6 37 38 4,6 4 37 38 4
UART5_TXD UART5_RXD AIN2 AIN3
4,6 39 40 4,6 4 39 40 4
GPIO2_12 GPIO2_13 AIN0 AIN1
4,6 41 42 4,6 10,3 41 42 4
GPIO2_10 GPIO2_11 CLKOUT2 GPIO0_7
4,6 43 44 4,6 43 44
GPIO2_8 GPIO2_9
4,6 45 46 4,6 45 46
GPIO2_6 GPIO2_7
FEMALE HEADER 2x23 FEMALE HEADER 2x23 GNDA_ADC

DGND DGND
DGND DGND
C EXPANSION HEADER C

EXPANSION HEADER

VDD_3V3A SYS_VOLT

VDD_3V3EXP
VDD_3V3A U8
8 1
2 IN OUT 6
C6 5 NC1 NC2 7
C159 9 EN NC3
C160 4.7uF,6.3V 4 PAD 3 3V3EXP_FB R150 52.3K,1%
10uF,10V 0.1uf,16V GND FB

R190
R191
R192
R193
R194
R195
TPS73701DRBR R189
C166 0.1uf,16V
30.1K,1%
DGND DGND
B B

P4 DGND

10K,1%
10K,1%
10K,1%
10K,1%
10K,1%
10K,1%
3 1 9 DGND
MMC0_DAT2 DAT2 GND
3 2 10
MMC0_DAT3 CD/DAT3 CD
3 3 11 SD_CD VDD_3V3B
MMC0_CMD CMD GND1
4 12 R196 10K,1%
5 VDD GND2 13
3 MMC0_CLKO CLOCK GND3
6 14 R197
7 VSS GND4
3 MMC0_DAT0 DAT0
3 8
MMC0_DAT1 DAT1 microSD 0,1%
MOLEX 502570-001

DGND

10,4
uSD CONNECTOR
CD/EMU4

A A

Title
BeagleBone Expansion Headers, SD/MMC.and LDO
Size Document Number Rev
B A6A
450-5500-001
Date: Thursday, June 28, 2012 Sheet 11 of 11
5 4 3 2 1