William Stallings

Computer Organization
and Architecture
8th Edition

Chapter 5
Internal Memory
 Semiconductor Memory Types
Memory Type Category Erasure Write Mechanism Volatility

Random-access
Read-write memory Electrically, byte-level Electrically Volatile
memory (RAM)

Read-only
Masks
memory (ROM)
Read-only memory Not possible

Programmable
ROM (PROM)

Erasable PROM
UV light, chip-level
(EPROM) Nonvolatile

Electrically

Electrically Erasable Read-mostly memory

Electrically, byte-level
PROM (EEPROM)

Flash memory Electrically, block-level

Semiconductor Memory
• RAM
—Read/Write
—Volatile
—Temporary storage
—Static or dynamic
Memory Cell Operation
Dynamic RAM
• Bits stored as charge in capacitors
• Charges leak
• Need refreshing even when powered
• Simpler construction
• Smaller per bit
• Less expensive
• Need refresh circuits
• Slower
• Main memory
Dynamic RAM Structure
DRAM Operation
• Address line active when bit read or written
— Transistor switch closed (current flows)
• Write
— Voltage to bit line
– High for 1 low for 0
— Then signal address line
– Transfers charge to capacitor
• Read
— Address line selected
– transistor turns on
— Charge from capacitor fed via bit line to sense amplifier
— Capacitor charge must be restored
Static RAM
• Bits stored as on/off switches
• No charges to leak
• No refreshing needed when powered
• More complex construction
• Larger per bit
• More expensive
• Does not need refresh circuits
• Faster
• Cache
• Digital
—Uses flip-flops
Stating RAM Structure
Static RAM Operation
• Transistor arrangement gives stable logic
state
• State 1
—C1 high, C2 low
—T1 T4 off, T2 T3 on
• State 0
—C2 high, C1 low
—T2 T3 off, T1 T4 on
• Address line transistors T5 T6 is switch
• Write – apply value to B & compliment to
B
• Read – value is on line B
SRAM v DRAM
• Both volatile
—Power needed to preserve data
• Dynamic cell
—Simpler to build, smaller
—More dense
—Less expensive
—Needs refresh
—Larger memory units
• Static
—Faster
—Cache
Read Only Memory (ROM)
• Permanent storage
—Nonvolatile
• Microprogramming (see later)
• Systems programs (BIOS)
• Function tables
Types of ROM
• Written during manufacture
—Very expensive for small runs
• Programmable (once)
—PROM
—Needs special equipment to program
• Read “mostly”
—Erasable Programmable (EPROM)
– Erased by UV
—Electrically Erasable (EEPROM)
– Takes much longer to write than read
—Flash memory
– Erase whole memory electrically
Organisation in detail
• A 16Mbit chip can be organised as 1M of
16 bit words
• A bit per chip system has 16 lots of 1Mbit
chip with bit 1 of each word in chip 1 and
so on
• A 16Mbit chip can be organised as a 2048
x 2048 x 4bit array
—Reduces number of address pins
– Multiplex row address and column address
– 11 pins to address (211=2048)
– Adding one more pin doubles range of values so x4
capacity
Refreshing
• Refresh circuit included on chip
• Disable chip
• Count through rows
• Read & Write back
• Takes time
• Slows down apparent performance
Typical 16 Mb DRAM (4M x 4)
Packaging
Systems Design & Programming Memory CMPE 310

Memory Types
Two basic types:
Q ROM: Read-only memory
Q RAM: Read-Write memory

Four commonly used memories:

P ROM
P Flash, EEPROM
P Static RAM (SRAM)
P Dynamic RAM (DRAM), SDRAM, RAMBUS, DDR RAM

Generic pin configuration:

Address connection
Write
A0 A1 ... AN WE
Read
OE
Select
O0 O1 ... ON CS
Output/Input-output connection

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Systems Design & Programming Memory CMPE 310

Memory Chips

The number of address pins is related to the number of memory locations.

Common sizes today are 1K to 256M locations.
Therefore, between 10 and 28 address pins are present.

The data pins are typically bi-directional in read-write memories.

The number of data pins is related to the size of the memory location.
For example, an 8-bit wide (byte-wide) memory device has 8 data pins.
Catalog listing of 1K X 8 indicate a byte addressable 8K bit memory with 10 address
pins.

Each memory device has at least one chip select (CS) or chip enable (CE) or select (S) pin
that enables the memory device.
This enables read and/or write operations.
If more than one are present, then all must be 0 in order to perform a read or write.

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Systems Design & Programming Memory CMPE 310

Memory Chips

Each memory device has at least one control pin.

For ROMs, an output enable (OE) or gate (G) is present.
The OE pin enables and disables a set of tristate buffers.
For RAMs, a read-write (R/W) or write enable (WE) and read enable (OE) are
present.
For dual control pin devices, it must be hold true that both are not 0 at the same
time.

ROM:
Non-volatile memory: Maintains its state when powered down.
There are several forms:
Q ROM: Factory programmed, cannot be changed. Older style.
Q PROM: Programmable Read-Only Memory.
Field programmable but only once. Older style.
Q EPROM: Erasable Programmable Read-Only Memory.
Reprogramming requires up to 20 minutes of high-intensity UV light exposure.

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Systems Design & Programming Memory CMPE 310

Memory Chips

ROMs (cont):

Q Flash, EEPROM: Electrically Erasable Programmable ROM.

Also called EAROM (Electrically Alterable ROM) and NOVRAM (NOn-Volatile
RAM).
Writing is much slower than a normal RAM.

Used to store setup information, e.g. video card, on computer systems.

Can be used to replace EPROM for BIOS memory.

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Systems Design & Programming Memory CMPE 310

EPROMs
Intel 2716 EPROM (2K X 8):
A7 1 24 VCC VPP is used to program the device
A6 2 23 A8
A5 3 22 A9 by applying 25V and pulsing PGM
A4 4 21 VPP while holding CS high.
A3 5 20
A2 19 CS Data Outputs
6 A10
2716
A1 7 18 PD/PGM
A0 8 17 O7
O0 9 16 O6 Chip Select
O1 10 15 O5 CS Output
PWR Down
O2 11 14 O4 PD/PGM Buffers
Prog Logic
GND 12 13 O3

2K x 8 EPROM Y
Decoder Y-Gating
Address Inputs

Pin(s) Function
A0-A10 Address
PD/PGM Power down/Program X 16,384
Decoder Cell Matrix
CS Chip Select
O0-O7 Outputs

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Systems Design & Programming Memory CMPE 310

EPROMs
2716 Timing diagram:

Address
tOH

CS tDF
High Z
Data Out Valid
tACC1
Read Mode (PD/PGM =VIL)
Sample of the data sheet for the 2716 A.C. Characteristics.
Limits
Symbol Parameter Unit Test Condition
Min Typ. Max
tACC1 Addr. to Output Delay 250 450 ns PD/PGM= CS =VIL
tOH Addr. to Output Hold 0 ns PD/PGM= CS =VIL
tDF Chip Deselect to Output Float 0 100 ns PD/PGM=VIL
... ... ... ... ... ... ...
This EPROM requires a wait state for use with the 8086 (460ns constraint).

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Systems Design & Programming Memory CMPE 310

SRAMs
TI TMS 4016 SRAM (2K X 8):
A7 1 24 VCC
A6 2 23 A8
A5 3 22 A9
A4 4 21 W Pin(s) Function
A3 TMS4016 20
5 G A0-A10
A2 6 19 A10 Address
A1 7 18 S DQ0-DQ7 Data In/Data Out
A0 8 17 DQ7
DQ0 16 S (CS) Chip Select
9 DQ6
DQ1 10 15 DQ5 G (OE) Read Enable
DQ2 11 14 DQ4
GND 13 W (WE) Write Enable
12 DQ3

2K x 8 SRAM
Virtually identical to the EPROM with respect to the pinout.

However, access time is faster (250ns).

See the timing diagrams and data sheets in text.

SRAMs used for caches have access times as low as 10ns.

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Systems Design & Programming Memory CMPE 310

DRAMs

DRAM:
SRAMs are limited in size (up to about 128K X 8).
DRAMs are available in much larger sizes, e.g., 64M X 1.

DRAMs MUST be refreshed (rewritten) every 2 to 4 ms

Since they store their value on an integrated capacitor that loses charge over time.

This refresh is performed by a special circuit in the DRAM which refreshes the entire
memory.
Refresh also occurs on a normal read or write.
More on this later.

The large storage capacity of DRAMs make it impractical to add the required number
of address pins.
Instead, the address pins are multiplexed.

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Systems Design & Programming Memory CMPE 310

DRAMs
TI TMS4464 DRAM (64K X 4):

G 1 18 VSS Pin(s) Function

DQ0 2 17 DQ3
DQ1 A0-A7 Address
3 TMS4464 16 CAS
W 4 15 DQ2 DQ0-DQ3 Data In/Data Out
RAS 5 14 A0
A6 6 13 A1 RAS Row Address Strobe
A5 7 12 A2 Column Address Strobe
A4 CAS
8 11 A3
VDD 9 10 A7 G Output Enable
W Write Enable
64K x 4 DRAM
The TMS4464 can store a total of 256K bits of data.

It has 64K addressable locations which means it needs 16 address inputs, but it has
only 8.
The row address (A0 through A7) are placed on the address pins and strobed into a
set of internal latches.
The column address (A8 through A15) is then strobed in using CAS.

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Systems Design & Programming Memory CMPE 310

DRAMs
TI TMS4464 DRAM (64K X 4) Timing Diagram:

RAS

CAS

Row Column Dont care

CAS also performs the function of the chip select input.

A0 A8 A1 A9 A2 A10 A3 A11 Address BUS A4 A12A5 A13A6 A14 A7 A15

1A 1B 2A 2B 3A 3B 4A 4B RAS 1A 1B 2A 2B 3A 3B 4A 4B

74157 (2-to-1MUX) S S 74157 (2-to-1MUX)

0: latch A to Y
1Y 2Y 3Y 4Y 1: latch B to Y 1Y 2Y 3Y 4Y

A0 A1 A2 A3 Inputs to DRAM A4 A5 A6 A7

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Systems Design & Programming Memory CMPE 310

DRAMs

Larger DRAMs are available which are organized as 1M X 1, 4M X 1, 16M X 1, 64M X 1,

256M X 1.
DRAMs are typically placed on SIMM (Single In-line Memory Modules) boards.
30-pin SIMMs come in 1M X 8, 1M X 9 (parity), 4M X 8, 4M X 9.
72-pin SIMMs come in 1/2/3/8/16M X 32 or 1M X 36 (parity).
VSS Addr0-11 RAS W NC
VCC DQ0-31 CAS PD1-4

+ 5 10 15 20 25 30 35 40 45 50 55 60 65 70
+

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Systems Design & Programming Memory CMPE 310

DRAMs

Pentiums have a 64-bit wide data bus.

The 30-pin and 72-pin SIMMs are not used on these systems.
Rather, 64-bit DIMMs (Dual In-line Memory Modules) are the standard.
These organize the memory 64-bits wide.
The board has DRAMs mounted on both sides and is 168 pins.

Sizes include 2M X 64 (16M), 4M X 64 (32M), 8M X 64 (64M) and 16M X 64 (128M).

The DIMM module is available in DRAM, EDO and SDRAM (and NVRAM) with
and without an EPROM.

The EPROM provides information about the size and speed of the memory device
for PNP applications.

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Systems Design & Programming Memory CMPE 310

Memory Address Decoding

The processor can usually address a memory space that is much larger than the memory
space covered by an individual memory chip.

In order to splice a memory device into the address space of the processor, decoding is nec-
essary.

For example, the 8088 issues 20-bit addresses for a total of 1MB of memory address space.

However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins.

A decoder can be used to decode the additional 9 address pins and allow the EPROM to be
placed in any 2KB section of the 1MB address space.

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Systems Design & Programming Memory CMPE 310

Memory Address Decoding

A0 O0
Address Bus A1 O1 Data Bus

...

...
A19
A10 O7
A18
A17 2716
(2K X 8)
A16
EPROM
A15
CS
A14
A13
A12
A11
RD of 8088/86 Or MRDC bus signal.
IO/M
Logic 0 when A11 through A19 are all 1.

(Book shows OE connection for RD but chip definition does NOT have this pin)

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Systems Design & Programming Memory CMPE 310

Memory Address Decoding

To determine the address range that a device is mapped into:

A19 - A11 A10 - A0

1111 1111 1XXX XXXX XXXX

1111 1111 1000 0000 0000 (FF800H)

To
1111 1111 1111 1111 1111 (FFFFFH)

This 2KB memory segment maps into the reset location of the 8086/8088 (FFFF0H).

NAND gate decoders are not often used

Large fan-in NAND gates are not efficient
Multiple NAND gate IC's might be required to perform such decoding
Rather the 3-to-8 Line Decoder (74LS138) is more common.

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Systems Design & Programming Memory CMPE 310

Memory Address Decoding

The 3-to-8 Line Decoder (74LS138)

Inputs
Output
Enable Select
C B A 0 1 2 3 4 5 6 7
Select Inputs

A 0 G2A G2B G1

1 1 X X X X X 1 1 1 1 1 1 1 1
B
X 1 X X X X 1 1 1 1 1 1 1 1
C 2
X X 0 X X X 1 1 1 1 1 1 1 1

Outputs
3 0 0 1 0 0 0 0 1 1 1 1 1 1 1
4 0 0 1 0 0 1 1 0 1 1 1 1 1 1
G2A 5 0 0 1 0 1 0 1 1 0 1 1 1 1 1
Enable

G2B 6 0 0 1 0 1 1 1 1 1 0 1 1 1 1
0 0 1 1 0 0 1 1 1 1 0 1 1 1
G1 7 0 0 1 1 0 1 1 1 1 1 1 0 1 1
0 0 1 1 1 0 1 1 1 1 1 1 0 1
0 0 1 1 1 1 1 1 1 1 1 1 1 0

Note that all three Enables (G2A, G2B, and G1) must be active, e.g. low, low and high,
respectively.
Each output of the decoder can be attached to an 2764 EPROM (8K X 8).

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Systems Design & Programming Memory CMPE 310

Memory Address Decoding

A0
A13 through A15 select a 2764 Address Bus

...
A12
A16 through A19 enable the decoder O0
Data Bus

...
O7
A13 F0000-F1FFF
A 0
A14 F2000-F3FFF 2764
B 1 (8K X 8)
74LS138

A15 F4000-F5FFF
C 2 EPROM
F6000-F7FFF
3
F8000-F9FFF CS
4 CS
G2A FA000-FBFFF
5 CS
G2B 6 FC000-FDFFF CS
A16 FE000-FFFFF
CS
G1 7 CS
CS
CS
A17 Address space
A18 F0000H-FFFFFH
A19 RD of 8088/86
The EPROMs cover a 64KB section of memory.

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Systems Design & Programming Memory CMPE 310

Memory Address Decoding

Yet a third possibility is a PLD (Programmable Logic Device).

PLDs come in three varieties:
Q PLA (Programmable Logic Array)
Q PAL (Programmable Array Logic)
Q GAL (Gated Array Logic)

PLDs have been around since the mid-1970s but have only recently appeared in memory
systems (PALs have replaced PROM address decoders).

PALs and PLAs are fuse-programmed (like the PROM).

Some are erasable (like the EPROM).

A PAL example (16L8) is shown in the text and is commonly used to decode the memory
address, particularly for 32-bit addresses generated by the 80386DX and above.

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Systems Design & Programming Memory CMPE 310

Memory Address Decoding

AMD 16L8 PAL decoder.
It has 10 fixed inputs (Pins 1-9, 11), two fixed outputs (Pins 12 and 19) and 6 pins that
can be either (Pins 13-18).
Programmed to decode address lines A19 - A13 onto 8 outputs.
;pins 1 2 3 4 5 6 7 8 9 10
A19 A18 A17 A16 A15 A14 A13 NC NC GND
I1 1 20 VCC ;pins 11 12 13 14 15 16 17 18 19 20
I2 2 19 O8 NC O8 O7 O6 O5 O4 O3 O2 O1 VCC
I3 3 18 O7
I4 4 17 O6 Equations:
16L8

I5 5 16 O5 /O1 = A19 * A18 * A17 * A16 * /A15 * /A14 * /A13

I6 6 15 O4 /O2 = A19 * A18 * A17 * A16 * /A15 * /A14 * A13
I7 7 14 O3 /O3 = A19 * A18 * A17 * A16 * /A15 * A14 * /A13
I8 8 13 O2 /O4 = A19 * A18 * A17 * A16 * /A15 * A14 * A13
I9 9 12 O1
GND 10 I10 /O5 = A19 * A18 * A17 * A16 * A15 * /A14 * /A13
11
/O6 = A19 * A18 * A17 * A16 * A15 * /A14 * A13
/O7 = A19 * A18 * A17 * A16 * A15 * A14 * /A13
/O8 = A19 * A18 * A17 * A16 * A15 * A14 * A13
AND/NOR device with logic expressions (outputs) with up to 16 ANDed inputs and 7
ORed product terms.

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Systems Design & Programming Memory CMPE 310

8088 and 80188 (8-bit) Memory Interface

The memory systems sees the 8088 as a device with:

Q 20 address connections (A19 to A0).
Q 8 data bus connections (AD7 to AD0).
Q 3 control signals, IO/M, RD, and WR.

We'll look at interfacing the 8088 with:

Q 32K of EPROM (at addresses F8000H through FFFFFH).
Q 512K of SRAM (at addresses 00000H through 7FFFFH).

The EPROM interface uses a 74LS138 (3-to-8 line decoder) plus 8 2732 (4K X 8)
EPROMs.

The EPROM will also require the generation of a wait state.

The EPROM has an access time of 450ns.
The 74LS138 requires 12ns to decode.
The 8088 runs at 5MHz and only allows 460ns for memory to access data.
A wait state adds 200ns of additional time.

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Systems Design & Programming Memory CMPE 310

8088 and 80188 (8-bit) EPROM Memory Interface

A0
To wait state generator Address Bus

...
A11
WAIT O0
Data Bus

...
74LS138 O7
A12
A 0 2732
A13
B 1 (4K X 8)
A14
C 2 RD
IO/M 3 OE
CS
A15 4 CS
A16 G2A 5 CS
G2B 6 CS
A17 CS
A18 G1 7 CS
CS
A19 1K CS
Address space
5V F8000H-FFFFFH

The 8088 cold starts execution at FFFF0H. JMP to F8000H occurs here.

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Systems Design & Programming Memory CMPE 310

8088 and 80188 (8-bit) RAM Memory Interface

A0 A 0 O0
A1 Address Bus

...

...
A8 A14 O7
A2 A9
74LS244

A3 WE
Buffer
A10 OE
A4

74LS244
A11 A CS

74LS138
Buffer
A5 0
A12 B

(32K X 8)
A6 1 CS

62256
A 13 C 2 CS
A7 A14 3
1G 2G 4 CS
1G 2G G1 5 CS
G2A 6 CS
WR G2B 7
2 CS
RD CS
A15 A0 O0
74LS244

...

...
A16 3 A14 O7 Data Bus
Buffer

A17 WE
OE
A

(32K X 8)
CS
74LS138

0 G

62256
A B
74LS138

BD Buffer
CS

74LS245
1G 2G B 0
1 C 2
C 3 CS
A18 2 CS
3 4
G1 4 4 G1 5 CS
A19 G2A 6 Dir
G2A 5 CS
IO/M G2B 67 G2B 7 CS
CS

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Systems Design & Programming Memory CMPE 310

8086 - 80386SX 16-bit Memory Interface

These machines differ from the 8088/80188 in several ways:
P The data bus is 16-bits wide.
P The IO/M pin is replaced with M/IO (8086/80186) and MRDC and MWTC for 80286
and 80386SX.
P BHE, Bus High Enable, control signal is added.
P Address pin A0 (or BLE, Bus Low Enable) is used differently.

The 16-bit data bus presents a new problem:

The microprocessor must be able to read and write data to any 16-bit location in addi-
tion to any 8-bit location.
The data bus and memory are divided into banks:
High bank Low bank
FFFFFF FFFFFE
FFFFFD FFFFFC
8 bits 8 bits
Odd bytes D15-D8 D7-D0
Even bytes
8 MB BHE selects 8 MB BLE selects
000003 000002
000001 000000

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Systems Design & Programming Memory CMPE 310

8086 - 80386SX 16-bit Memory Interface

BHE and BLE are used to select one or both:

BHE BLE Function

0 0 Both banks enabled for 16-bit transfer
0 1 High bank enabled for an 8-bit transfer
1 0 Low bank enabled for an 8-bit transfer
1 1 No banks selected

Bank selection can be accomplished in two ways:

P Separate write decoders for each bank (which drive CS).
P A separate write signal (strobe) to each bank (which drive WE).
Note that 8-bit read requests in this scheme are handled by the microprocessor (it
selects the bits it wants to read from the 16-bits on the bus).

There does not seem to be a big difference between these methods although the book claims
that there is.
Note in either method that A0 does not connect to memory and bus wire A1 connects to
memory pin A0, A2 to A1, etc.

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Systems Design & Programming Memory CMPE 310

80386SX 16-bit Memory Interface (Separate Decoders)

A0 O0
A1 to A16 Address Bus D8 to D15

...

...
MWTC A15 O7
A17 WE
OE
A18 A CS

74LS138
3 0
A19
B 1 CS 62512
C 2 CS(64K X 8)
3
BHE 4 CS
G1 5

Separate Decoders
CS
A20 G2A 6 CS
A21 A 7

80386SX
0
74LS138

G2B CS
A22 B 1
C 2 A 0 O0 CS
3 D0 to D7

...

...
4 A15 O7
A23 G1 5
G2A 6 WE
G2B 7 OE

Data Bus
A CS
74LS138

0
B 1 CS 62512
MRDC C 2
3 CS (64K X 8)
M/IO CS
G1 45 CS
BLE
G2A 6 CS
G2B 7 CS
CS

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Systems Design & Programming Memory CMPE 310

Memory Interfaces

See text for Separate Write Strobe scheme plus some examples of the integration of
EPROM and SRAM in a complete system.
It is just an application of what we've been covering.

80386DX and 80486 have 32-bit data buses and therefore 4 banks of memory.
32-bit, 16-bit and 8-bit transfers are accomplished by different combinations of the
bank selection signals BE3, BE2, BE1, BE0.

The Address bits A0 and A1 are used within the microprocessor to generate these sig-
nals.
They are don't cares in the decoding of the 32-bit address outside the chip (using a
PLD such as the PAL 16L8).

The high clock rates of these processors usually require wait states for memory access.
We will come back to this later.

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Systems Design & Programming Memory CMPE 310

Pentium Memory Interface

The Pentium, Pentium Pro, Pentium II and III contain a 64-bit data bus.
Therefore, 8 decoders or 8 write strobes are needed as well as 8 memory banks.
The write strobes are obtained by combining the bank enable signals (BEx) with the
MWTC signal.
MWTC is generated by combining the M/IO and W/R signals.
BE7
WR7
BE6
WR6
BE5
WR5
W/R BE4
MWTC WR4
M/IO BE3
WR3
BE2
WR2
BE1
WR1
BE0
WR0

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Systems Design & Programming Memory CMPE 310

Pentium Memory Interface

A3-A18

WR2
WR1
WR0

WR3
D15-D23

D24-D31
D8-D15
D0-D7
A29 I1
A30 I2 O1 A 0 O0 A 0 O0 A 0 O0 A 0 O0
A31 I3 O2

...

...

...
...

...

...
...
...
A15 O7 A15 O7 A15 O7 A15 O7
I4 O3
16L8

I5 O4

(64K X 8)

27512

27512

27512
WE WE WE WE

27512
I6 O5
I7 O6 CE CE CE
I8 O7 CE
I9 O8 OE OE OE OE
I10

A19 I1
A20 O1
A21 I2 O2 A 0 O0 A 0 O0 A 0 O0 A 0 O0
A22 I3
...

...

...

...
...

...

...

...
I4 O3 A15 O7 A15 O7 A15 O7 A15 O7

D56-D63
D32-D39

D40-D47

D48-D55
A23 I5
16L8

A24 O4
A25 I6 O5
27512

27512

27512

27512
WE WE WE WE
A26 I7 O6
A27 I8 O7 CE CE CE CE
A28 I9
I10 O8 OE OE OE OE

WR7
MRDC
WR4

WR6
WR5

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Systems Design & Programming Memory CMPE 310

Pentium Memory Interface

In order to map previous memory into addr. space FFF80000H-FFFFFFFFH

A29 I1
A30 I2 O1 ;pins 1 2 3 4 5 6 7 8 9 10
A31 I3 O2 A29 A30 A31 NC NC NC NC NC NC GND
I4 O3 ;pins 11 12 13 14 15 16 17 18 19 20
16L8

I5 O4
I6 O5 U2 CE NC NC NC NC NC NC NC VCC
I7 O6
I8 O7 Equations:
I9 O8 /CE = /U2 * A29 * A30 * A31
I10

A19 I1
A20 O1 ;pins 1 2 3 4 5 6 7 8 9 10
A21 I2 O2
A22 I3
I4 O3
A19 A20 A21 A22 A23 A24 A25 A26 A27 GND
A23 I5 ;pins 11 12 13 14 15 16 17 18 19 20
16L8

A24 O4
A25 I6 O5 A28 U2 NC NC NC NC NC NC NC VCC
A26 I7 O6
A27 I8 O7 Equations:
A28 I9
I10 O8 /U2 = A19 * A20 * A21 * A22 * A23 * A24 * A25 *
A26 * A27 * A28
Use a 16L8 to do the WR0 - WR7 decoding using MWTC and BE0 - BE7.
See the text -- Figure 10-35.
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Systems Design & Programming Memory CMPE 310

Memory Architecture

In order to build an N-word memory where each word is M bits wide (typically 1, 4 or 8
bits), a straightforward approach is to stack memory:

A word is selected by setting exactly

S0
Word 0 one of the select bits, Sx, high.
S1
Word 1
S2 Storage cell
Word 2
N words

This approach works well for small

memories but has problems for large
memories.
SN-2
Word N-2
SN-1 For example, to build a 1Mword
Word N-1
(where word = 8 bits) memory, requires
1M select lines, provided by some
Input-Output off-chip device.
(M bits)

This approach is not practical. What can we do?

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Systems Design & Programming Memory CMPE 310

Memory Architecture
Add a decoder to solve the package problem:
S0
Word 0
S1
Binary encoded address

A0 Word 1
S2 Storage cell
A1 Word 2

Decoder
A2
This reduces the
AK-1 number of external
SN-2 address pins from
Word N-2 1M to 20.
SN-1
Word N-1
K = log2N

one-hot Input-Output
(M bits)
This does not address the memory aspect ratio problem:
The memory is 128,000 time higher than wide (220/23)!
Besides the bizarre shape factor, the design is extremely slow since the vertical wires
are VERY long (delay is at least linear to length).

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Systems Design & Programming Memory CMPE 310

Memory Architecture

The vertical and horizontal dimensions are usually very similar, for an aspect ratio of unity.
Multiple words are stored in each row and selected simultaneously:
Row address = S0 Bit line
AK to AL-1 S1 Storage cell
AK S2
AK+1 Row Decoder
AK+2 Word line

AL-1
SN-2
SN-1

Column address =
A0 to AK-1 A0
Column decoder Sense amps
AK-1 and drivers
not shown
A column decoder is added to
select the desired word from a row. Input-Output
(M bits)

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Systems Design & Programming Memory CMPE 310

Memory Architecture
This strategy works well for memories up to 64 Kbits to 256 Kbits.
Larger memories start to suffer excess delay along bit and word lines.
A third dimension is added to the address space to solve this problem:
Block 0 Block i Block P-1

Row
Address

Column
Address
Block
Block selector
Address

Global Data bus

Global
Address: [Row][Block][Col] amplifier/driver
I/O

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Systems Design & Programming Memory CMPE 310

Dynamic RAM

DRAM requires refreshing every 2 to 4 ms. (some even at 16ms)

This is due to the storage mechanism. Data is stored as charge on a capacitor
This capacitor is not perfect, i.e., it discharges over the course of time via the access
transistor.
Refreshing occurs automatically during a read or write.
Internal circuitry takes care of refreshing cells that are not accessed over this interval.

Three different refresh methods are used:

Q RAS-only refresh
Q CAS before RAS refresh
Q Hidden refresh

Refresh time example:

For a 256K X 1 DRAM with 256 rows, a refresh must occur every 15.6us (4ms/256).
For the 8086, a read or write occurs every 800ns.
This allows 19 memory reads/writes per refresh or 5% of the time.

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Systems Design & Programming Memory CMPE 310

DRAM Refreshing

RAS-only refresh
Refresh cycle Refresh cycle

RAS

CAS Refresh

Address XXXXXXXXXX XXXXXXXXXX

Simplest and most widely used method for refreshing, carry out a dummy read cycle

RAS is activated and a row address (refresh address) is applied to the DRAM, CAS inactive

DRAM internally reads one row and amplifies the read data. Not transferred to the output
pins as CAS is disabled.

The main disadvantage of this refresh method is that an external logic device, or some pro-
gram, is required to generate the DRAM row addresses in succession.
DMA chip 8237 (will be discussed later) can be used to generate these addresses
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Systems Design & Programming Memory CMPE 310

Dynamic RAM

A10-A17 256K X 1 DRAM

A0
A1 Block 3 Block 2 Block 1 Block 0
A2
A3 255
Row Latches 254

Decoder
A4 64K array 64K array 64K array 64K array
A5 (256 X 256) (256 X 256) (256 X 256) (256 X 256)
A6 1
A7 0
A8
RAS 8 256-to-1 256-to-1 256-to-1 256-to-1
MUX MUX MUX MUX
WE

A0-A7
Column Latches

DIN
DOUT

MUX
A9(A0 from input pin on RAS) Dir
A8 S1
S0
CAS
These signals provide the block address.

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Systems Design & Programming Memory CMPE 310

DRAM Controllers

A DRAM controller is usually responsible for address multiplexing and generation of the
DRAM control signals.

These devices tend to get very complex. We will focus on a simpler device, the Intel
82C08, which can control two banks of 256K X 16 DRAM memories for a total of 1 MB.

Microprocessor bits A1 through A18 (18 bits) drive the 9 Address Low (AL) and 9 Address
High (AH) bits of the 82C08. 9 of each of these are strobed onto the address wires A0
through A8 to the memories.

Either RAS0/CAS0 or RAS1/CAS1 are strobed depending on the address.

This drives a 16-bit word onto the High and Low data buses (if WE is low) or writes
an 8 or 16 bit word into the memory otherwise.

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Systems Design & Programming Memory CMPE 310

DRAM Controllers
A1 AL0 A0 R1 (256K X 8)
...

...
AL8 A8 A 0 O0 A 0 O0
AH0 82C08

...

...
...

...
A18 A 8 O7 A 8 O7
...

AH8

41256A8

41256A8
S0 RD RAS0 R2 WE WE
S1 WR CAS0
RESET RAS1 RAS RAS
CLK CAS CAS
PCTL CAS1
PE AA/XA
BS
A19 RFRQ WE
PD1

I1 A 0 O0 A 0 O0

High Data Bus

Low Data Bus

BHE O1

...

...
...

...
I2 A 8 O7 A 8 O7
A0 I3 O2
A20 I4 O3
A21
16L8

41256A8

41256A8
I5 O4
A22 I6 O5 WE WE
A23 I7 O6 RAS RAS
I8 O7 CAS CAS
M/IO I9 O8
I10 WAIT

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Systems Design & Programming Memory CMPE 310

DRAM Controllers

WE (from the 82C08), BHE and A0 are used to determine if a write is to be performed and
which byte(s) (low or high or both) is to be written.

Address bit A20 through A23 along with M/IO enable these memories to map onto 1 MByte
range (000000H-0FFFFFH).

16L8 Programming:

WE I1 ;pins 1 2 3 4 5 6 7 8 9 10
A0 I2 O1 PE WE BHE A0 A20 A21 A22 A23 NC NC GND
A20 I3 O2 HWR ;pins 11 12 13 14 15 16 17 18 19 20
A21 I4 O3 LWR
A22 MIO CE NC NC NC NC LWR HWR PE VCC
16L8

I5 O4
A23 I6 O5
I7 O6 Equations:
I8 O7 /LWR = /A0 * /WE
I9 O8
M/IO I10 /HWR = /BHE * /WE
/PE = /A20 * /A21 * /A22 * /A23 * MIO

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Systems Design & Programming Memory CMPE 310

SDRAM and DDR SDRAM

SDRAM: Synchronous DRAM, DDR SDRAM: Double Data Rate SDRAM

(Don't confuse this with SRAM. This is still a dynamic RAM)

SDRAM have typical access time of 8 to 15 ns (even lower now) as compared to the
previously discussed EDO RAM which has access time of 50 to 60ns

The difference is noticeable with higher front side bus speeds found in today's boards

For SDRAMs, 168-pin DIMM sockets are used as memory modules with 64 bit data

SDRAMs work in burst mode and with a synchronous clock rate

They do not use the corresponding RAS, CAS, WE and CE signals
Rather commands such as write, read or burst stop are transferred

Some have a EEPROM, which contain data about the module type, organization of the
DRAMs used and timing behavior.
Chipset's system management can read this info and configure the best settings

10