嵌入式系統

Introduction to Embedded System Design

Part 2: 循序邏輯簡介
Introduction to Synchronous Sequential Logic

授課教師
Che-Wei LIN (林哲偉)

Introduction to Embedded System-1

 Reference

 M. M. Mano, M. D. Ciletti, Digital Design (Fourth Edition),

Prentice-Hall 2007.
 Introduction to Logic Design:
http://opencourses.emu.edu.tr/course/view.php?id=2

Introduction to Embedded System-2

 Sequential Circuits

 Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements

 Synchronous
Inputs Outputs
Combinational
Circuit
Flip-flops
Clock

Introduction to Embedded System-3

 Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0

R 0 0
Q

S Q
0 1

Initial Value

Introduction to Embedded System-4

 Latches
 SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

R 0 1
Q

S Q
0 0

Introduction to Embedded System-5

 Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0

R 1 0
Q

S Q
0 1

Introduction to Embedded System-6

 Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0

R 1 1
Q
0 1 1 0 1 Q=0

S Q
0 0

Introduction to Embedded System-7

 Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 0 0
Q
0 1 1 0 1
1 0 0 1 0 Q=1

S Q
1 1

Introduction to Embedded System-8

 Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 0 1
Q
0 1 1 0 1
1 0 0 1 0 Q=1

1 0 1 1 0 Q=1

S Q
1 0

Introduction to Embedded System-9

 Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1
R 1
Q=0
0 0 1 1 0 1
Q 1 0 0 1 0 Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 10

Introduction to Embedded System-10

 Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 1 10
Q
0 1 1 0 1
1 0 0 1 0 Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’

S Q
1 0

Introduction to Embedded System-11

 Latches
 SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S R Q
Q
0 0 Q=Q’=1 Invalid
0 1 1 Set
1 0 0 Reset
R Q
1 1 Q0 No change
Introduction to Embedded System-12
 Latches
 SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S’ R’ Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set
Q 1 0 0 Reset
R Q0 No change
1 1
Introduction to Embedded System-13
 Controlled Latches
 SR Latch with Control Input

R R S S
Q Q
C C
S Q R Q
S R

C S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q’ Invalid
Introduction to Embedded System-14
 Controlled Latches
 D Latch (D = Data) Timing Diagram

D S C
Q
C D
R Q
Q

t
C D Q
Output may
0 x Q0 No change
change
1 0 0 Reset
1 1 1 Set

Introduction to Embedded System-15

 Controlled Latches
 D Latch (D = Data) Timing Diagram

D S C
Q
C D
R Q
Q

C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set

Introduction to Embedded System-16

 Flip-Flops

 Controlled latches are level-triggered

 Flip-Flops are edge-triggered

CLK Positive Edge

CLK Negative Edge

Introduction to Embedded System-17

 Flip-Flops
 Master-Slave D Flip-Flop

D D Q D Q Q
D Latch D Latch
(Master) (Slave)
C C
Master Slave

CLK
CLK

D
Looks like it is negative
edge-triggered QMaster

QSlave
Introduction to Embedded System-18
 Flip-Flops
 Edge-Triggered D Flip-Flop
D Q

Q Positive Edge
CLK

Q D Q

D Negative Edge

Introduction to Embedded System-19

 Flip-Flops
 JK Flip-Flop

J
D Q Q
K
CLK Q Q

J Q
D = JQ’ + K’Q
K Q
Introduction to Embedded System-20
 Flip-Flops
 T Flip-Flop

T J Q T D Q

Q
K Q

T Q
D = JQ’ + K’Q
D = TQ’ + T’Q = T  Q Q

Introduction to Embedded System-21

Flip-Flop Characteristic Tables

D Q D Q(t+1)
0 0 Reset
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle

T Q T Q(t+1)
0 Q(t) No change
Q 1 Q’(t) Toggle
Introduction to Embedded System-22
Flip-Flop Characteristic Equations

D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t) Q(t+1) = T  Q
Q 1 Q’(t)
Introduction to Embedded System-23
 Flip-Flop Characteristic Equations
 Analysis / Derivation

J K Q(t) Q(t+1)
0 0 0 0 No change
0 0 1 1
J Q
0 1 0 Reset
0 1 1
K Q 1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1

Introduction to Embedded System-24

 Flip-Flop Characteristic Equations
 Analysis / Derivation

J K Q(t) Q(t+1)
0 0 0 0 No change
0 0 1 1
J Q
0 1 0 0 Reset
0 1 1 0
K Q 1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1

Introduction to Embedded System-25

 Flip-Flop Characteristic Equations
 Analysis / Derivation

J K Q(t) Q(t+1)
0 0 0 0 No change
0 0 1 1
J Q
0 1 0 0 Reset
0 1 1 0
K Q 1 0 0 1 Set
1 0 1 1
1 1 0 Toggle
1 1 1

Introduction to Embedded System-26

 Flip-Flop Characteristic Equations
 Analysis / Derivation

J K Q(t) Q(t+1)
0 0 0 0 No change
0 0 1 1
J Q
0 1 0 0 Reset
0 1 1 0
K Q 1 0 0 1 Set
1 0 1 1
1 1 0 1 Toggle
1 1 1 0

Introduction to Embedded System-27

 Flip-Flop Characteristic Equations
 Analysis / Derivation

J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1 K
J Q
0 1 0 0 0 1 0 0
0 1 1 0 J 1 1 0 1
K Q 1 0 0 1 Q
1 0 1 1
1 1 0 1
1 1 1 0

Q(t+1) = JQ’ + K’Q

Introduction to Embedded System-28

 Flip-Flops with Direct Inputs
 Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 x x 0
Q
R
Reset

Introduction to Embedded System-29

 Flip-Flops with Direct Inputs
 Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 x x 0
Q 1 0 ↑ 0
R 1 1 ↑ 1
Reset

Introduction to Embedded System-30

 Flip-Flops with Direct Inputs
 Asynchronous Preset and Clear

Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0

Q
CLR
Reset

Introduction to Embedded System-31

 Flip-Flops with Direct Inputs
 Asynchronous Preset and Clear

Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0
0 1 x x 1
Q
CLR
Reset

Introduction to Embedded System-32

 Flip-Flops with Direct Inputs
 Asynchronous Preset and Clear

Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0
0 1 x x 1
Q 1 1 0 ↑ 0
CLR 1 1 1 ↑ 1
Reset

Introduction to Embedded System-33

Analysis of Clocked Sequential Circuits
 The State
 State = Values of all Flip-Flops

Example
x
AB=00 D Q A

D Q B

CLK Q

Introduction to Embedded System-34

 Analysis of Clocked Sequential Circuits
 State Equations
x
D Q A
A(t+1) = DA
= A(t) x(t)+B(t) x(t) Q
=Ax+Bx
B(t+1) = DB D Q B
= A’(t) x(t)
= A’ x CLK Q

y(t) = [A(t)+ B(t)] x’(t) y

= (A + B) x’

Introduction to Embedded System-35

Analysis of Clocked Sequential Circuits
 State Table (Transition Table)
x
Present Next D Q A
Input Output
State State
Q
A B x A B y
0 0 0 0 0 0 B
D Q
0 0 1 0 1 0
CLK Q
0 1 0 0 0 1
0 1 1 1 1 0 y

1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
A(t+1) = A x + B x
1 1 1 1 0 0 B(t+1) = A’ x
y(t) = (A + B) x’
t t+1 t
Introduction to Embedded System-36
Analysis of Clocked Sequential Circuits
 State Table (Transition Table)
x
Present Next State Output D Q A

State x=0 x=1 x=0 x=1 Q

A B A B A B y y
0 0 0 0 0 1 0 0 D Q B
0 1 0 0 1 1 1 0
CLK Q
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0 y

t t+1 t A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
Introduction to Embedded System-37
 Analysis of Clocked Sequential
Circuits
 State Diagram Present Next State Output
State x=0 x=1 x=0 x=1
A B A B A B y y
AB input/output
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
0/0 1/0 1 0 0 0 1 0 1 0
0/1 1 1 0 0 1 0 1 0

00 10
x
D Q A

0/1 Q
1/0 0/1 1/0
D Q B

CLK Q
01 11
y

1/0
Introduction to Embedded System-38
Analysis of Clocked Sequential Circuits
 D Flip-Flops
Example:
x D Q A
Present Next y
Input
State State CLK Q
A x y A
0 0 0 0
0 0 1 1 A(t+1) = DA = A  x  y
0 1 0 1
0 1 1 0
1 0 0 1 01,10
1 0 1 0
00,11 0 1 00,11
1 1 0 0
1 1 1 1 01,10
Introduction to Embedded System-39
Analysis of Clocked Sequential Circuits
 JK Flip-Flops J Q A

Example: x K Q

Present Next Flip-Flop

I/P J Q B
State State Inputs
A B x A B JA KA JB KB K Q

0 0 0 0 1 0 0 1 0 CLK
0 0 0 0 0 1
0 0 1 JA = B KA = B x’
0 1 0 1 1 1 1 1 0
JB = x’ KB = A  x
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1 A(t+1) = JA Q’A + K’A QA
1 0 1 1 0 0 0 0 0 = A’B + AB’ + Ax
1 1 0 0 0 1 1 1 1 B(t+1) = JB Q’B + K’B QB
1 1 1 1 1 1 0 0 0 = B’x’ + ABx + A’Bx’
Introduction to Embedded System-40
Analysis of Clocked Sequential Circuits
 JK Flip-Flops J Q A

Example: x K Q

Present Next Flip-Flop J Q B

I/P
State State Inputs
A B x A B JA KA JB KB K Q

0 0 0 0 1 0 0 1 0 CLK

0 0 1 0 0 0 0 0 1 1 0 1
0 1 0 1 1 1 1 1 0 00 11
0 1 1 1 0 1 0 0 1
0
1 0 0 1 1 0 0 1 1 0 0
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1 01 10
1 1 1 1 1 1 0 0 0 1
1
Introduction to Embedded System-41
Analysis of Clocked Sequential Circuits
x A
 T Flip-Flops T Q y

Example: R Q

Present Next F.F

I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0
TA = B x TB = x
0 1 1 1 0 1 1 0
y =AB
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0
A(t+1) = TA Q’A + T’A QA
= AB’ + Ax’ + A’Bx
1 1 0 1 1 0 0 1
1 1
B(t+1) = TB Q’B + T’B QB
1 1 1 0 0 1
=xB
Introduction to Embedded System-42
Analysis of Clocked Sequential Circuits
x A
 T Flip-Flops T Q y

Example: R Q

Present Next F.F

I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0 0/0 0/0
0 1 1 1 0 1 1 0 00 1/0 01
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0 1/1 1/0
1 1 0 1 1 0 0 1 11 10
1 1 1 0 0 1 1 1 0/1 0/0
1/0
Introduction to Embedded System-43
 Mealy and Moore Models
 The Mealy model: the outputs are functions of both the present
state and inputs.
 The outputs may change if the inputs change during the clock pulse
period.
» The outputs may have momentary false values unless the inputs are
synchronized with the clocks.

 The Moore model: the outputs are functions of the present state
only.
 The outputs are synchronous with the clocks.

Introduction to Embedded System-44

Mealy and Moore Models

Block diagram of Mealy and Moore state machine

Introduction to Embedded System-45

 Mealy and Moore Models
Mealy Moore
Present Next Present Next
I/P O/P I/P O/P
State State State State
A B x A B y A B x A B y
0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 1 0 1 0
0 1 0 0 0 1 0 1 0 0 1 0
0 1 1 1 1 0 0 1 1 1 0 0
1 0 0 0 0 1 1 0 0 1 0 0
1 0 1 1 0 0 1 0 1 1 1 0
1 1 0 0 0 1 1 1 0 1 1 1
1 1 1 1 0 0 1 1 1 0 0 1

For the same state, For the same state,

the output changes with the input the output does not change with the input

Introduction to Embedded System-46

 Moore State Diagram

State / Output

0 0
1
00/0 01/0

1 1

11/1 10/0
1
0 0
Introduction to Embedded System-47
 State Reduction and Assignment

 State Reduction Reductions on

the number of flip-flops and
the number of gates.
 A reduction in the number of
states may result in a reduction in
the number of flip-flops.

 An example state diagram

showing in Fig. 5.25.

Fig. 5.25 State diagram

Introduction to Embedded System-48
 State Reduction

State: a a b c d e f f g f g a
Input: 0 1 0 1 0 1 1 0 1 0 0
Output: 0 0 0 0 0 1 1 0 1 0 0
 Only the input-output sequences
are important.
 Two circuits are equivalent
» Have identical outputs for all
input sequences;
» The number of states is not
important.

Fig. 5.25 State diagram

Introduction to Embedded System-49
 Equivalent states

 Equivalent states
 Two states are said to be equivalent
» For each member of the set of inputs, they give exactly the same output and
send the circuit to the same state or to an equivalent state.
» One of them can be removed.

Introduction to Embedded System-50

 Reducing the state table

 Reducing the state table

 e = g (remove g);
 d = f (remove f);

Introduction to Embedded System-51

 Reducing the state table
 The reduced finite state machine

State: a a b c d e d d e d e a
Input: 0 1 0 1 0 1 1 0 1 0 0
Output: 0 0 0 0 0 1 1 0 1 0 0
Introduction to Embedded System-52
 Reducing the state table
 The checking of each pair of
states for possible
equivalence can be done
systematically using
Implication Table.
 The unused states are treated
as don't-care condition 
fewer combinational gates.

Fig. 5.26 Reduced State diagram

Introduction to Embedded System-53

 State Assignment
 State Assignment
 To minimize the cost of the combinational circuits.
 Three possible binary state assignments. (m states need n-bits, where 2n
> m)

Introduction to Embedded System-54

 Any binary number assignment is satisfactory as long as each state is
assigned a unique number.
 Use binary assignment 1.

Introduction to Embedded System-55

 Design Procedure

 Design Procedure for sequential circuit

 The word description of the circuit behavior to get a state diagram;
 State reduction if necessary;
 Assign binary values to the states;
 Obtain the binary-coded state table;
 Choose the type of flip-flops;
 Derive the simplified flip-flop input equations and output equations;
 Draw the logic diagram;

Introduction to Embedded System-56

Design of Clocked Sequential Circuits
 Example:
Detect 3 or more consecutive 1’s

0 1
S0 / 0 S1 / 0
0 State A B
S0 0 0
0 1
0 S1 0 1
S2 1 0
S3 / 1 S2 / 0 S3 1 1
1 1

Introduction to Embedded System-57

Design of Clocked Sequential Circuits
 Example:
Detect 3 or more consecutive 1’s

Present Next
Input Output
State State
A B x A B y 0 1
0 0 0 0 0 0 S0 / 0 S1 / 0
0 0 1 0 1 0 0
0 1 0 0 0 0
0 1 1 1 0 0 0 0 1
1 0 0 0 0 0
1 0 1 1 1 0
S3 / 1 S2 / 0
1 1 0 0 0 1
1 1 1 1 1 1 1 1

Introduction to Embedded System-58

Design of Clocked Sequential Circuits
 Example:
Detect 3 or more consecutive 1’s

Present Next
Input Output
State State
A B x A B y Synthesis using D Flip-Flops
0 0 0 0 0 0
0 0 1 0 1 0 A(t+1) = DA (A, B, x)
0 1 0 0 0 0 = ∑ (3, 5, 7)
0 1 1 1 0 0 B(t+1) = DB (A, B, x)
1 0 0 0 0 0 = ∑ (1, 5, 7)
1 0 1 1 1 0 y (A, B, x) = ∑ (6, 7)
1 1 0 0 0 1
1 1 1 1 1 1
Introduction to Embedded System-59
 Design of Clocked Sequential Circuits
with D F.F.
 Example:
Detect 3 or more consecutive 1’s

Synthesis using D Flip-Flops

B
DA (A, B, x) = ∑ (3, 5, 7) 0 0 1 0
=Ax +Bx A 0 1 1 0
DB (A, B, x) = ∑ (1, 5, 7) x B
= A x + B’ x 0 1 0 0

y (A, B, x) = ∑ (6, 7) A 0 1 1 0
x
=AB B
0 0 0 0
A 0 0 1 1
x
Introduction to Embedded System-60
Design of Clocked Sequential Circuits
with D F.F.
 Example:
Detect 3 or more consecutive 1’s

Synthesis using D Flip-Flops

DA = A x + B x
DB = A x + B’ x x D Q A

y =AB Q
y

D Q B

CLK Q

Introduction to Embedded System-61

 Flip-Flop Excitation Tables
Present Next F.F. Present Next F.F.
State State Input State State Input
Q(t) Q(t+1) D Q(t) Q(t+1) J K 0 0 (No change)
0 1 (Reset)
0 0 0 0 0 0 x 1 0 (Set)
0 1 1 0 1 1 x 1 1 (Toggle)
0 1 (Reset)
1 0 0 1 0 x 1 1 1 (Toggle)

1 1 1 1 1 x 0 0 0 (No change)
1 0 (Set)

Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0
Introduction to Embedded System-62
 Design of Clocked Sequential Circuits
with JK F.F.
 Example:
Detect 3 or more consecutive 1’s

Present Next Flip-Flop

Input
State State Inputs
Synthesis using JK F.F.
A B x A B JA KA JB KB
0 0 0 0 0 0 x 0 x JA (A, B, x) = ∑ (3)
0 0 1 0 1 0 x 1 x dJA (A, B, x) = ∑ (4,5,6,7)
0 1 0 0 0 0 x x 1 KA (A, B, x) = ∑ (4, 6)
0 1 1 1 0 1 x x 1 dKA (A, B, x) = ∑ (0,1,2,3)
0 x JB (A, B, x) = ∑ (1, 5)
1 0 0 0 0 x 1
dJB (A, B, x) = ∑ (2,3,6,7)
1 0 1 1 1 x 0 1 x
KB (A, B, x) = ∑ (2, 3, 6)
1 1 0 0 0 x 1 x 1
dKB (A, B, x) = ∑ (0,1,4,5)
1 1 1 1 1 x 0 x 0
Introduction to Embedded System-63
 Design of Clocked Sequential Circuits
with JK F.F.
 Example:
Detect 3 or more consecutive 1’s

Synthesis using JK Flip-Flops

B B
JA = B x KA = x’
0 0 1 0 x x x x
JB = x KB = A’ + x’
A x x x x A 1 0 0 1
x x
J Q A
B B
x K Q y 0 1 x x x x 1 1
A 0 1 x x A x x 0 1
J Q B x x

K Q

CLK
Introduction to Embedded System-64
Design of Clocked Sequential Circuits
with T F.F.
 Example:
Detect 3 or more consecutive 1’s

Present Next F.F.

Input
State State Input
A B x A B TA TB Synthesis using T Flip-Flops
0 0 0 0 0 0 0
0 0 1 0 1 0 1 TA (A, B, x) = ∑ (3, 4, 6)
0 1 0 0 0 0 1 TB (A, B, x) = ∑ (1, 2, 3, 5, 6)
0 1 1 1 0 1 1
1 0 0 0 0 1 0
1 0 1 1 1 0 1
1 1 0 0 0 1 1
1 1 1 1 1 0 0
Introduction to Embedded System-65
 Design of Clocked Sequential Circuits
with T F.F.
 Example:
Detect 3 or more consecutive 1’s

Synthesis using T Flip-Flops

TA = A x’ + A’ B x
TB = A’ B + B  x x
T Q A

Q y

B B
T Q B
0 0 1 0 0 1 1 1
Q
A 1 0 0 1 A 0 1 0 1
x x
CLK

Introduction to Embedded System-66