Module 3:Digital Electronics

Derived Gates

Quote of the day

“Never think you are nothing, never
think you are everything, but think you
are something and achieve anything ”.
― Albert Einstein
 Review basic gates

AND OR
X Y X·Y X Y X+Y NOT
0 0 0 0 0 0 Y Ȳ
0 1 0 0 1 1 0 1
1 0 0 1 0 1 1 0
1 1 1 1 1 1

X X
Y X·Y X+Y Y Ȳ
Y
 Derived gates
AND + NOT=NAND Logical Symbol
A A
A·B A·B
B B

NAND
A B A·͞ B
0 0 1
0 1 1
1 0 1
1 1 0
 Derived gates
• OR + NOT=NOR Logical Symbol
A
A+B
B

NOR
A B A+͞ B
0 0 1
0 1 0
1 0 0
1 1 0
 Derived gates
• Exclusive-OR EX-OR
Boolean Expression
for EX-OR
ĀB + AB̄

EX-OR
• Logical Symbol
A B AB
0 0 0
0 1 1
1 0 1
1 1 0
 Derived gates
• Exclusive-NOR EX-NOR
Boolean Expression
for EX-NOR

AB+ĀB̄

• Logical Symbol EX-NOR

A B AʘB
A 0 0 1
AʘB 0 1 0
B
1 0 0
1 1 1
 Universal gates
• NAND and NOR gates are called as universal gates
because we can implement all gates using these
gates.
• NAND as Universal gates
• NOT using NAND
A
A·A=Ā
A

• AND using NAND

A
B A·B = A·B
 NAND as Universal gates
• OR using NAND
A Ā

AB  A  B  A  B

B
B̄
• NOR using NAND
A Ā

AB
AB
B
B̄
 EX-OR using NAND
A A .A  B   A  A  B  A  AB
2
A 1
4
B A·B
3

B
 
B . A  B  B  A  B  B  AB
OUTPUT OF GATE 4:
B  A A  B  B  A  A  B  B  A  A  B  AB  AB
 EX-NOR using NAND
A A .A  B   A  A  B  A  AB
2
A  A B
1
4
B A·B 5
3

B
 
B . A  B  B  A  B  B  AB
 B A
OUTPUT OF GATE 4:

B  A A  B  B  A  A  B  B  A  A  B  AB  AB
OUTPUT OF GATE 5:

AB  AB     
 AB  AB  A  B  A  B 
 NOR as universal gate
• NOT using NOR • OR using NOR
A A͞+A=Ā A A͞+B A+B
B
A

• AND using NOR

A Ā
A  B  A B  A B
B
B̄
• NAND using NOR
A Ā A  B  A B  A B

B
B̄ A B
 EX-NOR using NOR
A

A
B A A͞+B
B

B
OUTPUT OF GATE 2:
 
A  . A  B  A  A  B  A   A  B  A  A  A  B  A  B

OUTPUT OF GATE 3:
 
B  . A  B  B  A  B  B   A  B  B  A  B  B  A  B

OUTPUT OF GATE 4:
A  B  A  B  A  B A  B  A  B A  B  A  B A  B
 EX-OR using NOR

A
B

• Output of Gate 4
A  B A  B
• Output Gate of 5
A  B A  B  A  B A  B  AB  AB  AB  AB
 Half adder using basic gates
• Half adder is a circuit which adds two one bit
binary data.
• The result of half adder generates sum(S) and
carry (C).
• Observe the truth table. Half Adder
A B S C
• S=AB and C=A·B,
0 0 0 0
• S=Ā·B+A·B̄
0 1 1 0
S=ĀB + AB̄
1 0 1 0
1 1 0 1
C=A.B
Fig. Logic Diagram using basic gates
 Half adder using Logic gates
• Use EX-OR gate for A S=AB
sum and AND gate B
to generate carry
C=A.B
• Half adder using
A
NAND 2
A 1 4
B A·B
3 S=AB

C=A·B

• Half adder does not add the carry generated

from previous stage.
 Full Adder
• Full adder is the circuit which adds two bits along with
carry in(Cin) and generates Sum(S) and carry out (Cout).
• From Truth Table Writing equation for S and Cout.
• S=ĀB̄Cin+ĀBCin̄ +AB̄Cin̄ +ABCin
• S=(ĀB̄+AB)Cin+ (ĀB+AB̄)Cin̄ Full Adder
• S=(AʘB)Cin+(AB) Cin̄ A B Cin S Cout
0 0 0 0 0
S=(AB) Cin
0 0 1 1 0
Now writing for Cout 0 1 0 1 0
• Cout =ĀBCin+AB̄Cin+ABCin̄ +ABCin 0 1 1 0 1
• Cout =ĀBCin+AB̄Cin+AB(Cin̄ +Cin) 1 0 0 1 0
• Cout =(ĀB+AB̄)Cin+AB 1 0 1 0 1
Cout =(AB) Cin+AB 1 1 0 0 1
1 1 1 1 1
 Full adder using Logic gates

AB

Full adder using NAND gates

A
2 Cin 7
A 6 S=AB  Cin
1 4 9
B A·B AB
3 8
B
10 Cout=(AB ) Cin +A·B
5 11
A·B
 Reduction of carry out expression using Boolean algebra
Consider the expression for carry out.
Cout =ĀBCin+AB̄Cin+AB(Cin̄ +Cin)
Cout =ĀBCin+A(B̄Cin+B)
Cout =ĀBCin+A(Cin+B)
Cout =(ĀB+A)Cin+AB=(B+A)Cin+AB

Cout = AB + Acin + Bcin

• This expression consists of product terms which
are summed together to form Boolean
expression. Such expressions are referred as sum
of product form(SOP) equations.
• Now let us implement this expression using basic
gates(AND-OR-NOT).
 Implementation of SOP equation using Basic Gates

• Cout = AB + Acin + Bcin

• To Implement this expression using basic gates
we require three AND gates and one OR gate.
A
1
B

A Cout
2 4
Cin

B
3
Cin
Implementation of SOP equation using NAND Gates

A Double Inversions cancel's out

1
B

A Cout
2 4
Cin

Bubbled OR gate
B
Cin
3  
A  B  C  A B C

Bubbled OR gate is
equivalent to NAND
gate, So Replace
Implementation of SOP equation using NAND Gates

A
1
B

A Cout
2 4
Cin

B
3
Cin

Bubbled OR gate is
equivalent to NAND
gate, So Replace