Tema 1: Introducción al Siseño de

Sistemas Electrónicos Digitales

Vivado, Nexys 4 DDR y

FPGA Artix 7

DSED, Curso 2017-2018

Pablo Ituero
RTL Hardware Design by P.
Chu
1
Slides Credit
• Introducción a Vivado: Transparencias del
Prof. Alexander Sudnitson de la Tallinn
University of Technology del curso IAY0600
Digital Systems Design (LECTURES)
• Placa Nexys 4 DDR: Manual de referencia de
Digilent.
https://reference.digilentinc.com/reference/prog
rammable-logic/nexys-4-ddr/reference-manual
• Artix 7 FPGA: Manual de referencia y
transparencias de Xilinx.

2
Introduction to Vivado
Design Suite
Vivado Design Suite
• Vivado is the new tool that only supports 7 series FPGA, UltraScale
and all more recent families.
• Completely re-developed from scratch
• The algorithms for Vivado are implemented with having the ever-growing
size of FPGAs in mind
• New deterministic Place and Route Algorithm
• All steps have the same view on a global data structure
• Vivado HLS: High-level sysnthesis tool
• Xilinx Design Constraints
• All tools in Vivado except SDK and Vivado HLS are integrated part of
the GUI
New integrated GUI

ISE

Vivado All tools in Vivado except

SDK and Vivado HLS are
integrated part of the GUI
Vivado GUI
Creating a new project
Project manager
IP Integrator
Simulation: create testbench
Simulation: edit testbench
Running simulation
Specifying constraints: Specifying constraints
XDC Consttraints (replacement of UCF)
• XDC constraints are a combination of:
• Industry standard Synopsys Design Constraints (SDC), and
• Xilinx proprietary physical constraints
• XDC constraints have the following properties:
• They are not simple strings, but are commands that follow the Tcl semantic.
• They can be interpreted like any other Tcl command by the Vivado Tcl
interpreter.
• They are read in and parsed sequentially the same as other Tcl commands.
Master XDC
## This file is a general .xdc for the Nexys4 DDR Rev. C
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

## Clock signal
#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];

##Switches

#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
Design elaboration: I/O Planning
Design elaboration
Synthesis and the synthesized design
Implementation and the implemented design
Reports
Generating bitstream
Hardware manager: open target
Hardware manager: open target
Hardware manager: program device
Questions?
Nexys 4 DDR
Nexys 4 DDR
Nexys 4 DDR
• https://reference.digilentinc.com/reference/programmable-
logic/nexys-4-ddr/reference-manual
7 Series FPGA Overview

Part 1
 7 Series FPGA Families

Lowest Power Industry’s Best Industry’s Highest

Maximum Capability and Cost Price/Performance System Performance
Logic Cells
Block RAM
DSP Slices
Peak DSP Perf.
Transceivers
Transceiver
Performance
Memory Performance
I/O Pins

I/O Voltages

7 Series FPGA Overview - 32 © Copyright 2011 Xilinx

CLB Structure

SLICE
▪ Two side-by-side slices per CLB
– Slice_M are memory-capable
LUT

– Slice_L are logic and carry only SLICE

LUT

▪ Four 6-input LUTs per slice

– Consistent with previous architectures
– Single LUT in Slice_M can be a 32-bit
shift register or 64 x 1 RAM

▪ Two flip-flops per LUT

– Excellent for heavily pipelined designs

CLB
–
7 Series FPGA Overview - 35 © Copyright 2011 Xilinx
CLB Overview

7 Series FPGA Overview - 36 © Copyright 2011 Xilinx

Recommended Design Flow

CLB resources are inferred for generic design logic and do not require
instantiation. Good HDL design is sufficient. A few items to note:

• CLB flip-flops have either a set or a reset. The designer must not use both set
and reset.
• Flip-flops are abundant. Pipelining should be considered to improve performance.
• Control inputs are shared across a slice or CLB. The number of unique control
inputs required for a design should be minimized. Control inputs include clock,
clock enable, set/reset, and write enable.
• A 6-input LUT can be used as a 32-bit shift register for efficient implementation.
• A 6-input LUT can be used as a 64 x 1 memory for small storage requirements.
• Dedicated carry logic implements arithmetic functions effectively.

7 Series FPGA Overview - 37 © Copyright 2011 Xilinx

FPGA Slice Resources

▪ Four six-input Look Up Tables (LUT)

▪ Wide multiplexers
▪ Carry chain
▪ Four flip-flop/latches LUT/RAM/SRL

▪ Four additional flip-flops

LUT/RAM/SRL

▪ The implementation tools (MAP)

are responsible for packing slice
resources into the slice LUT/RAM/SRL

LUT/RAM/SRL

01

7 Series FPGA Overview - 40 © Copyright 2011 Xilinx

6-Input LUT with Dual Output

▪ 6-input LUT can be two 5-input LUTs with common inputs

– Minimal speed impact to
a 6-input LUT
– One or two outputs
6-LUT
– Any function of six variables or A6
two independent functions of
A5 A5
five variables A4 A4 D
A3 5-LUT
A3
A2 A2
A1 A1
O6

A5
A4 D O5
A3
5-LUT
A2
A1

7 Series FPGA Overview - 41 © Copyright 2011 Xilinx

Wide Multiplexers

▪ Each F7MUX combines the outputs of two

LUTs together
– Can implement an arbitrary 7-input function
LUT/RAM/SRL

– Can implement an 8-1 multiplexer

▪ The F8MUX combines the outputs of the
two F7MUXes LUT/RAM/SRL

– Can implement an arbitrary 8-input function

– Can implement a 16-1 multiplexer
▪ MUX is controlled by the BX/CX/DX slice LUT/RAM/SRL

input
▪ MUX output can drive out combinatorially
or to the flip-flop/latch LUT/RAM/SRL

01

7 Series FPGA Overview - 42 © Copyright 2011 Xilinx

Carry Chain

▪ Carry chain can implement fast

arithmetic addition and subtraction
– Carry out is propagated vertically LUT/RAM/SRL

through the four LUTs in a slice

– The carry chain propagates from one
slice to the slice in the same column in LUT/RAM/SRL

the CLB above

▪ Carry look-ahead
– Combinatorial carry look-ahead over the LUT/RAM/SRL

four LUTs in a slice

– Implements faster carry cascading from
LUT/RAM/SRL
slice to slice 01

7 Series FPGA Overview - 43 © Copyright 2011 Xilinx

Slice Flip-Flops and Flip-Flop/Latches
FF FF/L

▪ Each slice has four flip-flop/latches (FF/L)

– Can be configured as either flip-flops or
latches
– The D input can come from the O6 LUT LUT/RAM/SRL

output, the carry chain, the wide multiplexer,

or the AX/BX/CX/DX slice input
▪ Each slice also has four flip-flops (FF) LUT/RAM/SRL

– D input can come from O5 output or the

AX/BX/CX/DX input
• These don’t have access to the carry chain,
wide multiplexers, or the slice inputs LUT/RAM/SRL

▪ If any of the FF/L are configured as latches,

the four FFs are not available
LUT/RAM/SRL

01

7 Series FPGA Overview - 44 © Copyright 2011 Xilinx

Slice Flip-Flop Capabilities

▪ All flip-flops are D type

▪ All flip-flops have a single clock input (CLK) D Q
CE
CE
▪ Clock can be inverted at the slice boundary
CK
CK
▪ All flip-flops have an active high chip enable (CE)
SRSR
▪ All flip-flops have an active high SR input
▪ Input can be synchronous or asynchronous, as determined by the
configuration bit stream
▪ Sets the flip-flop value to a pre-determined state, as determined by
the configuration bit stream

7 Series FPGA Overview - 45 © Copyright 2011 Xilinx

Distributed RAM

The function generators (LUTs) in SLICEMs can be implemented as a synchronous RAM

resource called a distributed RAM element. Multiple LUTs in a SLICEM can be combined
in various ways to store larger amount of data. RAM elements are configurable within a
SLICEM to implement these configurations:
• Single-Port 32 x 1-bit RAM
• Dual-Port 32 x 1-bit RAM
• Quad-Port 32 x 2-bit RAM
• Simple Dual-Port 32 x 6-bit RAM
• Single-Port 64 x 1-bit RAM
• Dual-Port 64 x 1-bit RAM
• Quad-Port 64 x 1-bit RAM
• Simple Dual-Port 64 x 3-bit RAM
• Single-Port 128 x 1-bit RAM
• Dual-Port 128 x 1-bit RAM
• Single-Port 256 x 1-bit RAM

7 Series FPGA Overview - 46 © Copyright 2011 Xilinx

Block RAM

▪ 36K/18K block RAM

– All Xilinx 7 series FPGA families use ADDRA Port A 36
36 DOA
same block RAM as Virtex-6 FPGAs 4
DIA
WEA
CLKA
▪ Configurations same as Virtex-6 FPGAs
36 Kb
– 32k x 1 to 512 x 72 in one 36K block Memory
Array
– Simple dual-port and true dual-port 36
ADDRB
36
DIB DOB
configurations 4 WEB
CLKB
– Built-in FIFO logic Port B

– 64-bit error correction coding per 36K

block
– Adjacent blocks combine to 64K x 1
without extra logic

7 Series FPGA Overview - 47 © Copyright 2011 Xilinx

DSP Slice

• All 7 series FPGAs share the same DSP slice

• 25x18 multiplier
• 25-bit pre-adder
• Flexible pipeline
• Cascade in and out
• Carry in and out
• 96-bit MACC
• SIMD support
• 48-bit ALU
• Pattern detect
• 17-bit shifter
• Dynamic operation
(cycle by cycle)

7 Series FPGA Overview - 48 © Copyright 2011 Xilinx

DSP Slice

7 Series FPGA Overview - 49 © Copyright 2011 Xilinx

7 Series FPGA Overview - 50 © Copyright 2011 Xilinx
ARTIX 7 FPGA
• https://www.xilinx.com/products/silicon-devices/fpga/artix-
7.html#documentation
• https://www.xilinx.com/support/documentation/data_sheets/ds180
_7Series_Overview.pdf
• https://www.xilinx.com/support/documentation/user_guides/ug474
_7Series_CLB.pdf
• https://www.xilinx.com/support/documentation/user_guides/ug479
_7Series_DSP48E1.pdf
• https://www.xilinx.com/support/documentation/user_guides/ug473
_7Series_Memory_Resources.pdf