Hierarchical Design

DSED, Curso 2018-2019

Pablo Ituero
RTL Hardware Design by P.
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Crédito de las transparencias y
lectura alternativa
• Transparencias del Prof. Pong P. Chu
• Transparencias del Prof. Erkay Savaş Sabancı
University
• La clase cubre el capítulo 13 de RTL Hardware
Design by P. Chu

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Outline
1. Introduction
2. Components
3. Generics
4. Configuration
5. Library
6. Package
7. Subprogram

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1. Introduction
• How to deal with 1M gates or more?
• Hierarchical design
• Divided-and-conquer strategy
• Divide a system into smaller parts

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Benefits of hierarchical
design
• Complexity management
• Focus on a manageable portion of the system, and
analyze, design and verify each module in isolation.
• Construct the system in stages by a designer or
concurrently by a team of designers.
• Help synthesis process

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• Design reuse
• Use predesigned modules or third-party cores
• Use the same module in different design
• Isolate device-dependent components (e.g., SRAM)

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Relevant VHDL constructs
• Component
• Generic
• Configuration
• Library
• Package
• Subprogram

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2. Components
• Hierarchical design usually shown as a block
diagram (structural description)
• VHDL component is the mechanism to
describe structural description in text
• To use a component
• Component declaration (make known)
• Component instantiation (create an instance)

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 Component declaration
• In the declaration section of entity
• Info similar to entity declaration
• Syntax:

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• E.g., a decade (mod-10) counter

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• Component declaration for dec_counter

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Component instantiation
• Instantiate an instance of a component
• Provide a generic value
• Map formal signals to actual signals

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• Syntax

• Port association (named association)

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• E.g., 2-digit decimal counter
(00=>01=> . . . =>99 =>00 . . .)

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• The VHDL code is a textual description of a
schematic

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• Positional association
• Appeared to be less cumbersome
• E.g., order of port declaration in entity:

• Alternative component instantiation

• Trouble if the order later changes in entity declaration

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• Mapping of constant and unused port
• E.g.,

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• Good synthesis software should
• remove the unneeded part
• perform optimization over the constant input

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3. Generics
• Mechanism to pass info into an
entity/component
• Declared in entity declaration and then can be
used as a constant in port declaration and
architecture body
• Assigned a value when the component is
instantiated.
• Like a parameter, but has to be constant

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• e.g., parameterized binary counter
• Note that the generic is declared before the port and
thus can be used in port declaration

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• e.g., to use the parameterized counter

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• e.g., parameterized mod-n counter
• Count from 0 to n-1 and wrap around
• Note that WIDTH depends on N

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• E.g., the 2-digit decimal counter again

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• Another useful application of generic: passing
delay information

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4. Configuration
• Bind a component with an entity and an
architecture
• Flexible and involved.
• Only simple binding of entity and architecture is
needed in synthesis
• Entity: like a socket in a printed circuit board
• Architecture: like an IC chip with same outline
• Not supported by all synthesis software

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• Application of binding:
• E.g., adder with different speed:
Fast but large adder or small but slow adder
• E.g., Test bench
descriptions at different stages

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• Type of configuration:
• Configuration declaration (an independent design unit)
• Configuration specification (in architecture body)
• Default binding: (no configuration)
• Component bound to an entity with identical name
• Component ports bound to entity ports of same names
• Most recently analyzed architecture body bound to the
entity

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• Configuration declaration
• An independent design unit
• Simplified syntax

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• E.g., create two architecture bodies for the
decade counter (one up and one down)

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• Configuration specification
• Included in the declaration section of architecture
body
• Syntax:

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• E.g.,

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• Component instantiation and configuration in
VHDL 93
• Remove component and configuration declaration
• Usually satisfactory for RT-level synthesis
• Syntax:

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• E.g.,

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5. Other constructs for
developing large system
• Subprogram
• Package
• Library

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Subprogram
• Include function and procedure
• Made of sequential statement
• Is not a design unit; must be declared
• Aimed for software hierarchy not hardware
hierarchy
• We only use function for synthesis
• Shorthand for complex expression
• “House-keeping tasks; e.g., type conversion

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Function Vs. Procedure
• Function
• Only receives IN parameters. Signals passed as
parameters cannot be assigned values.
• Execute in zero simulation time (wait statements
cannot be used)
• Easy to synthesize
• Procedure
• Can receive IN-OUT-INOUT parameters. Can
modify signals.
• Can include wait statements
• Hard to synthesize, just for simulation purposes
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• Syntax of function

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• E.g.,

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• E.g.,

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• E.g.,

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Package
• Groups of procedures and functions that are
related can be aggregated into a module that is
called package.
• A package can be shared across many VHDL
models.
• A package can also contains user defined data
types and constants.
• A library is a collection of related packages.
• Packages and libraries serve as repositories
for functions, procedures, and data types.

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Package
• Divided into
• Package declaration
• Package body (implementation of subprograms)
• Both are design units

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• Syntax

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• E.g.,

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• Improved mod-n counter

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Library
• Design units (design files)
• entity declaration,
• architecture body,
• configuration declaration,
• package declaration,
• package body
• Each design unit is analyzed (compiled) and
placed in a design library.
• Recall that libraries are generally implemented as
directories and are referenced by a logical name.
• this logical name corresponds to physical path to the
corresponding directory.

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• Default library: work
• E.g.,

• Non-default library has to be declared:

• syntax:

• E.g., library ieee;

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• E.g.,

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