ME - Micro - L1 - The PIC18F Microcontrollers - Architecture and Assembly Language Programming - VF - Eng

ME - Microprocessors
Lesson 1 - Architecture and Assembly Language Programming

Dr. Mohamad Mroué
1
What is a Microprocessor?
 Microprocessor is a computer Central Processing Unit (CPU) on a
single chip.
‒ It contains millions of transistors connected by wires.
Introduction to Embedded Systems Design using PIC18F – L1 2

Microprocessor Evolution
 Intel Created the First Commercial Microprocessor
‒ Introduced the 4004 in 1971, contained 2,300 transistors
 IBM Introduced its Original PC in 1981
‒ Used the Intel 8088 processor containing 29,000 transistors
 Smaller transistors allow

‒ More transistors per chip
‒ More processing per clock cycle
‒ Faster clock rates
‒ Smaller/cheaper chips

Microprocessor Evolution
 Moore’s Law: "The number of transistors incorporated in a chip will
approximately double every 24 months.“ (1965)

Introduction
 Microprocessors and microcontrollers are widely used in embedded systems. A
microcontroller includes a microprocessor in addition to a fixed amount of RAM,
ROM, I/O ports, and timers, all on a single chip.
‒ This makes them ideal for many applications where cost and space are critical.
‒ Some microcontrollers include an ADC (analog to digital converter).

Single-chip Computer/Microcontroller-based Design
 For tasks requiring low update rates, coding is accomplished using a
software programming language such as C.
 Tasks that need to have high deterministic update rates are coded
using the native assembly language for a particular microcontroller.
 The other constraint with a microcontroller-based system is the fixed

number of available peripherals.
‒ Though microcontroller vendors offer a wide range of devices with different
numbers and types of peripherals, it is not always possible to find one that
matches the application requirements perfectly.

Presentation Progress
1. Overview of the PIC18 Family

2. The PIC File Register
3. The PIC18F458 Instructions
4. Addressing Modes
5. PIC status register
6. PIC data format and directives
7. The program counter and program ROM space


4. Addressing Modes

Overview of the PIC18 Family
 In 1989, Microchip Technology Corporation introduced an 8-bit
microcontroller called the PIC (Peripheral Interface Controller).
 Microchip is one of the well known suppliers of microcontrollers
worldwide.
 PIC18xxx is available in 18- and 80-pin package.

PIC18 features
 The PIC18 has a RISC architecture that comes with some standard
features such as on-chip program (code) ROM, data RAM, data
EEPROM, timers, ADC, and USART and I/O ports.

Internal Architecture of PIC18
Data Bus
Harvard Architecture Data Memory
Program Memory
Program Bus
PIC18F448/458
Internal Architecture of PIC18 Data Bus
PIC18F448/458
Some features of the PIC18F458
 Operating frequency: DC – 40 MHz
 Program Memory: 32 Kbytes
 Data Memory: 1536 Bytes
 Data EEPROM: 256 Bytes
 I/O Ports: 5 (A, B, C, D, E)
 Timers: 4
 Serial Communication: USART
 10-bit ADC: 8 input channels
 Instruction Set: 75 instructions

I/O port pins and their functions
 A total of 33 pins are set aside for the five ports PORTA,
PORTB, PORTC, PORTD, and PORTE.
 Each port has three SFRs associated with it. They are
designated as PORTx, TRISx, and LATx.
‒ Note that TRIS stands for TRIState and LAT stands for LATch.
 The TRISx SFR is used solely for the purpose of making a
given port an input or output port.
‒ To make a port an output, we write 0s to the TRISx register.
TRISB 1 0 0 1 0 0 1 1
Example: RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

MOVLW B’10010011’ ; WREG = 10010011 PORTB
MOVWF TRISB ; TRISB = 10010011

Clock Cycles and Instruction Cycles

Q-Cycle Activity and Instruction Fetch

Q-Cycle Activity and Instruction Execution

Pipelining
 Pipeline vs. Non-pipeline:
‒ The idea of pipelining in its simplest form is to allow the CPU to fetch and
execute at the same time.

Fetch – Q1, Q2, Q3, Q4
 Instruction Fetch
‒ Example: ADDWF 0x34, F

Execute – Q1
 Instruction Decode

Execute – Q2
 Fetch Data

Execute – Q3
 The ALU performs operation

Execute – Q4
 Data written to destination


4. Addressing Modes

PIC microcontroller data RAM and EEPROM
 The data RAM size for the PIC18 varies
from 256 bytes to 4096 bytes.
 It has two components:

‒ General-Purpose RAM (GPR): divided into
banks of 256 bytes each.
‒ Special Function Registers (SFRs)
 In some of the PIC18 family members,

we also have a small amount of
EEPROM to store critical data that does
not need to be changed very often.
The PIC file register – Read Write RAM
 The Special Function Registers (SFRs) are dedicated to specific
functions such as ALU status, timers, serial communication, I/O ports,
ADC, and so on.
‒ The function of each SFR is fixed by the CPU designer at the time of design
because it is used for control of the microcontroller or peripheral.
 The PIC SFRs are 8-bit registers

‒ we use only direct addressing mode in accessing the SFR registers.
 The GPRs are used for data storage.

File register and access bank in the PIC18
 The file register of the PIC18 family can have a
maximum of 4096 (4K) bytes (addresses of
000-FFFH).
 It is divided into 256-byte banks

‒ Up to a maximum of 16 banks (16 × 256 = 4096)
‒ Every PIC18 has at least one bank for the file
register
• It is called the access bank
• It is divided into two equal sections of 128 bytes.
o GPRs: from locations 00H to 7FH
o SFRs: from locations F80H to FFFH
‒ A file register of more than 256 bytes will
necessitate bank switching.


4. Addressing Modes

Instruction Set
 Literal operations
 Byte-oriented file register operations
 Byte-to-Byte move operations (2-word)
 Bit-oriented file register operations
 Control operations
‒ CALL, GOTO, and Branch
 We can identify basically three addressing modes:

‒ Immediate addressing mode (Literal Operations)
‒ Direct addressing mode
‒ Indirect addressing mode (using FSRx)
Literal operations
 In immediate addressing mode, the operand is a
literal constant and comes immediately after the
opcode when the instruction is assembled.
‒ Notice that immediate data is called a literal in
the PIC.
 This addressing mode can be used to load

information into WREG and selected registers, but
not to any file register.
k

Literal operations
 The 8-bit WREG working register is the most
widely used in the PIC microcontroller. It is
used for all arithmetic and logic instructions.
 MOVLW instruction (MOVLW K)

‒ It moves 8-bit data into the WREG register.
‒ K is an 8-bit value that can range from 0-255 in
decimal or 00-FF in hex.
 ADDLW instruction (ADDLW K)

‒ It tells the CPU to add the literal value K to register
WREG and put the result back in the WREG
register.

Literal operations - Example
 In order to add numbers together in the PIC, the WREG register must
be involved. One form of the ADD instruction is
ADDLW K; WREG = WREG + K

Literal operations - Example
 Example: show how the flag register is affected by the following instructions.
‒ After the addition, register WREG contains 00 and the flags are as follows:
• C = 1 because there is a carry out from D7.
• Z = 1 because the result in WREG is zero.
• DC = 1 because there is a carry from D3 to D4.

Literal operations
k: constant
ff = 00 → FSR0 = k
ff = 01 → FSR1 = k
ff = 10 → FSR2 = k

Literal operations
ADDLW k ;WREG = WREG + k
ANDLW k ;WREG = WREG AND k
IORLW k ;WREG = WREG OR k
MOVLW k ;WREG = k
SUBLW k ;WREG = k - WREG
XORLW k ;WREG = WREG XOR k
RETLW k ;Return from subroutine, WREG = k

k
LFSR f, k ;FSR(f) = k
MOVLB k ;BSR = k
MULLW k ;PROD = WREG * k

Literal operations
 MULLW:
‒ MOVLW 0x25 ;WREG = 0x25
‒ MULLW 0x65 ;PROD = WREG * 0x65

Literal operations - Examples

Byte-oriented file register operations

WREG, FileReg, and ALU in PIC18
d = 0, dest = WREG d = 1, dest = f

PIC18F Instruction Set – Byte Oriented
f: RAM address

f: RAM address

opcode
Affected flags
Destination:
d = 0, dest = WREG RAM address
d = 1, dest = f If f = INDFx then address = FSRx
Bank: else, address = f
a = 0, bank 0
a = 1, bank BSR

ADDWF f, d ;dest = f + WREG
ADDWFC f, d ;dest = f + WREG + CY
ANDWF f, d ;dest = f and WREG
IORWF f, d ;dest = f OR WREG
XORWF f, d ;dest = f XOR WREG
DECF f, d ;dest = f - 1
DECFSZ f, d ;dest = f - 1, skip next inst if 0
DCFSNZ f, d ;dest = f - 1, skip next inst if not 0
INCF f, d ;dest = f + 1
INCFSZ f, d ;dest = f + 1, skip next inst if 0
INFSNZ f, d ;dest = f + 1, skip next inst if not 0

CPFSEQ f, d ;skip next inst if f = WREG
CPFSGT f, d ;skip next inst if f > WREG
CPFSLT f, d ;skip next inst if f < WREG
MOVF f, d ;dest = f
MOVWF f ;f = WREG
MULWF f ;PROD = f * WREG ( PROD = {PRODH, PRODL} )
COMF f, d ;dest = 1's complement of f

NEGF f ;f = 2's complement of f (-f)
CLRF f ;f = 0x00
SETF f ;f = 0xFF

SUBWF f, d ;dest = f - WREG
SUBWFB f, d ;dest = f - WREG - 𝐶𝑌 (Borrow = 𝐶𝑌)
SUBFWB f, d ;dest = WREG - f - 𝐶𝑌 (Borrow = 𝐶𝑌)
RLCF f, d ;Rotate Left through carry

RLNCF f, d ;Rotate Left f (No carry)
RRCF f, d ;Rotate Right through carry

RRNCF f, d ;Rotate Right f (No carry)
SWAPF f, d ;swap nibbles in f

TSTFSZ f, d ;test f, skip next instruction if 0

Byte-oriented operations - Examples
 ADDWFC and addition of 16-bit numbers
‒ Example: write a program to add two 16-bit numbers. The numbers are 3CE7H and 3B8DH. Assume that
fileReg location 6 = (8D) and location 7 = (3B). Place the sum in fileReg locations 6 and 7; location 6 should
have the lower byte.
;location 6 = (8D)
;location 7 = (3B)
MOVLW 0xE7 ;load the low byte now (WREG = E7H)

ADDWF 0x6, F ;F = W + F = E7 + 8D = 74 and CY = 1
MOVLW 0x3C ;load the high byte (WREG = 3CH)
ADDWFC 0x7, F ;F = W + F + carry, adding the upper byte
;with carry from lower byte
;F = 3C + 3B + 1 = 78H (all in hex)
‒ Notice the use of ADDWF for the lower byte and ADDWFC for the higher byte.


CPFSEQ f, d ;skip next inst if f = WREG

CPFSLT f, d ;skip next inst if f < WREG


Byte-to-Byte move operations (2-word)
 The MOVFF instruction copies data from RAM
(File Register)
one location in fileReg to another location
in fileReg. This is achieved without going
through the WREG register. 0x240 0x48
MOVFF 0x240, 0x268
0x268 0x5F
0x48

Bit-oriented file register operations

BSF f, b ; f(b) = 1
BCF f, b ; f(b) = 0
BTFSS f, b ; skip next instruction if f(b) = 1
BTFSC f, b ; skip nest instruction if f(b) = 0
BTG f, b ; f(b) = 1’s complement of f(b)

 one of the most important features of the PIC is its ability to access
the file register's RAM location in bits as well as bytes.
‒ This means that all I/O ports, SFRs, and general purpose RAM areas for the
PIC18 are bit-addressable because they are part of the file register data RAM.
‒ WREG is also bit-addressable because it is part of the SFRs.
 This is a very powerful feature of the PIC18 family.
 The bit-oriented instructions use only the direct addressing mode.

 There is no register indirect addressing mode for bit-oriented
instructions in the PIC18.

Bit-oriented operations - Examples
TRISB 1 1 1 1 1 1
0 1 1
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

PORTB
10
RB2 = 0 → RB2 = 1
RB2 = 1 → RB2 = 0

Control operations
 CALL, GOTO, and Branch

Instruction Format
 Opcode Field Descriptions

PIC18F Instruction Set

PIC18F Instruction Set


4. Addressing Modes

Direct and Indirect Addressing Modes
RAM
f
(File Register)
0x48
Direct
Access bank Addressing
CLRF 0x68, 0
Mode
in the
RAM address: 0x048 access bank
a = 0, access bank
0x068 0x00
0x48 0x068

Direct and Indirect Addressing Modes
RAM
f = INDF0
(File Register)
Indirect
Addressing
LFSR 0, 0x240 FSR0 Mode
CLRF INDF0 0x240 0x00
0x48 0x240
BSR f
0x02 0x48
MOVLB 0x02 Direct

CLRF 0x68, 1 RAM address: 0x248 Addressing
Mode
with
a = 1, bank BSR bank selection
0x268 0x00
0x48 0x268

Direct addressing mode
 Notice that if we use “DECF MYREG, W” instead of “DECF MYREG, F” in the BNZ
program, we will never get out of the loop because the values of MYREG and
WREG will remain unchanged.

Register indirect addressing mode
 In the indirect addressing mode, a register is used as a pointer to the
data RAM location.
 In the PIC18, three registers are used for this purpose: FSR0, FSR1,
and FSR2.
‒ FSR stands for file select register.
‒ The FSR is a 12-bit register allowing access to the entire 4096 bytes of data
RAM space in the PIC18.
‒ We use LFSR (Load FSR) to load the RAM address.

Register indirect addressing mode
 The FSR registers have the low-byte and high-byte parts called FSRxL and FSRxH.
‒ Note that the FSRxH is only 4-bit and the upper 4 bits are not used.
 Each of the FSR0, FSR1, and FSR2 registers has an INDF register associated with it,
and these are called INDF0, INDF1, and INDF2.
‒ When we move data into INDFx we are moving data into a RAM location pointed to by the
FSR.
‒ In the same way, when we read data from the INDF register, we are reading data from a RAM
location pointed to by the FSR.

Advantages of register indirect addressing mode
 Example: Write a program to copy the value 55H into RAM memory
locations 40H to 45H using using the register indirect addressing
mode with loop.

Auto-increment option for FSR
 Because the FSR is a 12-bit register, it can go from 000 to FFFH, which
covers the entire 4K RAM space of the PIC18.
 The PIC18 gives us the options of auto-increment and auto-
decrement for FSRn to overcome this problem.
 Example with CLRF instruction:
‒ Note: This table shows the syntax for the CLRF instruction, it works for all such
instructions.
 The auto-decrement or auto-increment affects the entire 12 bits of
the FSRn and has no effect on status register.
‒ This means that FSR0 going from FFF to 000 will not raise any flag.
 The option of PLUSWn is widely used for a RAM-based look-up table.

• LFSR FSR1,0x0120
• LFSR FSR2,0x0150
• MOVFF POSTINC1, POSTINC2


4. Addressing Modes

PIC18 status register
 The status register is an 8-bit register. It is also referred to as the flag
register.
‒ Only 5 bits of it are used by the PIC18. They are called conditional flags.
‒ These five flags are C (carry), DC (digital carry), Z (zero), OV (overflow), and N
(negative).
‒ Each of the conditional flags can be used to perform a conditional branch
(jump).

 C, the carry flag
‒ This flag is set whenever there is a carry out from the D7 bit. This flag bit is
affected after an 8-bit addition or subtraction.
 DC, the digital carry flag

‒ If there is a carry from D3 to D4 during an ADD or SUB operation, this bit is
set; otherwise it is cleared.
 Z, the z flag
‒ The zero flag reflects the result of an arithmetic or logic operation
‒ If the result is zero, then Z = 1, otherwise Z = 0;

 OV, the overflow flag
‒ This flag is set whenever the result of a signed number operation is too large, causing the
high-order bit to overflow into the sign bit.
The carry flag is used to detect errors in unsigned arithmetic operations.
The overflow flag is used to detect errors in signed arithmetic operations.
 N, the negative flag

‒ Binary representation of signed numbers uses D7 (MSB) as the sign bit.
‒ The negative flag reflects the result of an arithmetic operation
• If D7 of the result is zero, then N = 0, and the result is positive.
• If D7 of the result is one, then N = 1, and the result is negative.
The N and OV flag bits are used for signed number arithmetic operations.
 In unsigned number addition, we must monitor the status of C (carry flag).

 In signed number addition, the OV (overflow) flag must be monitored by the
programmer.


4. Addressing Modes

PIC data type
 The PIC microcontroller has only one data type. It is 8 bits, and the
size of each register is also 8 bits. It is the job of the programmer to
break down data larger than 8 bits (00 to FFH, or 0 to 255 in decimal)
to be processed by the CPU.

Data format representation
 There are four ways to represent a byte of data in the PIC assembler.
The numbers can be in hex, binary, decimal, or ASCII formats.
‒ Hex numbers: Ex. 99H, 99h, 0x99, 0X99, 99, H’99’ or h’99’
• If the value starts with the hex digits A-F, then it must be preceded with a zero: Ex. 0FEH
‒ Binary numbers: Ex. B’10011001’ or b’10011001’
‒ Decimal numbers: Ex. D’12’, d’12’ or .12
‒ ASCII character: Ex. A’2’ or a’2’

• To define ASCII strings (more than one character), we use the DB (define byte) directive.

Assembler directives
 While instructions tell the CPU what to do, directives (also called
pseudo-instructions) give directions to the assembler.
 EQU (equate)
‒ This is used to define a constant value or a fixed address.
‒ The EQU directive associates a constant number with a data or an address
label so that when the label appears in the program, its constant will be
substituted for the label.

 SET
‒ This directive is used to define a constant value or a fixed address. In this
regard, the SET and EQU directives are identical. The only difference is the
value assigned by the SET directive may be reassigned later.
 ORG (origin)
‒ The ORG directive is used to indicate the beginning of the address. It can be
used for both code and data. The number that comes after ORG must be in
hex.

 END directive
‒ This indicates to the assembler the end of the source (asm) file. The END
directive is the last line of the PIC program, meaning that anything after the
END directive in the source code is ignored by the assembler.
 LIST directive
‒ The LIST directive is unique to the PIC assembler. It indicates to the assembler
the specific PIC chip for which the program should be assembled.
 #include directive
‒ The #include directive tells the PIC assembler to use the libraries associated
with the specific chip for which we are compiling the program.

 Using EQU for fixed data assignment

 Using EQU for SFR address assignment

Assembling and linking a PIC program
 Source file: myfile.asm

The assembler converts the
instructions into machine code.
 Object file: myfile.o
 Error file: myfile.err
 Hex file: myfile.hex

 List file: myfile.lst
 Map file: myfile.map
 Debug file: myfile.cod
 Intermediate object file: myfile.out



2. The WREG register
4. Using instructions with the default access bank

Program counter in the PIC
 The program counter is used by the CPU to point to the address of the next
instruction to be executed.
 As the CPU fetches the opcode from the program ROM, the program counter is
incremented automatically to point to the next instruction.
 The program counter in the PIC18 family is 21-bit. This means that the PIC18
family can access program addresses 000000 to 1FFFFFH, a total of 2M of code.
However, not all members of the PIC18 family have the entire 2M (221 = 2M) of
on-chip ROM installed.
 Example: The PIC18F458 has 32K of on-chip ROM.

Where the PIC wakes up when it is powered up
 The microcontroller wakes up at memory
address 0000 when it is powered up
(Applying Vcc to the RESET pin).
‒ The PC (Program Counter) will have the value
of 00000 in it.
‒ It expects the first opcode to be stored in ROM
address 00000H.

Placing code in program ROM

Placing code in program ROM

Appendix
90
Addition of unsigned numbers
 Example: show how the flag register is affected by the following instructions.
‒ After the addition, register WREG contains 00 and the flags are as follows:
• C = 1 because there is a carry out from D7.
• Z = 1 because the result in WREG is zero.
• DC = 1 because there is a carry from D3 to D4.

COMF instruction
 This instruction complements (inverts) the contents of fileReg and
places the result in WREG or fileReg.
‒ Example:

NEGF (negative fileReg)
 This instruction takes the 2's complement of a file register.

DECF instruction
 This instruction decrements (subtract one from) the contents of
fileReg and places the result in WREG or fileReg.
‒ Example 1:

DECF instruction
 This instruction decrements (subtract one from) the contents of
fileReg and places the result in WREG or fileReg.
‒ Example 2:

 The difference between “INCF fileReg, W” and “INCF fileReg, F”
‒ Notice that When the second parameter is not stated, it is assumed to be fileReg (F)

 Notice that if we use “DECF MYREG, W” instead of “DECF MYREG, F” in the BNZ
program, we will never get out of the loop because the values of MYREG and
WREG will remain unchanged.

Bank switching and “INCF F, D, A” instruction
 With A = 0, the access bank is the default bank. Now to use banks
other than the access bank, two things must be done:
1. Load the BSR with the desired bank number, and
2. Make A = 1 in the instruction itself.
 Therefore, instruction "INCF MYREG, F, 1" has a totally

different meaning from "INCF MYREG, F, 0".
‒ The A = 1 means to use the bank pointed to by BSR.

 In the following code, we first load the bank number into the BSR register using
the MOVLB instruction, and then manipulate the contents of RAM location 0x240
(location 40 of bank 2):

 In the following code, although we loaded BSR, location 0x40 of the access bank
is used because the A bit was not indicated.

 Example: The role of the D and A bits.

Read followed by write I/O operation
 Due to the timing issue, we must be careful not to have two I/O
operations one right after the other.
 Examine the following rewrite of an earlier code fragment in which
data was read from PORTC and sent to PORTB:

 We need a NOP (or some other instruction) to make sure that the
data is written into WREG before it is read for outputting to Port B.
‒ This is called data dependency in CPU design.
 This type of data dependency is commonly referred to as RAW (Read-

After-Write).
 The NOP will introduce a bubble into the pipeline to remove data
dependency due to RAW.

 One way to avoid this problem is to use the MOVFF instruction, which
is a 4-byte instruction. This is coded as follows:

 Pipeline for Read Followed by Write I/O

Concept of signed numbers in computer
 Many applications require signed data. In signed byte operands, the
Most Significant Bit (MSB) D7 is set aside for the sign (+ or -), while
the rest of the bits, D0 to D6, are used for the magnitude.
 The sign is represented by 0 for positive (+) numbers and 1 for

negative (-) numbers.
Negative numbers
 For negative numbers, D7 is 1; however, the magnitude is represented
in its 2’s complement.

Overflow problem in signed number operations
 The PIC indicates the existence of an error by raising the OV
(overflow) flag, but it is up to the programmer to take care of the
erroneous result.
‒ If the result of an operation on signed numbers is too large for the register, an
overflow occurs and the programmer must be notified.
‒ The designers of the CPU created the overflow flag specifically for the
purpose of informing the programmer that the result of the signed number
operation is erroneous.
‒ The N flag is D7 of the result. If N = 0, the sum is positive (+) and if N = 1, then
the sum is negative.

When is the OV flag is set?
 In 8-bit signed number operations, OV is set to 1 if either of the
following two conditions occurs:
1. There is a carry from D6 to D7 but no carry out of D7 (C = 0).
2. There is a carry from D7 out (C = 1) but no carry from D6 to D7.

 We conclude that in any signed number addition, OV indicates
whether the result is valid or not.
‒ If OV = 1, the result is erroneous; if OV = 0, the result is valid.
 We can state emphatically that

‒ In unsigned number addition, we must monitor the status of C
(carry flag).
‒ In signed number addition, the OV (overflow) flag must be
monitored by the programmer.

 In the PIC, instructions such as BNC and BC allow the program to
branch right after the addition of unsigned numbers.
 There are also the BOV and BNOV instructions for the OV flag that
allow us to correct the signed number error.
 We also have two branch instructions for the N flag (negative), BN

and BNN.

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ME - Microprocessors

Lesson 1 - Architecture and Assembly Language Programming

Introduction to Embedded Systems Design using PIC18F – L1 2

 Smaller transistors allow

Introduction to Embedded Systems Design using PIC18F – L1 3

Introduction to Embedded Systems Design using PIC18F – L1 4

Introduction to Embedded Systems Design using PIC18F – L1 5

 The other constraint with a microcontroller-based system is the fixed

Introduction to Embedded Systems Design using PIC18F – L1 6

1. Overview of the PIC18 Family

Introduction to Embedded Systems Design using PIC18F – L1 7

1. Overview of the PIC18 Family

Introduction to Embedded Systems Design using PIC18F – L1 8

Introduction to Embedded Systems Design using PIC18F – L1 9

Introduction to Embedded Systems Design using PIC18F – L1 10

Harvard Architecture Data Memory

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Example: RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

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1. Overview of the PIC18 Family

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 It has two components:

 In some of the PIC18 family members,

 The PIC SFRs are 8-bit registers

 The GPRs are used for data storage.

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 It is divided into 256-byte banks

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1. Overview of the PIC18 Family

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 We can identify basically three addressing modes:

 This addressing mode can be used to load

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 MOVLW instruction (MOVLW K)

 ADDLW instruction (ADDLW K)

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RETLW k ;Return from subroutine, WREG = k

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d = 0, dest = WREG d = 1, dest = f

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MULWF f ;PROD = f * WREG ( PROD = {PRODH, PRODL} )

COMF f, d ;dest = 1's complement of f

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RLCF f, d ;Rotate Left through carry