Professional Documents
Culture Documents
Fds8880 N-Channel Powertrench: Mosfet
Fds8880 N-Channel Powertrench: Mosfet
April 2005
FDS8880
N-Channel PowerTrench® MOSFET
30V, 11.6A, 10mΩ
Features General Description
rDS(ON) = 10mΩ, VGS = 10V, ID = 11.6A This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
rDS(ON) = 12mΩ, VGS = 4.5V, ID = 10.7A either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
High performance trench technology for extremely low r DS(ON) and fast switching speed.
r DS(ON)
Branding Dash
5 4
5 6 3
1 7 2
2
3
4 8 1
SO-8
Thermal Characteristics
RθJC oC/W
Thermal Resistance, Junction to Case (Note 2) 25
o
RθJA Thermal Resistance, Junction to Ambient at 10 seconds (Note 3) 50 C/W
o
RθJA Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3) 85 C/W
Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 - - V
VDS = 24V - - 1
IDSS Zero Gate Voltage Drain Current µA
VGS = 0V TA = 150oC - - 250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA
On Characteristics
VGS(TH) Gate to Source Threshold Voltage V GS = VDS, ID = 250µA 1.2 - 2.5 V
ID = 11.6A, VGS = 10V - 0.0079 0.010
ID = 10.7A, VGS = 4.5V - 0.0096 0.012
rDS(ON) Drain to Source On Resistance Ω
ID = 11.6A, VGS = 10V,
- 0.0125 0.0163
TA = 150oC
Dynamic Characteristics
CISS Input Capacitance - 1235 - pF
VDS = 15V, VGS = 0V,
COSS Output Capacitance - 260 - pF
f = 1MHz
CRSS Reverse Transfer Capacitance - 150 - pF
RG Gate Resistance VGS = 0.5V, f = 1MHz 0.6 2.5 4.3 Ω
Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V - 23 30 nC
VDD = 15V
Qg(5) Total Gate Charge at 5V VGS = 0V to 5V - 12 16 nC
ID = 11.6A
Qg(TH) Threshold Gate Charge VGS = 0V to 1V - 1.3 1.6 nC
Ig = 1.0mA
Qgs Gate to Source Gate Charge - 3.3 - nC
Qgs2 Gate Charge Threshold to Plateau - 2.0 - nC
Qgd Gate to Drain “Miller” Charge - 4.2 - nC
2 www.fairchildsemi.com
FDS8880 Rev. A1
FDS8880 N-Channel PowerTrench® MOSFET
Switching Characteristics (VGS = 10V)
tON Turn-On Time - - 51 ns
td(ON) Turn-On Delay Time - 7 - ns
tr Rise Time VDD = 15V, ID = 11.6A - 27 - ns
td(OFF) Turn-Off Delay Time VGS = 10V, RGS = 11Ω - 38 - ns
tf Fall Time - 15 - ns
tOFF Turn-Off Time - - 80 ns
Notes:
1: Starting TJ = 25°C, L = 1mH, IAS = 12.8A, VDD = 30V, VGS = 10V.
2: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins. R θJC is guaranteed by design while RθJA is determined by the user’s board design.
3: RθJA is measured with 1.0 in2 copper on FR-4 board
4: FDS8880_NL is lead free product. FDS8880_NL marking will appear on the reel label.
3 www.fairchildsemi.com
FDS8880 Rev. A1
FDS8880 N-Channel PowerTrench® MOSFET
Typical Characteristics TA = 25°C unless otherwise noted
1.2 12
1.0 10
POWER DISSIPATION MULTIPLIER
VGS = 10V
0.6 6
0.4 4
0.2 2
RθJA=50o C/W
0 0
0 25 50 75 100 125 150 25 50 75 100 125 150
TA , AMBIENT TEMPERATURE (o C) TA , AMBIENT TEMPERATURE (oC)
2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2 RθJA=50oC/W
0.1
0.05
THERMAL IMPEDANCE
0.02
ZθJA, NORMALIZED
0.01
0.1
PDM
0.01 t1
t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
0.001
10-5 10-4 10 -3 10-2 10-1 100 101 10 2 103
t, RECTANGULAR PULSE DURATION (s)
1400
TRANSCONDUCTANCE
MAY LIMIT CURRENT TA = 25 oC
IN THIS REGION
FOR TEMPERATURES
ABOVE 25o C DERATE PEAK
VGS = 10V
IDM, PEAK CURRENT (A)
CURRENT AS FOLLOWS:
I = I25 150 - TA
100
10
10 -5 10-4 10-3 10-2 10-1 100 101 102 103
t , PULSE WIDTH (s)
4 www.fairchildsemi.com
FDS8880 Rev. A1
FDS8880 N-Channel PowerTrench® MOSFET
Typical Characteristics TA = 25°C unless otherwise noted
100 50
If R = 0 PULSE DURATION = 80µs
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) DUTY CYCLE = 0.5% MAX
If R ≠ 0 VDD = 15V
IAS, AVALANCHE CURRENT (A)
30
10 STARTING TJ = 25o C
20
TJ = 150oC TJ = -55oC
STARTING TJ = 150oC 10
1 0
0.01 0.1 1 10 100 1.5 2.0 2.5 3.0 3.5
tAV, TIME IN AVALANCHE (ms) VGS , GATE TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6. Transfer Characteristics
Figure 5. Unclamped Inductive Switching
Capability
50 50
PULSE DURATION = 80µs
VGS = 10V VGS = 4V
DUTY CYCLE = 0.5% MAX
40 40
rDS(ON), DRAIN TO SOURCE
ID, DRAIN CURRENT (A)
ON RESISTANCE (mΩ)
VGS = 5V
ID = 11.6A
VGS = 3V
30 30
20 20
10 TA = 25oC 10
PULSE DURATION = 80µs ID = 1A
DUTY CYCLE = 0.5% MAX
0 0
0 0.2 0.4 0.6 0.8 2 4 6 8 10
VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)
1.6 1.2
PULSE DURATION = 80µs VGS = VDS, ID = 250µA
NORMALIZED DRAIN TO SOURCE
1.0
1.2
1.0
0.8
0.8
Figure 9. Normalized Drain to Source On Figure 10. Normalized Gate Threshold Voltage vs
Resistance vs Junction Temperature Junction Temperature
5 www.fairchildsemi.com
FDS8880 Rev. A1
FDS8880 N-Channel PowerTrench® MOSFET
Typical Characteristics TA = 25°C unless otherwise noted
1.10 2000
ID = 250µA CISS = CGS + CGD
NORMALIZED DRAIN TO SOURCE
COSS ≅ CDS + C GD
BREAKDOWN VOLTAGE
1.05 1000
C, CAPACITANCE (pF)
1.00 CRSS = CGD
0.95
Figure 11. Normalized Drain to Source Figure 12. Capacitance vs Drain to Source
Breakdown Voltage vs Junction Temperature Voltage
10
VDD = 15V
VGS , GATE TO SOURCE VOLTAGE (V)
WAVEFORMS IN
2 DESCENDING ORDER:
ID = 11.6A
ID = 1A
0
0 5 10 15 20 25
Qg, GATE CHARGE (nC)
6 www.fairchildsemi.com
FDS8880 Rev. A1
FDS8880 N-Channel PowerTrench® MOSFET
Test Circuits and Waveforms
VDS BVDSS
tP
VDS
L
IAS
VARY tP TO OBTAIN VDD
+
REQUIRED PEAK IAS RG
VDD
VGS -
DUT
tP
0V IAS 0
0.01Ω
tAV
Figure 14. Unclamped Energy Test Circuit Figure 15. Unclamped Energy Waveforms
VDS
RL VDD Qg(TOT)
VGS
VDS
VGS = 10V
Qg(5)
VGS
+ Qgs2
VGS = 5V
VDD
-
DUT VGS = 1V
Ig(REF) 0
Qg(TH)
Qgs Qgd
Ig(REF)
0
Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
+
VGS
VDD
10% 10%
- 0
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0
Figure 18. Switching Time Test Circuit Figure 19. Switching Time Waveforms
7 www.fairchildsemi.com
FDS8880 Rev. A1
FDS8880 N-Channel PowerTrench® MOSFET
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM , and the maximum transient thermal impedance curve.
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM , in an Thermal resistances corresponding to other copper areas
application. Therefore the application’s ambient can be obtained from Figure 21 or by calculation using
temperature, TA (oC), and thermal resistance RθJA (oC/W) Equation 2. The area, in square inches is the top copper
must be reviewed to ensure that TJM is never exceeded. area including the gate and source pads.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part. 26
R θ JA = 64 + ------------------------------- (EQ. 2)
(T –T ) 0.23 + Area
JM A (EQ. 1)
P = -------------------------------
DM R θ JA The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 22 shows the effect of
In using surface mount devices such as the SO8 package, copper pad area on single pulse transient thermal
the environment in which it is applied will have a significant impedance. Each trace represents a copper pad area in
influence on the part’s current and maximum power square inches corresponding to the descending list in the
dissipation ratings. Precise determination of PDM is complex graph. Spice and SABER thermal models are provided for
and influenced by many factors: each of the listed pad areas.
1. Mounting pad area onto which the device is attached and Copper pad area has no perceivable effect on transient
whether there is copper on one side or both sides of the thermal impedance for pulse widths less than 100ms. For
board. pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
2. The number of copper layers and the thickness of the Therefore, CTHERM1 through CTHERM5 and RTHERM1
board. through RTHERM5 remain constant for each of the thermal
3. The use of external heat sinks. models. A listing of the model component values is available
in Table 1.
4. The use of thermal vias.
200
5. Air flow and board orientation.
RθJA = 64 + 26/(0.23+Area)
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
RθJA (o C/W)
150
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top 100
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides 50
the necessary information for calculation of the steady state
0.001 0.01 0.1 1 10
junction temperature or power dissipation. Pulse AREA, TOP COPPER AREA (in2)
applications can be evaluated using the Fairchild device Figure 21. Thermal Resistance vs Mounting
Spice thermal model or manually utilizing the normalized Pad Area
150
COPPER BOARD AREA - DESCENDING ORDER
0.04 in2
120 0.28 in2
IMPEDANCE (o C/W)
0.52 in2
ZθJA, THERMAL
0.76 in2
90 1.00 in2
60
30
0
10-1 100 101 102 103
t, RECTANGULAR PULSE DURATION (s)
Figure 22. Thermal Impedance vs Mounting Pad Area
8 www.fairchildsemi.com
FDS8880 Rev. A1
FDS8880 N-Channel PowerTrench® MOSFET
PSPICE Electrical Model
.SUBCKT FDS8880 2 1 3 ; rev August 2004
Ca 12 8 9.3e-10
Cb 15 14 9.3e-10
Cin 6 8 1.15e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD LDRAIN
Dplcap 10 5 DplcapMOD DPLCAP 5 DRAIN
2
10
Ebreak 11 7 17 18 33.5 RLDRAIN
RSLC1
Eds 14 8 5 8 1 51 DBREAK
Egs 13 8 6 8 1 RSLC2
+
Esg 6 10 6 8 1 5
51 ESLC 11
Evthres 6 21 19 8 1 -
Evtemp 20 6 18 22 1 50 +
-
RDRAIN 17 DBODY
6 EBREAK 18
ESG
It 8 17 1 8
-
+ EVTHRES 16
+ 19 - 21
Lgate 1 9 3.6e-9 LGATE EVTEMP MWEAK
8
Ldrain 2 5 1.0e-9 GATE RGATE + 18 - 6
1 MMED
Lsource 3 7 1.2e-10 9 20
22
RLGATE MSTRO
RLgate 1 9 36 LSOURCE
CIN SOURCE
RLdrain 2 5 10 8 7 3
RLsource 3 7 1.2 RSOURCE
RLSOURCE
Mmed 16 6 8 8 MmedMOD S1A S2A
Mstro 16 6 8 8 MstroMOD 12 RBREAK
13 14 15
17 18
Mweak 16 21 8 8 MweakMOD 8 13
S1B S2B RVTEMP
Rbreak 17 18 RbreakMOD 1 13 CB 19
CA
Rdrain 50 16 RdrainMOD 2.9e-3 + + 14 IT -
Rgate 9 20 2.5 6 5 VBAT
RSLC1 5 51 RSLCMOD 1e-6 EGS EDS +
8 8
RSLC2 5 50 1e3 - - 8
Rsource 8 7 RsourceMOD 5.4e-3 22
Rvthres 22 8 RvthresMOD 1 RVTHRES
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),5))}
.MODEL MmedMOD NMOS (VTO=1.8 KP=5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.5)
.MODEL MstroMOD NMOS (VTO=2.21 KP=150 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.53 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=25 RS=0.1)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
9 www.fairchildsemi.com
FDS8880 Rev. A1
FDS8880 N-Channel PowerTrench® MOSFET
SABER Electrical Model
REV August 2004
template FDS8880 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.6e-12,ikf=10,nl=1.01,rs=5.6e-3,trs1=8e-4,trs2=2e-7,cjo=5e-10,m=0.55,tt=1e-11,xti=2)
dp..model dbreakmod = (rs=0.2,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=4.27e-10,isl=10e-30,nl=10,m=0.38)
m..model mmedmod = (type=_n,vto=1.8,kp=5,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.21,kp=150,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.53,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5) LDRAIN
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4) DPLCAP 5 DRAIN
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=-1.0) 10 2
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1.0,voff=-1.5) RLDRAIN
c.ca n12 n8 = 9.3e-10 RSLC1
51
c.cb n15 n14 = 9.3e-10 RSLC2
c.cin n6 n8 = 1.15e-9 ISCL
}
}
10 www.fairchildsemi.com
FDS8880 Rev. A1
FDS8880 N-Channel PowerTrench® MOSFET
SPICE Thermal Model th JUNCTION
REV August 2004
FDS8880
Copper Area =1.0 in2
CTHERM1 TH 8 2.0e-3
CTHERM2 8 7 5.0e-3 RTHERM1 CTHERM1
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2 8
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
CTHERM8 2 TL 3 RTHERM2 CTHERM2
RTHERM1 TH 8 1e-1
7
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5 RTHERM3 CTHERM3
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18 6
RTHERM8 2 TL 25
2
Copper Area = 1.0 in 5
template thermal_model th tl
thermal_c th, tl
{
RTHERM5 CTHERM5
ctherm.ctherm1 th 8 =2.0e-3
ctherm.ctherm2 8 7 =5.0e-3
ctherm.ctherm3 7 6 =1.0e-2 4
ctherm.ctherm4 6 5 =4.0e-2
ctherm.ctherm5 5 4 =9.0e-2
ctherm.ctherm6 4 3 =2e-1 RTHERM6 CTHERM6
ctherm.ctherm7 3 2 1
ctherm.ctherm8 2 tl 3
3
rtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
RTHERM7 CTHERM7
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8 2
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25 RTHERM8 CTHERM8
}
tl CASE
COMPONANT 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.0 in2
RTHERM6 26 20 15 13 12
RTHERM7 39 24 21 19 18
11 www.fairchildsemi.com
FDS8880 Rev. A1
FDS8880 N-Channel PowerTrench® MOSFET
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
ACEx™ FACT Quiet Series™ ImpliedDisconnect™ POP™ Stealth™
ActiveArray™ FAST® IntelliMAX™ Power247™ SuperFET™
Bottomless™ FASTr™ ISOPLANAR™ PowerEdge™ SuperSOT™-3
CoolFET™ FPS™ LittleFET™ PowerSaver™ SuperSOT™-6
CROSSVOLT™ FRFET™ MICROCOUPLER™ PowerTrench® SuperSOT™-8
DOME™ GlobalOptoisolator™ MicroFET™ QFET® SyncFET™
EcoSPARK™ GTO™ MicroPak™ QS™ TinyLogic®
E2CMOS™ HiSeC™ MICROWIRE™ QT Optoelectronics™ TINYOPTO™
EnSigna™ I2C™ MSX™ Quiet Series™ TruTranslation™
FACT™ i-Lo™ MSXPro™ RapidConfigure™ UHC™
OCX™ RapidConnect™ UltraFET ®
Across the board. Around the world.™ OCXPro™ µSerDes™ UniFET™
The Power Franchise® OPTOLOGIC® SILENT SWITCHER® VCX™
Programmable Active Droop™ OPTOPLANAR™ SMART START™
PACMAN™ SPM™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
12 www.fairchildsemi.com
FDS8880 Rev.A