2316E 16,384 Bit Static Rom: Pin Configuration Block Diagram

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2316E

16,384 BIT STATIC ROM

■ Fast Access Time—45 0 ns Max. ■ EPROM/ROM Pin Compatible for


Cost-Effective System
■Single +5V ±10% Power Supply Development
■ Completly Static Operation
■ Intel MCS 80 and 85 Compatible
■ Inputs and Outputs TTL
Compatible
■ Three Programmable Chip
Selects for Simple Memory ■ Three-State Output for Direct
Expansion and System Interface Bus Interface

The Intel® 2316E is a 16,384-bit static, N-channel MQS read on ly m em ory (ROM) organized as 2048 words by 8 bits. Its
high b it density is ideal fo r large, non-volatile data storage applications such as program storage. The three-state outputs and
T T L in p u t/o u tp u t levels allow fo r dire ct interface w ith com mon system bus structures. The 2316E single +5V power supply
and 450 ns access tim e are both ideal fo r usage w ith high performance microcom puters such as the Intel M C S ™ -80 and
M C S ™ -85 devices.
A cost-effective system developm ent program may be implemented by using the pin com patible Intel 2716 16K U V EPROM
fo r pro to ty p in g and the lower cost 2316E ROM fo r productio n. The 2716 is fu lly com patible to the 2316E in all respects.
The three 2316E programmable chip selects may be defined by the user and are fixed during the masking process. T o sim p lify
the conversion fro m 2716 p ro to ty p in g to 2316E productio n, it is recommended th a t the 2316E programmable chip select
logic levels be defined the same as th a t shown in the below data sheet pin configuration. This pin con figura tion and these chip
select logic levels are the same as the 2716.

PIN CONFIGURATION BLOCK DIAGRAM

Ag

CS3

CS1

A10

cs 2
□7

06
D5
04
03

PIN NAMES
A o -A lO ADDRESS INPUTS
D 7 -D 0 DATA OUTPUTS
C S 1-C S 3 CHIP SELECT INPUTS
2316E

ABSOLUTE MAXIMUM RATINGS*


A m b ie n t Temperature Under Bias................... -1 0 °C to 80°C * COMMENT: Stresses above those listed under "Absolute M axi­
mum Ratings" may cause permanent damage to the device. This is a
Storage T e m p e ra tu re ................................... -6 5 °C to + 150°C
stress rating only and functional operation of the device at these or
Voltage On A ny Pin W ith Respect at any other conditions above those indicated in the operational
to G r o u n d ................ .. ...................................-0 .5 V to +7V sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
Power D is s ip a tio n ......................................................... 1.0 W att
reliability.

D.C. AND OPERATING CHARACTERISTICS


T a = 0°C to +70°C, VQQ = 5V ±10%, unless otherwise specified.

LIM ITS
SYM BO L PAR A M E TE R U N IT TEST C O N D ITIO NS
M IN . TY P .(1) MAX.

I LI Inp ut Load Current 10 IdA V||\| = 0 to 5.25V


(A ll Inp ut Pins)

■l OH O u tp u t Leakage C urrent 10 j iA Chip Deselected, V q u t = 4.0V

■l OL O u tp u t Leakage Current -2 0 iuA Chip Deselected, V q u t = 0-4V

■cc Power Supply Current 70 120 mA A ll Inputs 5.25V Data O ut Open

V lL Inp ut " L o w " Voltage -0 .5 0.8 V

V ,H Inp ut " H ig h " Voltage 2.4 Vcc+1-0V V

V0 L O u tp u t " L o w " Voltage 0.4 V I o l = 2.1 m A

VqH O u tp u t " H ig h " Voltage 2.4 V I q h = —400 /iA


N O TE : 1. Typical values for T a = 25°C and nominal supply voltage.

A.C. CHARACTERISTICS
T a = 0°C to +70°C, V c c = +5V ±10%, unless otherwise specified.

LIM ITS
SYM BO L P AR AM ETER U N IT
M IN . MAX.

tA Address to O utput Delay Time 450 ns

*co Chip Select to O u tp u t Enable Delay Time 120 ns

tD F Chip Deselect to O u tp u t Data Float Delay Tim e 10 100 ns

CONDITIONS OF TEST FOR CAPACITANCE121 T A = 25°C, f = 1 MHz


A.C. CHARACTERISTICS
L IM IT S
O u tp u t L o a d ........................... 1 T T L Gate and C l = 100 pF S YM BO L TEST
TYP. MAX.
Inp ut Pulse Levels....................................................0.8 to 2.4V
In p u t Pulse Rise and Fall Times (10% to 9 0 % ) ........... 20 ns C |N A ll Pins Except Pin Under 5 pF 10 pF
Tim ing Measurement Reference Level Test Tied to AC Ground
I n p u t ................................................................. IV a n d 2.2V C OUT A ll Pins Except Pin Under 10 pF 15 pF
O u t p u t ............................................................0.8V and 2.0V Test Tied to AC Ground
N O TE : 2. This parameter is periodically sampled and is not 100%
tested.
2316E

n9e.
A.C. Waveforms

Typical System Application (8K x 8 ROM Memory)

\ ADDRESS BUS
)
n r ~ .... ! I
,
MCS-80

s CONTROL BUS
J SYSTEM

11 .. I I I BUS

s_ _ DATA BUS
________ i
A12 z "' / ' A n

CS2
CHIP
SELECT
DECODER CS3
(INTEL
8205)
CS2
CS3

CS2
CS3

CS2

CS3

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