FILKOM | UB

CCE61206

Pemrograman FPGA
Agenda

• Introduction
• Review Sistem Digital
• FPGA design dengan Xilinx
• Rangkaian kombinasional
• Rangkaian Enkoder, Decoder, Multiplekser, Demux
• Rangkaian sekuensial (counter)
• -----------------------------------UTS-------------------------------------
• Desain project dan presentasi
• -----------------------------------UAS-------------------------------------

Slide 2
20 September
2021
 MULTIPLEXER

Slide 3
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Multiplexer
⚫ A multiplexer has
− N control inputs
− 2N data inputs
− 1 output
⚫ A multiplexer routes (or connects) the selected data input to the
output.

Data

Slide 4
inputs
Control
20 September input
2021
4 to 1 Multiplexer

Slide 5
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 Slide 6
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 Slide 7
20 September
2021
 Unlike in encoder/decoder, “sel”
become input port in entity as
control port
Therefore, we don’t need to
declare it in architecture

Slide 8
20 September
2021
 Dg cara sekuensial:

begin
process(sel)
begin
case sel is
when “111" => O <= I(7);
when “110" => O <= I(6);
when "101" => ...
...
....
....
end case;
end process;

Slide 9
20 September
2021
 DEMULTIPLEXER

Slide 10
20 September
2021
Demultiplexer
⚫ A demultiplexer has
− N control inputs
− 1 data input
− 2N outputs
⚫ A demultiplexer routes (or connects) the data input to the selected output.
− The value of the control inputs determines the output that is selected.
⚫ A demultiplexer performs the opposite function of a multiplexer.

Slide 11
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2021
library IEEE; out0
use IEEE.STD_LOGIC_1164.ALL;
bitin out1
entity demux1_4 is out2
port (
out0 : out std_logic; --output bit out3
out1 : out std_logic; --output bit
out2 : out std_logic; --output bit
out3 : out std_logic; --output bit
sel : in std_logic_vector(1 downto 0);
bitin : in std_logic --input bit sel
);
end demux1_4; bitin C0 C1 out0 out1 out2 out3

architecture Behavioral of demux1_4 is bitin 0 0 bitin 0 0 0

begin bitin 0 1 0 bitin 0 0
process(bitin,sel) bitin 1 0 0 0 bitin 0
begin bitin 1 1 0 0 0 bitin
case sel is
when "00" => out0 <= bitin; out1 <= '0'; out2 <= '0'; out3 <='0';
when "01" => out1 <= bitin; out0 <= '0'; out2 <= '0'; out3 <='0';
when "10" => out2 <= bitin; out0 <= '0'; out1 <= '0'; out3 <='0';
when others => out3 <= bitin; out0 <= '0'; out1 <= '0'; out2 <='0';
end case;
end process;

Slide 12
end Behavioral;

20 September
2021
Dg cara concurrent:

architecture Behavioral of demux1_4 is

begin
With sel select
out0 <= bitin when “00”,
‘0’ when others;

out1 <= bitin when “01”

‘0’ when others;

.... (lanjutkan utk out 1 dan out 2)

....
.....

end Behavioral;

Slide 13
20 September
2021
Tugas kelompok multiplexer:
DOWNLOAD & SIMULASI MUX 4 to 1

Input berupa kombinasi 4 switch selector

Output berupa salah satu LED

Selector berupa 2 buah push button

Slide 14
20 September
2021