DB g) 1/0 Interface Questions ee ae Ee clay Start Complete Exam Preparation Giese Pibecis Mock Tests CO tie Coreen Byte Download App VO Interface MCQ Qiiestion 1 View this Question Online > The first instructor of bootstrap loader program of an operating system is stored in 1. RAM 2. Hard Disk 3. BIOS 4. None Answer (Detailed Sollition Below) Option 3: BIOS 1/0 Interface MCQ Question 1 Detailed Solution The Correct Answer is BIOS. © key Points + The first instructor of the bootstrap loader program of an operating system is stored in BIOS(Basic Input/Output System). * The bootstrap loader is a programme that resides on the EPROM, ROM or other non-volatile memory of the machine. + It is executed by the processor automatically when the device is turned on. To continue installing the computer's operating system, the bootstrap loader reads the boot sector of the hard drives.+ The bootstrap loader first conducts the power-on self-test, also referred to as POST, when the machine is switched on or restarted. + The bootstrap loader loads the operating system for the machine into memory if the POST is ‘successful and no problems are found. + Itis then possible for the machine to access, load, and operate the operating system. * In computers that have an EFI (Extensible Firmware Interface), the bootstrap loader has been replaced and is now part of the EFI BIOS. Meee er hari Start Complete Exam Preparation ic ee eerie Coreen Download App V/0 Interface MCQ Question 2 View this Question Online = Which interrupt in 8085 Microprocessor is non-maskable? 1. RST5.5 2. RST7.5 3. TRAP 4, Both (a) and (b) Answer (Detailed Solution Below) Option 3: TRAP 1/0 Interface MCQ Question 2 Detailed Solution Anon-maskable is an interrupt which can not be disabled. RST 7.5, RST 5.5 are maskable interrupts but TRAP is a non-maskable interrupt.interrupts; Type Vector TRAP |Non-Maskadle| 0024 RST7.5| Maskable 003C RST6.5] Maskable 0034 RST5.5| Maskable 002c INTR | Maskable 0000 to 0038} ‘ eee ne ut Rete) Start Complete Exam Preparation CoA eco Download App V/0 Interface MCQ Question 3 View this Question Online > Arrange the following addresses in ascending order of their priority A. Address for divide error is OO00H B. Address for one - byte interrupt instruction, INT is O00CH C. Address for overflow, INTO instruction is 0010H D. Address for single step trap - TF must be set is 0004H E. Address for non maskable interrupt is O008H Choose the correct answer from the options given below: 1. A,DE,B,C 2. AED,B,C 3. AEB,C,D 4. ADB,E,CAnswer (Detailed Solution Below) Option 1: A,D, E, B,C V/0 Interface MCQ Question 3 Detailed Solution It is @ part of the current system interrupt state, which indicates the interrupt request that will currently be accepted. Markable interrupt: Those interrupt which can be disabled or ignored by the microprocessor are known as maskable interrupts Eg. INTR RST 7.5, RST 6.5, RST 5.5 TRAP is a Non markable interrupt because it can not be ignored by the microprocessor. Explanation: Priority order for given interrupt is O000H < 0004H < 0008H < O00CH <0010H ie. A Which method bypasses the CPU for certain types of data transfer? 1. Software interrupts 2. Interrupt driven 1/0 3. Polled /O 4, Direct memory access (DMA) Answer (Detailed Solution Below) Option 4 : Direct memory access (DMA) V/O Interface MCQ Question 4 Detailed Solution Concept: Direct memory access (DMA) is @ feature of computer systems thet allows certain hardware subsystems to access main system memory (random-access memory), independent of the central processing unit (CPU). Hence DMA bypasses the CPU for certain types of data transfer Types: ‘There are three modes of DMA operation: Burst mode DMA: + The CPU can be put on hold while the DMA transfer occurs and a full block of possibly hundreds or thousands of bytes can be moved. + For the entire duration of the transfer, the CPU stays idle and the DMA controller and the peripheral device get complete access to the system buses. Transparent mode:+ It takes the most time to transfer a biock of data, yet itis also the most efficient mode in terms of overall system performence. + In transparent mode, the DMA controller transfers data only when the CPU is performing operations that do not use the system buses. Cycle stealing mode: + In this only one byte of data transferred in a single request. + After one byte of data transfer, the control of the system bus is given back to the CPU transferring one byte of data per request, until the entire block of data has been transferred Peete rte Start Complete Exam Preparation Dear Ae ce a ar ole Download App 1/0 Interface MCQ Question 5 View this Question Online > Chain printer is a printer. 1. non-impact 2. daisy wheel 3. dot matrix 4. line Answer (Detailed Solution Below) Option 4: line 1/0 Interface MCQ Question 5 Detailed Solution The Correct Answer is Option 4 i.e Line.* Line Printer: > {tis an impact printer that prints one line of text at a time before advancing to another line. + Drum printers, chain printers, and dot matrix printers are the types of Line Printers. 2 Inachain printer, a chain of character set are used. * Non- impact printer: > Itisa type of printer that prints without touching the ribbon onto paper to print. + Inkjet printers and Laser printers are examples of non-impact printers. + Dot-matrix printer: = Itis a type of printer that prints by using a fixed number of pins against an ink ribbon to print dot patterns in the appropriate shape. + Daisy wheel printer: > In daisy wheel printer letters are pushed against the ribbon and it orints on the paper. eae Maen) Sela mel Cee Ll) sole Ceres Download App rt ca bo live eerie ey) Dea V/O Interface MCQ Question 6 View this Question Online > An interrupt in which the external device supplies its address as well as the interrupt request is interrupt Vectored 2 Maskable 3. Non-maskable 4 Designated Answer (Detailed Solution Below) Option 1:Vectored 1/0 Interface MCQ Question 6 Detailed Solution Vectored Interrupt : In this type of interrupts the interrupting device directs the processor for Interrupt service routine. Maskable An interrupt whose interrupt service can be stopped from being serviced temporarily is called Maskable Interrupt. Non Maskable An interrupt whose service cannot be delayed is called Non-Maskable Interrupt India's #1 Learning Platform Start Complete Exam Preparation Daily Live coo maa hea rere Question Bank & Quizzes Download App V/O Interface MCQ Question 7 View this Question Online >Match List| with List II List 1 List II \()) 1/0 interface informs (A) Handshaking the CPU that device is ready for transfer (I) requires two control \(B) Programmed 1/0 |signals_ working in opposite directions ((lll) has local memory & \control large set of I/O |devices. \(IV) require CPU to check \(D) 1/0 processor the I/O flag & perform [transfer ((C) Interrupt- initiated 1/0 Choose the correct answer from the options given below: 1. A-L.B-I,C-10, DAV 2. A-I,B-IV,C-IIL0-1 3. A-I,B-IV,C-1, D-Ill 4. A-WV,B-Ill,C-1,D-1 Answer (Detailed Solution Below) Option 3: A-II,B-IV,C-1, D-Ill 1/0 Interface MCQ Question 7 Detailed Solution The correct answer is option 3. © Key Points Handshaking: When one computer sends a message to another indicating that it wants to create @ contact channel, itis called handshaking. It requires two control signals working in opposite directions Programmed 1/0: The output of the 1/0 instructions written in the computer programmes the trigger. It requires the CPU to check the I/O flag & perform the transfer Interrupt-initiated /O:Interrupt powered I/O is a different way to deal with I/O. interrupt I/O is a method of monitoring input/output operation by sending a signal from a peripheral or terminal that needs to send or receive data. 1/0 interface informs the CPU that the device is ready for transfer V0 processor: Aprocessor with direct memory access is known as an input-output processor (IOP). The computer system is divided into memory units and processors in this way. I/O processor has local memory & control a large set of I/O devices. = Hence the correct answer is 4-//, B -/\/ C- |, D-IL PX eee ae pee tlia) eRe Toa Start Complete Exam Preparation fon ies 5 V/O Interface MCQ Question 8 View this Question Online > The errors that can be pointed out by the compiler are 1. Syniax errors 2. Intemal errors 3. Sematic errors 4. Logical errors Answer (Detailed Solution Below) Option 4 : Syntax errors 1/0 Interface MCQ Question 8 Detailed Solution ‘The correct answer is Syntax errors. + A syntax error is an error in the source code of a program. + Since computer programs must follow strict syntax to compile correctly, any aspects of the code that do not conform to the syntax of the programming language will produce a syntax error.* Unlike logic errors, which are errors in the flow or logic of a program, syntax errors are small grammatical mistakes, sometimes limited to a single character. ~ For example, a missing semicolon at the end of a line or an extra bracket at the end of a function may produce 2 syntax error. © Key Points + Internal errors are due to faulty logic or coding in the program. + Common types of internal errors include Bounds errors, Inserting a null pointer into a collection, Attempting to use a bad date. * A semantic error is 2 violation of the rules of the meaning of a natural language or a programming language. > semantic errors are the hardest to debug because the interpreter provides no information about what is wrong. + A logic error (or logical error) is a mistake in a program's source code that results in incorrect or unexpected behavior. © It {Sa type of runtime error that may simply produce the wrong output or may cause a program to crash while running. Dea RoC oie) ae ar eee Start Complete Exam Preparation Oe eaes Ronan Download App V/O Interface MCQ Question 9 View this Question Online > The Communication between the components in a microcomputer takes place via the address and _ 1. VO bus 2. Data bus 3. Address bus 4. Control lines Answer (Detailed Solittion Below) Option 2: Data bus1/0 Interface MCQ Question 9 Detailed Solution Concept: A group of wires called bus is used to provide necessary signals for communication between modules. A bus that connects major computer components is callled system bus. It connects the CPU, memory and I/0 modules. System bus is divided further into three types: data bus, address bus and contro! bus. lanation: Data bus: These are used to send data to memory and output ports and to receive data from memory and input port. These are bi-directional. The Communication between the components in a microcomputer takes place via the address and data bus. Address bus: It is unidirectional in nature. Address is send from CPU to memory and I/0 port. Control bus: Control lines regulate the ectivity on the bus. CPU sends the signals on the control bus to enable the outputs of addressed memory devices or port devices. a og ieee an ru Bartel) Start Complete Exam Preparation Ree Danes cg Mock Tests Ema raed Cres eau Download App V/O Interface MCQ Question 10 View this Question Online > Consider the following statements. |. Daisy chaining is used to assign priorities in attending interrupts. Il. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. Ill. In polling, the CPU periodically checks the status bits to know if any device needs its attention. IV. During DMA, both the CPU and DMA controller can be bus masters at the same time. Which of the above statements is/are TRUE? 1. land Il only 2. land IVoniy 3. land Illonly4, Monty Answer (Detailed Solution Below) Option 3: | and Ill only 1/0 Interface MCQ Question 10 Detailed Solution Statement |: TRUE In daisy chaining method of interrupt handling, the devices are connected serially in such a manner that nearest device to the CPU has the highest priority, followed by the next device and so on. ‘Statement Il: FALSE In vectored interrupt, vector address is given to the CPU to identify the source of interrupt. For example, in 8085 lP RST 4.5 is @ vectored interrupt. Here, 4.5 is the interrupt vector which gives the vector address as 4.5 x 8 = (36)19 = (0024)i6 Statement Ill: TRUE. In polling method, the CPU polls each device to check status bits to find out if the device has raised any interrupt. Itis 2 software method. Statement IV: FALSE In DMA mode, either the CPU or the DMA controller would gain control of the system bus a time, but Not both. Accordingly, the CPU would be either in busy state or Hold state. It would be in busy state until I/O device prepares the data and would go to Hold state when I/O device starts transferring data to main memory via DMA controller.