NXP Semiconductors LPC1769/68/67/66/65/64/63

32-bit ARM Cortex-M3 microcontroller

6. Block diagram

debug JTAG XTAL1

port interface RMII pins USB pins XTAL2
RESET

LPC1769/68/67/ USB PHY

TRACE MODULE

TEST/DEBUG
66/65/64/63 CLOCK
EMULATION

INTERFACE
GENERATION,
POWER CONTROL, CLKOUT
USB HOST/
ARM ETHERNET SYSTEM
MPU
DMA DEVICE/OTG
CORTEX-M3 CONTROLLER FUNCTIONS
CONTROLLER CONTROLLER
WITH DMA(1)
WITH DMA(1)
clocks and
I-code D-code system master master master controls
bus bus bus
slave
ROM
slave

MULTILAYER AHB MATRIX

SRAM 32/64 kB

FLASH
slave slave slave slave ACCELERATOR
P0 to HIGH-SPEED
P4 GPIO FLASH
AHB TO AHB TO
512/256/128 kB
APB APB
BRIDGE 0 BRIDGE 1 APB slave group 1 SCK0
SCK1 APB slave group 0
SSEL0
SSEL1 SSP0 MISO0
MISO1 SSP1
MOSI0
MOSI1
UART2/3 RXD2/3
RXD0/TXD0
UART0/1 TXD2/3
8 UART1
3 I2SRX
RD1/2
CAN1/2(1) I2S(1)
3 I2STX
TD1/2 TX_MCLK
SCL0/1 RX_MCLK
I2C0/1
SDA0/1
SCL2
SCK/SSEL I2C2
SPI0 SDA2
MOSI/MISO
2 MAT0/1 RI TIMER
TIMER 0/1 4 MAT2
2 CAP0/1
2 MAT3
WDT TIMER2/3 2 CAP2
2 CAP3
PWM1[7:0]
PWM1 EXTERNAL INTERRUPTS EINT[3:0]
PCAP1[1:0]

AD0[7:0] 12-bit ADC SYSTEM CONTROL

MCOA[2:0]
PIN CONNECT MCOB[2:0]
MOTOR CONTROL PWM
MCI[2:0]
P0, P2 MCABORT
GPIO INTERRUPT CONTROL
DAC(1) AOUT
RTCX1 32 kHz
OSCILLATOR RTC PHA, PHB
RTCX2 QUADRATURE ENCODER
INDEX
VBAT BACKUP REGISTERS
= connected to DMA
RTC POWER DOMAIN

002aad944

(1) Not available on all parts. See Table 2.

Fig 1. Block diagram

LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2020. All rights reserved.

Product data sheet Rev. 9.10 — 8 September 2020 6 of 93