Alfaisal University - College of Engineering

Electrical Engineering Department

EE 210: Digital Logic Systems
Assignment #4
Spring 2021 - Due Date: April 8, 2021 at 11:59pm (midnight)

Student Name: SOLUTION

Student Number:

I declare that this submission is my own, and that no part of it has been copied from another source except
where properly acknowledged.
Student’s signature: _________________________

Follow the guidelines below in submitting your work.

1. Your homework should have this cover page duly filled out by you.
2. Where possible and applicable, your solution should be typed and printed.
3. Use white, preferably plain, A4-sized paper in your submission.
4. Start a new page for every new problem. However, more than one sub-problem (or short
problems) can be answered on the same sheet.
5. Arrange problems in the order they are assigned. Do not change problem numbers.
6. Show your work in an organized manner. Do not crowd your solution pages.
7. Elaborate on any assumptions made or shortcuts (jumps) taken in your solution.
8. Reference your figures, tables, constants, equations and conversions, used to complete the
problem.

Problem P1 P2 P3 Total
Mark
Maximum 20 15 35 70

Evaluator’s initials: _______________

Date: _______________

Course Learning Outcomes (CLO) Problems

Design digital logic systems using gates and blocks (de/multiplexers,

CLO1 3
encoders/decoders, adders, latches, flip lops, registers, etc.)
Evaluate and validate the design and operation of digital logic
CLO2 1
systems.
 Alfaisal University - College of Engineering
Electrical Engineering Department
EE 210: Digital Logic Systems
Assignment #4
Spring 2021 - Due Date: April 8, 2021 at 11:59pm (midnight)

Problem 1:
Using four half adders
a) Design a full subtractor circuit incrementor. (A circuit that adds one to a four-bit binary number).
b) Design a four bit combinational decrementor. (A circuit that subtracts one from a four-bit binary
number).
 Alfaisal University - College of Engineering
Electrical Engineering Department
EE 210: Digital Logic Systems
Assignment #4
Spring 2021 - Due Date: April 8, 2021 at 11:59pm (midnight)

Problems 2:
Construct a 16 X 1 multiplexer with two 8 X 1 and one 2 X 1 multiplexers. Use block diagrams.

Problem 3:
Implement the following Boolean function with a 4 X 1 multiplexer and external gates.

𝐹2 (𝐴, 𝐵, 𝐶, 𝐷) = Σ (1,2,5,7,8,10,11,13,15)