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Sri Venkateshwara College of Engineering: Usn: 1 V E IA Test-I
Sri Venkateshwara College of Engineering: Usn: 1 V E IA Test-I
Sri Venkateshwara College of Engineering: Usn: 1 V E IA Test-I
Date 01/08/2016
Sri Venkateshwara College of Engineering
INTERNAL ASSESSMENT TEST QUESTION PAPER Rev No. 01
Page 1 of 1
USN: 1 V E
CBCS SCHEME 2017
IA Test- I
Term: April-2021 to August-2021
Programme: Electronics & Communication Engineering Semester& Section: 6 - ‘A’ & ‘B’
Course Title : VLSI Design Date: 25/05/2021
Course Code: 17EC63 Time: 9.15 AM to 10.45 AM
Duration: 90 Minutes Maximum Marks: 30
Instructions: Answer THREE full questions, choosing ONE full question from each part. Use A4
sheets only.
Kx,
SL.NO Question Marks
COx
PART – I (20 Marks)
K2, Explain with a neat diagram enhancement mode transistor action of nMOS
a) CO363.1 transistor. 10
1 K2,
b) CO363.1
Describe the fabrication steps for nMOS transistor using a neat diagram 10
OR
K3, Derive the expression for drain to source current of nMOSFET
a) CO363.1 10
2 K3, With a neat circuit and sketch explain CMOS inverter DC characteristics by
b) CO363.1 mentioning all the operating regions 10
TOTAL 60
Scrutinizer Signature