Zaman Dissertation Revised - Final Format Approved LW 7-31-2020

Approved and certified by L.
Wallace, University of Dayton, Graduate Academic Affairs
MODELING AND EXPERIMENTAL CHARACTERIZATION OF MEMRISTOR
DEVICES FOR NEUROMORPHIC COMPUTING
Dissertation
Submitted to
The School of Engineering of the
UNIVERSITY OF DAYTON
In Partial Fulfillment of the Requirements for
The Degree of
Doctor of Philosophy in Engineering
By
Ayesha Zaman, M.S.
UNIVERSITY OF DAYTON
Dayton, Ohio
August 2020
Name: Zaman, Ayesha

APPROVED BY:
Guru Subramanyam, Ph.D. Tarek M. Taha, Ph.D.

Advisory Committee Chairman Committee Member
Professor Professor
Electrical and Computer Engineering Electrical and Computer Engineering
Andrew Sarangan, Ph.D. Ahmed Ehteshamul Islam, Ph.D.

Committee Member Committee Member
Professor Air Force Research Laboratory
Electrical and Computer Engineering
Sabyasachi Ganguli, Ph.D.

Committee Member
Air Force Research Laboratory
Robert J. Wilkens, Ph.D., P. E. Eddy M. Rojas, Ph.D., M.A., P.E.

Associate Dean for Research and Innovation Dean, School of Engineering
Professor
School of Engineering
ii
© Copyright by
Ayesha Zaman
All rights reserved
2020
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ABSTRACT
Name: Zaman, Ayesha

University of Dayton
Advisor: Dr. Guru Subramanyam
This thesis presents systematic study on the fundamental understanding of an emerging
electronic device; memristor. First, different metal-switching layer-metal combinations were
examined to explore the most stable memristor characterization. Each device consisted of top and
bottom electrodes using reactive and inert metal contacts respectively. Next, charge transport
mechanisms through such devices were investigated. Bilayer lithium niobate based memristor
devices were fabricated and characterized as a model system for device physics study. This work
demonstrates analysis of simple, steady state current conduction process through bilayer lithium
niobate based memristor both for high and low resistance states. It is suggested when the device
is in a high resistance state, deep trap energy level within the memristor switching layer initiate
the device conductivity. The elastic trap assisted tunneling (ETAT) mechanism agrees with the
experimental measurements in the high resistive region. The ohmic conduction mechanism agrees
with the experimental measurements in the low resistive region for room temperature
measurements. Memristor conductivity at high resistance state was found insignificantly affected
with thermal variation and fits reasonably well for ETAT mechanism without taking the phonon
assisted effects into account. The low resistance state conductivity is suggested to be because of
space charge limited current (SCLC) conduction mechanism. Multiple memristor devices were
investigated to corroborate the applicability of the proposed charge transport mechanism using
theoretical framework and experimental validation. Lastly, several techniques are reported for
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characterizing stable, multiple or intermediate resistance states from different memristor device
combinations for neuromorphic computing applications.
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ACKNOWLEDGMENTS
First, I would like to Thank Almighty Allah for letting me through this journey of life . I
would like to express my deepest gratitude to my Advisor Prof Guru Subramanyam, and I truly
appreciate the degrees of freedom he offered on conducting my research. I would like to
acknowledge my other dissertation committee members : Prof Tarek Taha who is very kind and
willing to help when I meet problems. I am grateful to Prof. Andrew Sarangan for his valuable
suggestion and device fabrication support from his lab. I also want to thank Dr. Islam for his
constructive technical discussion on my research. I thank Dr. Ganguli for his support and for
providing me the opportunity to work as a summer intern at Airforce Research Laboratory last
year.
I am thankful to Prof. Weisong Wang and Dr. Eunsung Shin for their tremendous support
fabricating number of memristor wafers for our research lab. I would like to mention all my
friends from our Microwave Electronics Research Lab at University of Dayton including Prof.
Hailing Yue, Dr. Shu Wang, Dr. Kuanchang Pan, Dr. Urmila Nath, Liangyu Li, Kaushik Annam,
Malia Harvey, Jinchenn Zhao and Jinjing Li.
Last but not least, I owe to my family: my father Mr. A. B. M. Amanuzzaman, my mother
Mrs. Khaleda Zaman, my younger sisters Rakhi K. Zaman and Halima Zaman, my husband Dr.
Tanvir Atahary and my one and only son Aariz Tanvir. All of them have been my strongest
support.
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Dedicated to my parents my father Mr. A.B.M. Amanuzzaman and my mother Mrs. Khaleda
Zaman who never ceases to make me positive even at the hardest part of my life.
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TABLE OF CONTENTS
ABSTRACT …………………………………………………………………………………...………iv
ACKNOWLEDGMENTS...……………………………………………………………………...……vi
DEDICATION ……………….……………………………………………………………...………..vii
LIST OF FIGURES.………………………………………………………………………...……...….xi
LIST OF TABLES...………………………………………………………………………..………....xx
CHAPTER 1 INTRODUCTION .......................................................................................................... 1
1.1 Research Motivation ............................................................................................................. 1
1.2 Hysteretic Loop ..................................................................................................................... 3
1.3 Memristor as Emerging Non-volatile Memory Technology ................................................. 4
1.4 Biological Synapses and Memristors as Synapses ................................................................ 5
1.5 Research Objectives and Approach....................................................................................... 6
1.6 Organization of the Thesis .................................................................................................... 7
CHAPTER 2 FABRICATION OF DIFFERENT THIN FILM LAYERS ........................................... 9
2.1 Material Studies for Memristor Device ................................................................................. 9
2.2 Impact of Switching Layer .................................................................................................. 10
2.3 Process Flow for Memristor Fabrication ............................................................................. 12
2.4 Microscopic Images for Memristor ..................................................................................... 16
2.5 Summary of device Fabrication .......................................................................................... 16
CHAPTER 3 DEVICE CHARACTERIZATION ............................................................................... 17
3.1 Measurement Set Up ........................................................................................................... 17
3.2 Different MIM Structures ................................................................................................... 18
3.2.1 Characterization for different Oxide Based Memristors ................................................. 19
3.2.2 Characterization for Chalcogenide Based Memristors ................................................... 28
3.3 Stable Repetitive Characterizations from different MIM Structures ................................... 30
3.4 Detailed Research on Lithium Niobate Memristor Devices ................................................ 33
3.5 Characterization Based on Device Chemistry ..................................................................... 34
3.6 Repetitive Characterization Based on Device Area ............................................................ 36
3.7 Temperature Dependent Characterization ........................................................................... 37
3.8 Summary of Electrical Characterization ............................................................................. 40
CHAPTER 4 INVESTIGATION OF DOMINANT CHARGE TRANSPORT MECHANISM ........ 42
4.1 State of the Art-Charge Transport Mechanism through MIM Structure ............................. 42
4.2 Prior Physical Models for Memristor Conduction .............................................................. 46
4.3 Filamentary and Non-Filamentary Switching within MIM Structure ................................. 53
4.3.1 Filamentary Switching .................................................................................................... 53
4.3.2 Non-Filamentary Switching ............................................................................................ 53
4.4 Experimental Verification for Filamentary/Non-Filamentary Switching from Memristor
Device................................................................................................................................. 54
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4.4.1 Variation of Resistive States with Device Area .............................................................. 55
4.4.2 Variation of Programming voltage with oxide thickness ................................................ 57
4.4.3 Dispersion for Subsequent Switching ............................................................................. 58
4.5 Hypothesis for the Proposed Charge Transport Mechanism ............................................... 58
4.5.1 Investigation of Poole-Frenkel Emission for Memristor Off State ................................. 61
4.5.2 Investigation of Schottky Emission for Memristor Off State Conductivity .................... 63
4.5.3 Investigation of Elastic Trap Assisted Tunneling for Memristor Off State .................... 65
CHAPTER 5 VERIFICATION OF PROPOSED CONDUCTION MECHANISMS ........................ 70

5.1 HRS Simulation for Room Temperature Measurement ...................................................... 70
5.2 HRS Simulation for Elevated Temperature Measurements ................................................ 71
5.3 ETAT Simulation Results Up to Turn Over Voltage .......................................................... 73
5.4 LRS State for Variable Temperature ................................................................................... 74
5.5 LRS Simulation for Variable Temperature Measurements ................................................. 75
5.6 Experimental Results for Off State Conductivity using Pulse Measurement ...................... 78
5.7 ETAT Simulation Result for Multi level Conductivity along HRS .................................... 80
5.8 Validation of Charge Transport Mechanism using Experimental Results from Multiple
Devices ............................................................................................................................... 82
5.9 HRS Simulation Results from Multiple Devices................................................................. 83
5.10 LRS Simulation Results from Multiple Devices at Room Temperature ............................. 85
5.11 Validation of Fitting Parameters using Statistical Tools ..................................................... 87
5.11.1 Confidence Interval ........................................................................................................ 87
5.11.2 Calculation for Error Margin .......................................................................................... 88
5.11.3 Calculation for Critical Value ......................................................................................... 88
5.11.4 Calculation for Standard Error ........................................................................................ 88
5.11.5 R-Square ......................................................................................................................... 89
5.11.6 SSE ................................................................................................................................. 89
5.11.7 RMSE ............................................................................................................................. 89
5.12 Summary of device Simulation ........................................................................................... 90
CHAPTER 6 CHARACTERIZATION FOR NEUROMORPHIC ATTRIBUTES ........................... 91
6.1 Background ......................................................................................................................... 91
6.2 Performance Metrics for Neuromorphic Device ................................................................. 92
6.2.1 Device Dimension .......................................................................................................... 92
6.2.2 Ultra-low Power Consumption ....................................................................................... 92
6.2.3 Programming Time ......................................................................................................... 92
6.2.4 Repeatability ................................................................................................................... 93
6.2.5 Analog Resistive Switching ............................................................................................ 93
6.2.6 Endurance and Retention ................................................................................................ 93
6.3 Techniques for Determining Multi-Level Resistive Switching ........................................... 93
6.3.1 Incremental Bias Dependent MRS.................................................................................. 94
6.3.2 Repetitive Sweep Bias dependent MRS ......................................................................... 96
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6.3.3 Compliance Current dependent MRS ............................................................................. 98
6.3.4 Set/Reset Voltage Dependent MRS ................................................................................ 99
6.3.5 Temperature dependent MRS ....................................................................................... 104
6.3.6 Pulse Measurement for MRS ........................................................................................ 105
6.3.7 Alternate Representation of Multiple Resistive States.................................................. 108
6.4 Summary of Memristor as Synthetic Synapse................................................................... 109
CHAPTER 7 CONCLUSION AND OUTLOOK ............................................................................. 110
7.1 Summary of Research Contribution .................................................................................. 110
7.2 Future Work ...................................................................................................................... 111
REFERENCES ................................................................................................................................... 113
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LIST OF FIGURES
Figure 1.1. Fundamental relations of the four physical variables utilized for electrical characterization
for a solid-state device: voltage (v), current (i), charge (q) and flux (ϕ), linked by four circuit
elements: resistor (R), capacitor (C), inductor (L), and memristor (M). ........................................3
Figure 1.2. Pinched hysteresis loop for a typical memristor device. Increase of sweeping frequency
causes the loop area to shrink. ........................................................................................................3
Figure 1.3. Resistive Switching types (a) Unipolar (b) Bipolar switching Reprinted with permission
from [88] Resistive Switching memory for Non-Volatile storage and neuromorphic
computing by Shimeng Yu, July, 2013 retrieved from http://purl.stanford.edu/xh257vm1382
Copy right (2013) Stanford University. .........................................................................................5
Figure 1.4. Analogy between the biological synapse and oxide based synthetic synaptic device[76] ............6
Figure 2.1. Pictorial representation of thin film layers for oxide based Memristor Device .......................... 10
Figure 2.2. Pictorial representation of deposition Steps for oxide based Memristor Device :1. Substrate
cleaning 2. Dehydration bake 3. Photoresist coating 4. Pre-exposure bake 5. UV exposure 6.
Photoresist developing 7. O2 asher treatment 8. Metallization 9. Lift-off & cleaning 10. O2
asher treatment 11. Deposition of switching layer (Sputtering for TiOx /TiO2 , PLD for
LiNbO3-x / LiNbO3 , VO2 , TaO2 , ALD for HfO2 , SiO2 , Al2O3 12. Photoresist coating , 13.
Pre-exposer bake , 14. UV Exposure , 15. Photo resist develop , 16. O2 asher treatment, 17.
Dry etch 18. Photo resist remove , 19. O2 asher treatment , 20. Photo resist coating , 21. Pre
exposer bake, 22. UV Exposure 23. Photo resist developing , 24. O2 asher treatment , 25.
Metallization 26. Lift off and cleaning ......................................................................................... 14
Figure 2.3. Pictorial representation of deposition Steps for chalcogenide (GeTe/GST) based Memristor
Device .......................................................................................................................................... 15
Figure 2.4. Microscopic Image for (a) Single Memristor device (b) Memristor (4x4) Crossbar structure ... 16
Figure 3.1. Keithley 2400 Source Meter Unit (SMU), Jmicro Technology LMS-2709 microscope, S-725
micro positioner and LMS-91A thermal module system ............................................................. 17
Figure 3.2. MELCOR MTTC 1410 temperature controller and Thermaltake coolant flow control system.. 17
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Figure 3.3. Plot for triangular sweep input bias applied to the memristor device ......................................... 18
Figure 3.4. Bilayer Titanium Oxide based Memristor Device (a) cross sectional view, electrical
characterization demonstrating variation of device (b)current with applied bias (c) current
density with electric field ............................................................................................................. 20
Figure 3.5. Lithium Niobate Oxide based Memristor Device with dissimilar electrode combination
along memristor top and bottom (a) cross sectional view, electrical characterization
demonstrating variation of device (b) current with applied bias (c)current density with
electric field.................................................................................................................................. 21
Figure 3.6. Bilayer Lithium Niobate Oxide based Memristor Device with identical electrode
combination along memristor top and bottom (a) cross sectional view, electrical
characterization demonstrating device (b) current with applied bias (c) current density with
electric field.................................................................................................................................. 22
Figure 3.7. Hafnium Oxide based Memristor Device having (Ni/Pt) interface layer at the bottom
electrode(a) cross sectional view, electrical characterization demonstrating variation of
device (b) Current density with Electric field (c) plot for variation of current density with
electric field.................................................................................................................................. 23
Figure 3.8. Signature characteristics of Memristor device having SiO2 as the switching layer (a) Cross-
sectional view of SiO2 based Memristor device having 12.50 µm2 as the overlapped area (b)
variation of device (b) current with applied bias (c) current density with electric field. .............. 24
Figure 3.9. Demonstration of Al2O3 based Memristor device (a) cross sectional view of MIM structure,
electrical characterization demonstrating variation of device (b) &(d) current with applied
bias (showing abrupt and gradual modulation respectively) (c) & (e) current density with
electric field (showing digital and analog resistive transition respectively) ................................. 26
Figure 3.10. Vanadium Oxide based Memristor Device with Identical conducting layer combination as
memristor top and bottom electrodes (a) cross sectional view, electrical characterization
demonstrating variation of device (b) current with applied bias (c) current density with
electric field.................................................................................................................................. 27
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Figure 3.11. Tantalum Oxide based Memristor Device with Identical electrode combination along
memristor top and bottom (a) cross sectional view, electrical characterization demonstrating
variation of device (b) current with applied bias (c) current density with electric field ............... 28
Figure 3.12. Germanium Antimony Telluride (GST)based Memristor Device with Identical electrode
characterization demonstrating variation of (b) device current with applied bias (c) current
density with electric field ............................................................................................................. 29
Figure 3.13. Germanium Telluride (GeTe) based Memristor Device with identical electrode
characterization demonstrating variation of (b) device current with applied bias (c) current
density with electric field. ............................................................................................................ 30
Figure 3.14. Electrical characterization (using 50 consecutive sweep bias) for determining intra device
variability from a bilayer lithium niobate based memristor device with 7.50 µm2 overlap area .. 31
variability from a GST based memristor device with 7.50 µm2 overlap area .............................. 32
variability from a GeTe based memristor device with 7.50 µm2 overlap area ............................. 32
variability from a GeTe based memristor device with 7.50 µm2 overlap area ............................. 33
Figure 3.18. Cross sections of the six different device structures studied. The switching layer of each
device (bottom to top) was constructed as follows: (a) LiNbOx (b) LiNbOy (c) Al2O3 /
LiNbOx (d) LiNbO3 / LiNbOx (e) LiNbOx /LiNbO3 and (f) an alternative composition of
LiNbOx/LiNbO3 ........................................................................................................................... 35
Figure 3.19. Repetitive Sweep dependent Current Voltage Characterization at room temperature from
Memristor device varying proportion of Lithium niobate within switching layer (a) to (f) to
investigate best possible MIM combination for stable hysteresis ................................................ 36
Figure 3.20. Repetitive electrical characterization from bilayer lithium niobate based memristor device
varying overlap area size (a) to (d)............................................................................................... 37
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Figure 3.21. Electrical characterization of bilayer lithium niobate based memristor device with variable
temperatures (a) room temperature 25oC (b) 35oC (c) 45oC (d) 55oC (e) 65oC (f) 75oC (g)
85oC (h) 95oC ............................................................................................................................... 38
Figure 3.22. Variation of Memristor resistance states (both HRS and LRS) with temperature..................... 39
Figure 4.1. Diagram demonstrating Typical Current Conduction Processes through MIM Structure .......... 42
Figure 4.2. Typical charge transport mechanisms through MIM structure (a) Direct Tunneling (b)
Fowler-Nordheim Tunneling (c) Ohmic Conduction (d) Poole-Frenkel (P-F) Emission (e)
Schottky Emission ........................................................................................................................ 43
Figure 4.3. HP Lab fabricated Memristor device (a) Pt/TiO2 /TiO2-x /Pt structure (b) Proposed
Mechanism for resistivity change................................................................................................. 47
Figure 4.4. Demonstration of manganese doped bilayer titanium oxide based memristor device (a)
cross sectional view (b) plot for memristor off state currents in both polarity cases ................... 48
Figure 4.5. Electrical characterization for Hafnium Oxide based Non-Volatile memory device or
Resistive RAM (RRAM) (Fabricated by Stanford University Research group). Inset shows
sandwiched structure for the RRAM ............................................................................................ 49
Figure 4.6. Simulation for Elastic Trap Assisted Tunneling at High Resistive State (HRS) from
Hafnium oxide-based RRAM device ........................................................................................... 49
Figure 4.7. University of Michigan fabricated Memristor device (a) Pd/Ta2O5 /TaOx /Pd structure (b)
Ionic Transport Mechanism for Memristor conductivity change ................................................. 50
Figure 4.8. Variation of (a) memristor high resistance states and (b) resistance ratio (𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅) with
different overlap areas .................................................................................................................. 56
Figure 4.9. Plot for memristor electrical characterization and evolution of programming voltage with
oxide thickness (a) memristor I-V with thickness 42 nm (b) 29 nm (c) strong dependence of
programming voltage upon switching layer thickness ................................................................. 57
Figure 4.10. Energy Band diagram for bilayer Lithium niobate based Memristor device at Flat band
condition....................................................................................................................................... 59
Figure 4.11. Standard Logarithmic plot for Conductivity modulation as per Poole Frenkel emission
mechanism ................................................................................................................................... 61
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Figure 4.12. Verification of Poole Frenkel emission for Memristor high resistive state (HRS) (a)
logarithmic plot for memristor conductivity with square root of applied bias (b) conductivity
modulation for low bias state with temperature variations (c) plot for electron activation
energy with bias voltage. Y- intercept for the plot provides extracted deep trap energy level
assumed to be responsible for P-F emission during HRS ............................................................ 63
Figure 4.13. Fitting results for Schottky emission for bilayer lithium niobate based memristor device (a)
logarithmic plot for HRS current with variation of temperature (b) logarithmic plot for off
state current with variation of electric field (c) extraction of Schottky barrier height as per
definition mentioned in eqn. 3...................................................................................................... 64
Figure 4.14. Modulation of memristor energy band diagram under external bias condition, supporting
two step ETAT mechanism. ......................................................................................................... 66
Figure 4.15. Modulation of memristor energy band-diagram due to Ohmic Conduction ............................. 68
Figure 5.1. ETAT Simulation results for memristor high resistive state both for positive and negative
polarity. Experimental values are showed using the dotted points and simulated values are
mentioned with line within the plot.............................................................................................. 71
Figure 5.2. ETAT simulation results for memristor HRS at 65oC for (a) positive and(b) negative bias
measurements respectively........................................................................................................... 71
Figure 5.3. ETAT simulation results for memristor HRS at 95o C for (a) positive and(b) negative bias
measurements respectively........................................................................................................... 72
Figure 5.4. Combined plot for ETAT simulation for lithium niobite based memristor during device off
state maintaining (a) room temperature 25oC (b) 95oC compared with experimental results
(all dotted points correspond to measured values and line drawn correspond to the simulated
values within the plot) .................................................................................................................. 72
Figure 5.5. Plot for Electron Activation energy with variation of electric field ............................................ 73
Figure 5.6. Simulation results for memristor HRS up to Turn over voltage using ETAT process for (a)
Positive (b) Negative polarity bias ............................................................................................... 74
Figure 5.7. Plot for current voltage change for memristor low resistive state only ....................................... 75
xv
Figure 5.8. Simulation results using Ohmic conduction for Memristor device at highly conductive state
for (a) room temperature (b) 95oC compared with experimental results (all dotted points
correspond to measured values and line drawn correspond to the simulated values within the
plot) .............................................................................................................................................. 76
Figure 5.9. SCLC simulation result for memristor LRS conductivity at high bias , high temperature; linear
change of device current with applied bias (all black dotted points correspond to the
experimental on state current and the red line drawn indicates simulation result using SCLC
process .......................................................................................................................................... 77
Figure 5.10. Experimental condition applied for analog programmability from memristor device .............. 79
Figure 5.11. Evidence of Analog Switching from proposed bilayer lithium niobate based memristor
having overlap area of (7.50 µm2) (a) dc characterization from memristor device at room
temperature (b) precise analog control (gradual resistive switching) achieved from memristor
device suggesting analogy with potentiation (increase of resistance states) and depression
(decrease of resistance states) phenomena within human brain. .................................................. 80
Figure 5.12. Potentiation and depression phenomena simulated with the variation of trap distance d'
from 7.78nm to 4.45nm: ETAT simulation result applying identical pulse response for multi-
level resistive switching from memristor device at room temperature......................................... 81
Figure 5.13. Simulation of charge transport process from a 5 μm2 Memristor device at room
temperature (a) plot for current-voltage characterization (b) ETAT simulation result for HRS
(c) simulation for Ohmic conduction along LRS ......................................................................... 82
Figure 5.14. Simulation of charge transport process from a 2.5 μm2 Memristor device at room
temperature (a) plot for current-voltage characterization (b) ETAT simulation result for HRS
(c) simulation for Ohmic conduction along LRS ......................................................................... 82
Figure 5.15. Electrical Characterization from Multiple Memristor Devices (a) through (f) maintaining
room temperature and similar experimental condition ................................................................. 83
Figure 5.16. Simulation results for Elastic Trap Assisted Tunneling mechanism for the HRS region of
bilayer lithium niobate based memristor device (a) to (f). Here simulation has been done for
xvi
six different memristor devices of the same MIM structure where the same experimental
condition has been maintained ..................................................................................................... 84
Figure 5.17. Simulation for Memristor LRS or on state using the Ohmic Conduction process. Here
simulation has been shown for three more memristor devices collecting measured data at
room temperature (a), (b) and (c) simulation for three more different devices .......................... 86
Figure 6.1. Incremental bias dependent multilevel resistive switching from a bilayer titanium oxide
based memristor device (a)hysteresis with sweep bias V1= 5.60 V(b) hysteresis with sweep
bias V2= 7.0 V (c) combined plot demonstrating formation of intermediate resistive states
due to the use of incremental sweep bias along the memristor device ......................................... 95
Figure 6.2. (a) Logarithmic plot for twenty repeatable current-voltage characterization (b) linear plot for
stable, repeatable, intermediate resistive state at 0.8 0 V (c) combined plot for HRS, IRS and
LRS from a 20 μm2, memristor device where GST is the switching layer................................... 95
Figure 6.3. Analog modulation of resistivity from a hafnium oxide based memristor device (a) Plot for
increase (Potentiation) (b) decrease (Depression) of resistive states due to application of
repetitive bias (reset and set respectively) .................................................................................... 96
Figure 6.4. Repetitive Sweep voltage dependent Multi level resistive switching from a GeTe memristor
having overlap area (a) 5 µm2 and (b) 20 µm2 respectively .......................................................... 97
Figure 6.5. Illustration of memristor (GeTe) resistivity modulation with sequential sweep bias (a) result
from device (a) 5 µm2 and (b) 20 µm2 respectively .................................................................... 97
Figure 6.6. Compliance Current dependent multi level resistive switching from a bilayer lithium niobate
based memristor device while keeping the sweep bias always the same. .................................... 98
Figure 6.7. Compliance current dependent multi level resistive switching from a GeTe based memristor
device (a) Formation of four (4) Intermediate resistive states in between memristor off and
on states (b) plot for variation of HRS and LRS with that of three different compliance
current levels. ............................................................................................................................... 99
Figure 6.8. Compliance current dependent multi level resistive switching from a GST based memristor
device (a) Formation of ten (10) Intermediate resistive states in between memristor off and
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on states (b) plot for variation of HRS and LRS with that of six (6) different compliance
current levels. ............................................................................................................................... 99
Figure 6.9. Repetitive Set voltage dependent multiple resistive states from a memristor device having
area 5 µm2 where GST is the switching layer (a) formation of four intermediate resistive
states in between memristor off and on states due to the repetitive set bias along positive
polarity (b) Reset bias dependent MRS from a GeTe memristor having area 20 µm2 while
keeping the set bias the same ..................................................................................................... 100
Figure 6.10. Reset voltage dependent multiple resistive switching states from a GST based having
overlapped area of 7.50 µm2. ..................................................................................................... 101
overlapped area of 15.0 µm2 (a) formation of stable hysteresis loops with repetitive reset bias
showing distinct resistive levels along the negative polarity (b) variation of HRS and LRS
along the reset area ..................................................................................................................... 102
Figure 6.12. Reset Transition for multi level states (b) Modulation of HRS and LRS along negative
polarity ....................................................................................................................................... 103
Figure 6.13. Characterization for Reset voltage dependent Multiple resistive states from a memristor
device with TaO2 as the switching layer (a) modulation of conductivity from fourteen
intermediate states demonstrating repetitive reset bias dependent MLS (b) change of HRS
and LRS with repetitive reset bias along the negative polarity .................................................. 103
Figure 6.14. Logarithmic plot for modulation of memristor’s current voltage characterization with
variation of temperature (b) Modulation of resistance levels (both HRS and LRS) with
varying temperature ................................................................................................................... 104
Figure 6.15. Experimental condition applied for investigating Potentiation and Depression phenomena
from a bilayer lithium niobate based memristor device using 17ms pulse as the external
stimuli......................................................................................................................................... 106
Figure 6.16. Characterization as Synthetic synapse from a bilayer lithium niobate memristor device (a)
current voltage characterization from a 7.50 µm2 memristor device at room temperature (b)
modulation of device conductivity for memristor off state ........................................................ 106
xviii
current voltage characterization from a 2.5 µm2 memristor device at room temperature (b)
modulation of memristor off state current .................................................................................. 106
Figure 6.18. Gradual conductivity modulation from a GST based memristor device using 17ms pulse
measurement .............................................................................................................................. 107
Figure 6.19. Formation of three Intermediate resistive states in between memristor off and on states
where GST is the switching layer (a) from device with overlapped area 5 µm2 (b) 15 µm2 ...... 108
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LIST OF TABLES
Table 2.1 : Tabular representation of high k dielectrics utilized for fabricated Memristor devices @
University of Dayton [56] ............................................................................................................ 12
Table 3.1: Tabular representation for electrical characterization results from various MIM structures or
Memristor combinations .............................................................................................................. 41
Table 4.1: Tabular representation of previous literature review on memristor conductivity........................ 52
Table 4.2: Variation of device attributes for Filamentary and Non-Filamentary Resistive Switching .......... 54
Table 4.3: Summary of Suitability of Dominant Charge Transport Mechanism through Memristor
Device .......................................................................................................................................... 69
Table 5.1 : Tabular representation of fitting parameters for a bilayer lithium niobate based memristor
device ........................................................................................................................................... 78
Table 5.2: Tabular representation of fitting parameters using SCLC mechanism ......................................... 78
Table 5.3 : Tabular representation of Trap Energy level and trap distance values from Seven Different
Memristor devices at HRS maintaining room temperature are populated here. ........................... 85
Table 5.4: Tabular representation of fitted parameter from simulation for Ohmic conduction ..................... 87
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CHAPTER 1
INTRODUCTION
1.1 Research Motivation
Emergence of “Big Data” era is the driving force for downscaling of CMOS technology [1].
Current non-volatile flash memory has already encountered various technical challenges to keep
Moore’s law [2] alive within the existing Von-Neumann computer architecture [3]. First,
minimization of device structure reduces space between floating gates of two adjacent cells
existing in CMOS technology. This would cause floating of charges in one gate to the adjacent
cell with an undesired shift in threshold voltage leading to a read error [4]. Secondly reduction of
oxide thickness worsens the charge transport due to leakage current in the off-state condition.
Such variability with the threshold voltage would introduce unreliable stochastic operation within
the program, erase and retention capability of the flash device [5]. Such issues related to the flash
memory scaling need to be addressed with an alternating emerging memory device. Also, current
memory devices require either lower latency or higher capacity to support high computing
throughput maintaining the demand for low power applications. Studies in this area have widely
progressed within the last decade in terms of device size, power consumption, data retention, and
endurance [6]. In practice, it is hard for the conventional Von–Neumann computer architecture to
satisfy the memory requirement with device scaling. It is expected that a non-Von Neumann
architecture [7] with an alternate memory device other than the current CMOS technology can be
a viable solution in this regard. Since more than four decades’, research with resistive random-
access memory (RRAM) has emerged as a leading candidate for future non-volatile memory [8],
[9], [10]. Memristor is a class of such RRAM group devices. The term “Memristor” was first
postulated by the great mathematician Prof. Leon Chua back in 1971[11]. Three well known
fundamental electrical circuit elements (resistor, capacitor and inductor) are related with the
1
physical variables as shown using the diagram in fig 1. Keen observation of Dr. Chua led to the
argument that there should be a fourth fundamental electrical circuit element connecting the
missing link between the charge and the flux to comprehend the relationships between the four
physical variables (voltage, flux, current and charge). This element is suggested to behave as a
nonlinear two terminal resistors with memory capability. Hence, he named this as ‘Memristor’ or
‘memory resistor’. This was claimed to be the fourth fundamental electrical circuit element by
Prof. Leon Chua [12]. Non-linear behavior from this new element was claimed to be completely
unique with bow-tie shape within the current voltage characterization. His proposition was
physically realized in 2008 by a research group from Hewlett Packard (HP) Labs under Dr. Stan
Williams [13]. Signature characteristics from memristor device is a zero-crossing pinched
hysteresis loop [14] supporting the claim by Prof Chua. Such response indicates that memristor
does not store energy as capacitors and inductors, but it has a memory effect. Like other three
elements memristor is also a passive element. State of a regular resistor is determined directly
using the instantaneous input (voltage or current) and sometimes one or a set of internal state
variables. Equation below shows such relation for conductivity measurement for a
standard/regular resistor. Here (i, v) represent instantaneous input and ‘w’ is the internal state
variable [15].
𝑖𝑖 = 𝐺𝐺(𝑤𝑤, 𝑣𝑣)𝑣𝑣 (1.1)
On the other hand, in case of memristor device, rate of change of state variable is considered
as device input. This has been depicted in the rate equation as follows
𝑑𝑑𝑑𝑑
= 𝑓𝑓(𝑤𝑤, 𝑣𝑣) (1.2)
𝑑𝑑𝑑𝑑
2
𝑑𝑑𝑣𝑣
R= 𝑑𝑑𝑓𝑓
v i
L=
𝑑𝑑𝑞𝑞
𝑑𝑑𝑣𝑣
C=
𝑑𝑑∅
𝑑𝑑𝑓𝑓
q φ
𝑑𝑑∅
M= 𝑑𝑑𝑑𝑑
Figure 1.1. Fundamental relations of the four physical variables utilized for electrical characterization for a
solid-state device: voltage (v), current (i), charge (q) and flux (ϕ), linked by four circuit elements: resistor
(R), capacitor (C), inductor (L), and memristor (M).
1.2 Hysteretic Loop
The response of a memristor device to a periodic stimulus is a pinched hysteresis loop.
Such signature characteristics indicate memristors do have memory effect. At very high
frequencies 10 𝜔𝜔𝑜𝑜 , a memristive system resembles as a linear resistor while for low frequency
stimulus, it operates as a nonlinear device [16]. Figure 1.2. shows typical bowtie shaped signature
characteristics from a memristor device.
Figure 1.2. Pinched hysteresis loop for a typical memristor device. Increase of sweeping frequency causes
the loop area to shrink.
3
1.3 Memristor as Emerging Non-volatile Memory Technology
Conventional memory technologies (SRAM, DRAM, FLASH) are facing scaling
limitation beyond 10 nm technology node [17]. New computing paradigms need to be considered
to further improve computing system performance. Emerging memory technologies may bring
enormous opportunities to combat with the formidable device scaling challenges [18]. Among
various emerging memory technologies, ‘Memristor’ is attractive due to its simple structure and
great compatibility with current CMOS technology. Primary target for the development of
resistive random-access memory (RRAM) is to replace the flash memory. Resistive switching is
the change of resistance state within a solid-state nanostructured device. Change of device state
from high resistive to low resistive states is called SET. The opposite process is named as RESET
[19]. RRAM or Memristor consists of a switching layer sandwiched in between two conducting
layers. Among various types of switching layers researched in works [20],[21], [22],[23], oxide
and chalcogenide based sandwiched structured memristor devices are reported in this dissertation.
Switching mode is not an intrinsic property of the thin film deposited as switching layer itself.
Rather it is the property of both the material used for the switching layer and the interface
between the electrode and the switching layer. At pristine state, voltage required to turn on the
device is higher than the SET voltage. This is called the forming voltage [24]. Depending upon
the electrical polarity required, switching modes are of two types. In case of unipolar switching,
switching direction depends upon the amplitude of the applied voltage and not the polarity of the
bias. It is also called non-polar switching mode of operation. Bipolar switching means, switching
direction depends upon the polarity of the applied voltage. This means SET and RESET occur at
opposite polarity biases [25]. A compliance current (CC) is recommended to protect device from
permanent dielectric break down. Figure 1.3 shows plot for both type of switching modes.
4
Figure 1.3. Resistive Switching types (a) Unipolar (b) Bipolar switching Reprinted with permission from
[88] Resistive Switching memory for Non-Volatile storage and neuromorphic computing by Shimeng Yu,
July, 2013 retrieved from http://purl.stanford.edu/xh257vm1382 Copy right (2013) Stanford University.
1.4 Biological Synapses and Memristors as Synapses
Potential implementation of memristor device for neuromorphic architecture need to be
explored more. Neural network comprises of neurons connected through the synapses. Human
brain contains ~1010 neurons connected with each other. Each neuron is connected through ~1014
synapses in human brain [26]. Fundamental attribute of biological brain’s compute capability is,
the ‘synaptic plasticity’. Synaptic weight is the amount of influence the firing from one neuron
has upon the neighboring neuron which are connected through synapses [27]. The phenomena
related to the modulation of synaptic weight is named as synaptic plasticity. Amplitude or amount
of synaptic weight controls signal transmission to the neurons. In short, synaptic plasticity
ensures learning capability with high scale connectivity to provide parallel processing capability.
This learning capability is essential for building artificial cognitive systems. Within a biological
synapse, Spike Timing Dependent Plasticity (STDP) is mainly an asynchronous process [28].
STDP is the ability of synapses to change their strength according to the pre and post synaptic
spikes. Several research groups [29],[30],[31] have demonstrated fundamental synaptic learning
functions using memristor as the synthetic, synapse. Figure 1.4. demonstrates analogy between
biological synapse and two terminal memristor as the oxide synaptic device. Overlapped area
5
between electrodes and oxide layer acts as the memristor active region which can be
characterized to emulate biological synaptic conductivity [32].
Figure 1.4. Analogy between the biological synapse and oxide based synthetic synaptic device[76]
1.5 Research Objectives and Approach
Principle objective of this research is to characterize memristor devices with various
three-layered combinations which is expected to offer not only binary states but also can be
utilized as multilevel storage element. In keeping Moore’s Law alive, present-day research
considers this ReRAM or Memristor as the most valuable candidate. Knowledge of electrical
characterizations and conduction properties through memristor is very useful in optimizing the
devices for various applications mostly for neuromorphic architecture [33],[34]. In this regard,
research work presented here is divided into three parts. First task is to show dc characterization
from various Metal-Insulator-Metal (MIM) combinations. Task two depicts a methodology for
approximating charge transport mechanism through an oxide based memristor device. Finally,
task three would combine experimental results from memristors demonstrating multi-level
resistive switching; an important criterion for neuro-morphic device.
6
Core contributions of our research comprises of LiNbO3/LiNbO3-x based memristor
fabrication, characterization, analysis of dominant current conduction mechanism, and
implementation of multi-level resistance states. Forming-free current voltage
characterization is necessary to utilize memristor device to emulate human brain utilizing
memristor devices as synthetic synapses in neuromorphic architecture. Although the
LiNbO3/LiNbO3-x based memristors showed very low Roff/Ron ratio, forming-free I-V
characteristics, the low SET/RESET voltages, and the ability to control the intermediate
resistance states are attractive for neuromorphic computing.
A simple steady state analytical model for charge transport mechanism has been
developed explaining the effect of defects/traps within memristor switching layer
responsible for device conductivity. Elastic Trap Assisted Tunneling due to a deep trap
energy level dominates memristor high resistance state conductivity. Existence of
unfilled shallow trap energy level promotes memristor low resistance conductivity.
Unlike different memristor devices reported so far, the lithium niobate based memristor
device has low resistance ratio, but it can still show multiple intermediate resistance
states in the high resistance region.
1.6 Organization of the Thesis
Introductory chapter one provides an overview of technical challenges faced by the
existing CMOS technology with the ever-increasing need of high capacity and low-cost data
storage. Non-transistor structures named as ‘Memristor’ has been extensively studied as an
alternative memory approach. Chapter two gives detailed explanation of the thin film layers
utilized for different memristor device combinations projected for our research work. This
chapter includes stepwise process flow both for oxide and chalcogenide based memristor devices.
7
Chapter three illustrates dc electrical characterization results from the different memristor
devices. Apart from variation within thin film composition, this report studies existence of
significant modulation of device characterizations with memristor overlap areas, thermal
variation and cycle to cycle variation. In chapter four we report charge transport process for
metal-insulator-metal devices. This chapter presents different literature review for the physical
model comprising current conduction mechanism through memristor devices of different
structures and combinations. After investigating different standard conduction mechanisms, the
most dominant process has been hypothesized for a bilayer lithium niobate based memristor
device. Chapter five illustrates verification of the proposed charge transport process using
MATLAB simulation results. Fitting parameters have been extracted simulating electrical
characterization results from multiple memristor devices. Each result was validated using
standard statistical approach. Chapter six includes characterization results using different
techniques for investigating multiple resistive states from memristors. Existence of intermediate
resistance states signifies gradual or analog switching capability from the device. The last chapter
(chapter seven) provides summary of the research conducted on memristor devices. It also briefs
future work related to the current research.
8
CHAPTER 2
FABRICATION OF DIFFERENT THIN FILM LAYERS
2.1 Material Studies for Memristor Device
Typically, three different thin film layers are required for an MIM structure; top and
bottom metal electrodes and a switching layer sandwiched in between. Figure 2.1. shows
sandwiched memristor structure with cross sectional and top view. Overlap area between
conducting layer and the switching layer acts as the active cell for a memristor device. Several
materials have been used for the memristor device fabrication both as electrodes and storage
materials [35],[36],[37],[38],[39]. According to the literature review [40-44], so far utilized
materials as memristor thin film layers from periodic table are mentioned below.
Electrode/Metal : Magnesium(Mg), Aluminum (Al), Titanium (Ti), Chromium (Cr), Manganese
(Mn), Ferrum (Fe) , Cobalt (Co), Nickel (Ni), Copper (Cu), Zinc (Zn) , Germanium (Ge) ,
Yttrium(Y), Zirconium (Zr), Niobium (Nb) , Molybdenum (Mo), Stannum (Sn), Lanthenum (La),
Hafnium(Hf), Tantalum(Ta), Tungsten (W), Cerium (Ce), Gadolinium(Gd), Ytterbium (Yb),
Lutetium(Lu).
Oxides to the Relevant Metal: Aluminum (Al), Titanium (Ti), Nickel (Ni), Copper (Cu),
Rutherfordium (Ru), Argentum (Ag), Tungsten (W), Iridium (Ir), Platinum (Pt), Aurum (Au). In
order to assess an MIM structure for use as a memristor, relevant electronic properties need to be
well understood. First task of this project is to study signature characteristics of memristors with
different transition metal oxides [45], [46] and chalcogenides [47]. MIM stack combination must
be selected in a way that would produce the most desirable and stable hysteresis. While choosing
the materials for memristor fabrication, low power consumption from ultra-small device structure
must be ensured as the first criteria.
9
Figure 2.1. Pictorial representation of thin film layers for oxide based Memristor Device
This dissertation work presents characterization of memristor devices with using
Platinum (Pt), Gold (Au), Silver (Ag) and Nickel (Ni) as metal electrodes. In most cases use of
same noble metal both as top and bottom electrodes exhibits unipolar switching from memristor
device [48]. On the other hand, use of oxidizable material as one of the electrodes results in
bipolar switching mode. When both the electrodes are chosen oxidizable to achieve bipolar
switching, care needs to be taken to maintain significant asymmetry in the oxygen gettering
capability [49]. In our case, while depositing the conducting layer, metals were chosen in a way
to have a combination of one electrochemically inert and one active electrode. A thin layer of
Titanium (Ti) is added to promote adhesion.
2.2 Impact of Switching Layer
Since late 1990’s high –k materials have been investigated to identify the dielectric thin film
which could potentially replace SiO2. Such high k materials are evaluated depending upon the
values of dielectric constant, thermal and chemical stability in contact with Si and band offsets
with Si [50]. A switching material having a higher dielectric constant, and a larger energy band
gap are desirable for the potential candidates. Thermal stability in contact with Si is a critical
issue. Fabrication of MIM stack requires the annealing of the (oxide/Si) structure to a high
temperature in the range of (T>1000oC). This is because, at very high temperature the intermixing
10
of metal and Si might severely compromise the device functionality. As per ITRS, band offsets
between a high k dielectric and Si should be at least 1eV, which would restrain memristor off
state current at a higher level [51]. Requirements mentioned below need to be considered while
choosing a new oxide as a replacement for typically used SiO2 for CMOS technology [52].
I. Oxide should be chosen in a way that it has high enough ‘k’ to be used with couple of
years of scaling. Value of ‘k’ is preferable between 10 to 30. But there should always be
an optimization so that energy bandgap value is good enough (~4 eV). This is because
high k values vary inversely with oxide bandgap [53].
II. The oxide must be thermodynamically stable as it is in direct contact with Si substrate.
III. Kinetic stability and compatibility with processing up to 1000oC must be maintained.
IV. Oxide band offset with Si (substrate) needs to be at least 1 eV so that it can minimize
carrier injection into its band.
V. Projected oxide should form good electrical interface with Si. Interface should ensure
highest quality in terms of roughness and interface defects to consider a high k dielectric
as the SiO2 replacement [54].
VI. This report illustrates use of titanium oxide, lithium niobate, hafnium oxide, aluminum
oxide, silicon di oxide, tantalum oxide, vanadium oxide, germanium telluride and
germanium antimony telluride as switching layer for different memristor devices. Based
upon electrical bias-based conductivity modulation, memristor devices studied for this
research can be divided into two types [55]
 Oxide Memristor: Mostly transition metal oxides having higher dielectric constant compared
to the silicon di oxide is chosen for the memristor switching layer.
 Phase Change Memristors: Such memristors utilize phase change materials as the switching
layer in between two metal electrodes. Application of electric stimuli/bias causes the phase
11
change materials switch from amorphous (high resistive state) to polycrystalline (low
resistive state).
Table 2.1 : Tabular representation of high k dielectrics utilized for fabricated Memristor devices @
University of Dayton [56]
Material used as
Dielectric Constant (Fm-1) Band Gap (eV)
Switching Layer
TiO2 50-80 3.0
LiNbO3 28-86 4.0
HfO2 15-26 5.3
Ta2O5 25-26 3.8
Al2O3 9-11 6.7
VO2 11.5-22.3 5.05
SiO2 5-10 8.76
GST 15-16 0.70
GeTe 36-37.5 0.50
2.3 Process Flow for Memristor Fabrication
Memristor devices have been fabricated at the Airforce Research Laboratory (AFRL)
Sensors Directorate (RY) cleanroom, with support from AFRL RX, the Materials Directorate, and
the Center of Excellence for Thin-film Research and Surface Engineering (CETRASE) at the
University of Dayton. Fabrication of memristor devices consists of deposition of thin film
switching layer sandwiched in between two conducting layers. Photolithography mask has been
designed using AWR simulator [57]. Both the electrode layers are being deposited using
Electron-beam evaporation process [58]. RF Sputtering [59], Pulsed Laser Deposition (PLD)
[60], Atomic Layer Deposition (ALD) [61] has been chosen for different switching layer
deposition depending upon the availability of the fabrication facility. The procedure begins with
surface degreasing of a fresh 400 µm thick, 2-inch diameter, and 2 µm thick SiO2 coated Si wafer
12
by using cleaning step. The cleaning step is performed at 500 RPM, and it consists of Acetone
gun spray, Acetone bottle spray, Isopropanol bottle spray, and N2 blow drying for 15 seconds
each. After that, dehydration bake process is conducted at 110°C for 75 seconds. The spinning
duration and the ramping speed of this process are set to 30 seconds and 400 RPM. Next process
is SF-11 bake of the wafer at 250°C for 120 seconds. After the SF-11 bake process, a layer of
photoresist S1813 is coated on the wafer at 4000 RPM. The spinning duration and the ramping
speed are same with the SF-11 process. Then, 1813 bake process is conducted at 110°C for 75
seconds. The wafer is exposed to a UV light source (365 - 405 nm, 10 mW/cm2) through Metal1
mask for 5.3 seconds. Next process is developing S1813, and it is carried out with a mixed
solution of 351: DI water (1:5). The solution is sprayed onto the spinning (50 RPM) wafer three
times during total 50 seconds of total developing time. Then, the wafer is rinsed with a DI water
spray and dried with a N2 blower. After drying process, the photoresist S1813 patterns are
visually inspected under an optical microscope to ensure the quality of the patterns all over the
wafer. After that, the wafer is exposed to a DUV light source for 200 seconds. For developing SF-
11, the wafer is soaked in a fresh 101A developer for 100 seconds, and then, rinsed three times in
an automatic DI water rinse tank. After drying the wafer by using the N2 blower, the photoresist
SF-11 patterns are inspected under the optical microscope again. Once satisfactory patterns are
acquired, possible residue of the photoresist on the patterns is cleaned in an O2 plasma asher for 4
minutes with a 200 W of RF power. The bottom metal layer consists of metallic Ti (100 Å) and Pt
(500 Å) thin films. This layer is deposited using E-beam evaporation process. After the bottom
metal layer deposition, a metal lift off process and a photoresist removal process are carried out.
Next step is deposition of memristor switching layer. Several MIM structures were fabricated
using only the dielectric thin film. Some memristor devices were fabricated using bilayer oxides;
where part of the switching layer was oxygen deficient. Next thin film deposition step is the
deposition of top conducting layer. Then lift off and photoresist removal process are carried out.
13
Fabrication procedure is finished and the memristor (MIM structure) is ready to be characterized.
Fabrication process flow adopted during research has been demonstrated here by dividing the
mechanism into two parts. First part shows deposition steps adopted for memristor devices where
different type of oxide were used as the thin film layers. Second part shows pictorial
representation of fabrication steps using chalcogenide material as the switching layer.
(1) (2) (3) (4) (5)
(6) (7) (9) (10)

(8)
(11) (12) (13) (15)

(14)
(16) (17) (19) (20)

(18)
(21) (22) (23) (24)
(25) (26)
Figure 2.2. Pictorial representation of deposition Steps for oxide based Memristor Device :1. Substrate
cleaning 2. Dehydration bake 3. Photoresist coating 4. Pre-exposure bake 5. UV exposure 6. Photoresist
developing 7. O2 asher treatment 8. Metallization 9. Lift-off & cleaning 10. O2 asher treatment 11.
Deposition of switching layer (Sputtering for TiOx /TiO2 , PLD for LiNbO3-x / LiNbO3 , VO2 , TaO2 , ALD
for HfO2 , SiO2 , Al2O3 12. Photoresist coating , 13. Pre-exposer bake , 14. UV Exposure , 15. Photo resist
develop , 16. O2 asher treatment, 17. Dry etch 18. Photo resist remove , 19. O2 asher treatment , 20. Photo
resist coating , 21. Pre exposer bake, 22. UV Exposure 23. Photo resist developing , 24. O2 asher treatment ,
25. Metallization 26. Lift off and cleaning
14
Figure 2.3. Pictorial representation of deposition Steps for chalcogenide (GeTe/GST) based Memristor
Device
15
2.4 Microscopic Images for Memristor
Microscopic image for memristor devices both (single device and crossbar architecture)
has been presented here within figure 2.4. Size of overlap area varies from 2.5 µm2 to 40 µm2. A
cross point architecture [62] is preferable for high density data storage. Each intersecting point
within the crossbar structure acts as a switch or single memristor. Figure 2.4. b shows memristor
crossbar architecture where each memristor device is of 5µm2 in size.
Figure 2.4. Microscopic Image for (a) Single Memristor device (b) Memristor (4x4) Crossbar structure
2.5 Summary of device Fabrication
As per process flow, electrode layers for memristor devices were deposited using electron
beam evaporation process. Either pulsed laser deposition or sputtering technique were utilized for
the switching layer deposition.
16
CHAPTER 3
DEVICE CHARACTERIZATION
3.1 Measurement Set Up
Experimental set up consists of an electrical measurement unit with a semiconductor
characterization system (Keithley 2400-SCS) and a probing station. A MATLAB script was
developed to control the Keithley system to ensure maximum versatility.
Keithley
Microscope
Probe
Figure 3.1. Keithley 2400 Source Meter Unit (SMU), Jmicro Technology LMS-2709 microscope, S-725
micro positioner and LMS-91A thermal module system
Figure 3.2. MELCOR MTTC 1410 temperature controller and Thermaltake coolant flow control system
17
DC electrical characterization has been performed both for room temperature and
different elevated temperatures environment. Signature characteristics of bipolar resistivity has
been attained using both sweep bias and pulse inputs. Having this setup, we can apply any
arbitrary voltage sequence to the probed memristor wafer, with a minimum sample pulse width of
one Power Line Cycle (PLC), which is about 17 ms. Highly non-linear switching kinetics are
observed in the electrical characterization of each memristor device. To characterize the
memristor device, sweep bias was applied to the top electrode, and the bottom electrode was set
to the ground. Highly resistive and less resistive regions were determined with the application of
amount of voltages initiating SET and RESET phenomena [63].
Figure 3.3. Plot for triangular sweep input bias applied to the memristor device
3.2 Different MIM Structures
One possible way of fabricating memristor device is the Metal-Insulator-Metal in
sandwiched structure. Contact regions are the top and bottom electrodes and insulating layer is
the switching layer. Platinum (Pt), Gold (Au), Silver (Ag) and Nickle (Ni) have been used as
metal electrode. Titanium (Ti) has been added to promote adhesion. Seven different oxide
combinations along with two different chalcogenide materials have been utilized within
18
memristor switching layer. To date, we have successfully fabricated both oxide and chalcogenide
based memristor devices having intermediate thickness switching layer(10nm<thickness<100nm)
[64]. Among different high ‘k’ dielectrics Titanium oxide, Lithium Niobate, Vanadium Oxide,
Silicon di-Oxide, Hafnium Oxide and Aluminum Oxide were individually used as memristor
switching layer. Chalcogenide materials like Germanium Antimony Telluride (GST) and
Germanium Telluride (GeTe) thin films were also utilized as memristor mid layer. DC
characterization has been studied by varying thickness of each thin film layer as well. Electrical
characterization has been presented here for memristor device with different high ‘k’ dielectric as
the switching layer.
3.2.1 Characterization for different Oxide Based Memristors
Different transition metal oxides have been used as memristor switching layer. For each
memristor wafer, 2-inch diameter silicon (Si) substrate has been used. First oxide-based
combination presented here is the bilayer Titanium oxide based memristor device. This one has
50 nm Platinum as top and bottom electrodes. Very thin 5 nm of titanium (Ti) has been added to
promote adhesion. Metals have been deposited using electron beam evaporation technique.
Reactive sputtering has been utilized to fabricate the switching layer (30 nm thickness). Figure
3.4.a shows cross sectional view for bilayer titanium oxide based memristor device. Device
characterization relating modulation of current density with that of electric field has been plotted
within figure 3.4.c. Overlap area for this memristor device was 20 µm2.
Second projected combination was lithium niobate based memristor device. In this
section, dc characterization from three different combinations have been plotted where both the
electrode and sequence of switching layer has been modulated. First MIM structure with lithium
niobate, comprises of bottom electrode 50 nm thickness platinum (Pt) with a thin layer of
titanium (Ti). Top electrode has bilayer metals Gold (Au) 50 nm and Silver (Ag) 10 nm
19
respectively. Figure 3.5. shows cross sectional view for this memristor device along with
electrical characterization at room temperature. Overlap area of this memristor was 5 µm2.
Second memristor device with lithium niobate as switching layer comprises of bilayer thin film
deposited using standard pulsed laser deposition (PLD) technique. Same electrode combination
(Platinum (Pt) and Titanium (Ti) both as the top and bottom electrodes was deposited for this
MIM structure. Figure 3.6. shows device structure and dc characterization at room temperature.
Area of this memristor device was 7.50 µm2.
Pt ( 50 nm)
M1
Ti ( 5 nm)
TiO2 ( 10 nm)
TiOx ( 20 nm) I
Pt ( 50 nm)
M2
Ti ( 5 nm)
SiO2 ( 2 μm )
(a)
(b) (c)
Figure 3.4. Bilayer Titanium Oxide based Memristor Device (a) cross sectional view, electrical
characterization demonstrating variation of device (b)current with applied bias (c) current density with
electric field
20
Au ( 50 nm)
M1
Ag ( 10 nm)
LiNbO3 ( 40 nm) I
Pt ( 50 nm)
M2
Ti ( 5 nm)
SiO2 ( 2 μm )
(a)
-3
10 10 8
3 4
3
2
)
2
-2
1
1
Current density (Am

Current (A)
0 0
-1
-1
-2
-2 -3
-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 -2 -1.5 -1 -0.5 0 0.5 1 1.5
-1
Applied Bias(V) Electric field (Vm 10
7
)
Figure 3.5. Lithium Niobate Oxide based Memristor Device with dissimilar electrode combination along
memristor top and bottom (a) cross sectional view, electrical characterization demonstrating variation of
device (b) current with applied bias (c)current density with electric field
Next MIM device relating this section is the hafnium oxide based memristor device.
There, both the electrodes were deposited using platinum (Pt) thin film layers. Only variation was
addition of a thin layer (10 nm) of nickel (Ni) on top of the bottom electrode. In this case
switching layer thickness was 25 nm. Zero crossing pinched hysteresis with micro ampere level
on state current was obtained from such hafnium oxide based memristor device. Programming
voltage was much higher (~20 eV) than the memristor devices mentioned so far. Area of this
memristor was 20µm2.
21
Pt ( 80 nm)
M1
Ti ( 10 nm)
LiNbO3 ( 6 nm)
LiNbO3-x ( 36 nm) I
Pt ( 50 nm)
M2
Ti ( 10 nm)
SiO2 ( 2 μm )
(a)
(b) (c)
Figure 3.6. Bilayer Lithium Niobate Oxide based Memristor Device with identical electrode combination
along memristor top and bottom (a) cross sectional view, electrical characterization demonstrating device
(b) current with applied bias (c) current density with electric field
Next one is the Silicon di oxide based memristor device having 12.5 µm2 as the overlap
area. Such memristor device sustained electric fields higher than MeV range. This device was
found to produce on state current in the range of micro amperes. Programming voltage for this
device was approximately 20 V. Considering read voltage at around 5V, energy consumption was
estimated as 1.23x10-6 joule per synaptic event; provided it is utilized for neuro morphic circuit
element [65]. Zero crossing bipolar hysteresis was obtained at room temperature measurement.
Major advantage from such memristor combination is, such SiO2 based memristor produces
22
hysteresis where off to on resistance ratio [66] was found ~597 which is quite higher compared to
the transition metal oxide memristors characterized so far.
Pt ( 50 nm)
M1
Ti ( 5 nm)
HfO2 ( 25 nm) I
Ni (10 nm)
Pt ( 50 nm) M2
Ti ( 5 nm)
SiO2 ( 2 μm )
(a)
(b) (c)
Figure 3.7. Hafnium Oxide based Memristor Device having (Ni/Pt) interface layer at the bottom
electrode(a) cross sectional view, electrical characterization demonstrating variation of device (b) Current
density with Electric field (c) plot for variation of current density with electric field
23
Pt ( 50 nm)
M1
Ti ( 10 nm)
SiO2 ( 25 nm) I
Ni (10 nm)
Pt ( 50 nm)
M2
Ti ( 10 nm)
SiO2 ( 2 μm )
(a)
(b) (c)
Figure 3.8. Signature characteristics of Memristor device having SiO2 as the switching layer (a) Cross-
sectional view of SiO2 based Memristor device having 12.50 µm2 as the overlapped area (b) variation of
device (b) current with applied bias (c) current density with electric field.
Aluminum oxide was considered as the insulating layer for fabricating a new
combination of memristor device. Switching layer thickness was 25 nm. Platinum (Pt) which is
an inert metal was used both as top and bottom electrodes with a thin layer of titanium (Ti) to
promote adhesion. Reason for choosing such inert metal is to exclude the effect of electrode-
oxide interaction. Another layer of nickel (Ni) was added to the bottom electrode to investigate
the switching effect due to the interface developed between oxide layer and bilayer metals.
Sputter deposition technique was utilized for the growth of this memristor switching layer.
24
Electron beam evaporation was used for depositing memristor electrodes. Electrical
characterization was studied at room temperature. This study considers electrical characterization
varying the device overlap areas. Two memristor devices having 10 µm2 and 25 µm2 areas were
considered for characterization, maintaining the same experimental conditions. Triangular sweep
bias with peak input voltage of 1 V was provided along memristor top electrode; while the bottom
electrode terminal was always grounded. I-V hysteresis loops are the direct consequences of
memory effect [67]. Figure 3.9. (b) and (c) provide plot for change of memristor current density
with electric field acted upon the switching layer. In each case memristor’s programing voltage
was around 1 eV. After the set/programing voltage, memristor device with smaller area showed
sudden/digital transition. Memristor showing characterization as plotted in figure 3.9. b. is
suitable for non-volatile memory application. Same experiment was conducted for another
aluminum oxide based memristor device having relatively smaller (10 µm2) overlap area.
Electrical characterization from the second memristor device was plotted within figure 3.9.d. In
this case gradual transition from high resistive state to the low resistive one was observed which
is good for neuro morphic device. Memristor having larger area size emits more leakage current
compared to the previous one mentioned here. Power consumption per switching effect for both
the devices characterized here were in the range of sub micro joule. With controlled modulation
of memristor overlap area type of resistive switching can be varied. Such memristor is suggested
to be suitable both for non-volatile memory and fundamental element of neuromorphic circuit as
it shows gradual transition of resistivity.
25
Pt ( 50 nm)
M1
Ti ( 10 nm)
Al2O3 ( 25 nm) I
Ni (10 nm)
Pt ( 50 nm)
M2
Ti ( 10 nm)
SiO2 ( 2 μm )
(a)
(b) (c)
(d) (e)
Figure 3.9. Demonstration of Al2O3 based Memristor device (a) cross sectional view of MIM structure,
electrical characterization demonstrating variation of device (b) &(d) current with applied bias (showing
abrupt and gradual modulation respectively) (c) & (e) current density with electric field (showing digital
and analog resistive transition respectively)
26
Vanadium dioxide which is mainly a phase change material [68] was used for memristor
mid layer. In this case both Gold (Au) and Platinum (Pt) have been deposited as the bottom and
top electrode combination. Sequence and thickness of the deposited thin film layers are shown
within figure 3.10.a. Figure 3.10.b and c show plot of electrical characterization from this VO2
based memristor device having 25 µm2 overlapped area.
Au ( 130 nm)
Pt ( 100 nm) M1
Ti ( 20 nm)
VO2 ( 50 nm) I
Pt ( 100 nm)
Au ( 130 nm) M2
Ti ( 20 nm)
SiO2 ( 2 μm )
(a)
(b) (c)
Figure 3.10. Vanadium Oxide based Memristor Device with Identical conducting layer combination as
memristor top and bottom electrodes (a) cross sectional view, electrical characterization demonstrating
variation of device (b) current with applied bias (c) current density with electric field
27
Another transition metal oxide based memristor device is Tantalum oxide based
memristor. Figure 3.11. b and c. show electrical characterization from this memristor structure at
room temperature.
Pt ( 50 nm)
M1
Ti ( 10 nm)
TaO2 ( 25 nm) I
Pt ( 50 nm)
M2
Ti ( 10 nm)
SiO2 ( 2 μm )
(a)
-4 7
10 10
4 3
)
-2
2
2
1
Current density (Am
Current (A)
0
0
-2 -1
-2
-4
-2 -1 0 1 2
-1 -0.5 0 0.5 1
-1
7
Applied Bias(V) Electric field (Vm ) 10
(b) (c)
Figure 3.11. Tantalum Oxide based Memristor Device with Identical electrode combination along
memristor top and bottom (a) cross sectional view, electrical characterization demonstrating variation of
device (b) current with applied bias (c) current density with electric field
3.2.2 Characterization for Chalcogenide Based Memristors
This section presents memristor devices where chalcogenides were sandwiched in
between two metal electrodes. Silicon substrate has been considered as the base layer.
Germanium Antimony Telluride (GST) and Germanium Telluride (GeTe) has been considered as
memristor middle layer. In both cases Platinum (Pt) has been used both as top and bottom
electrodes. Switching layer thickness were GST (50 nm) and GeTe (40 nm) respectively for two
28
different memristor devices. Conventional switching within phase change materials takes place
by the modulation of phase from amorphous to crystalline or vice versa. Non thermal bipolar
resistive switching was observed from two different chalcogenide based memristor devices. In
this case, electrical pulses affect the structural defects within phase change material, other than
joule heating for thermally activated phase transformation. Triangular positive and negative
sweep was applied to the chalcogenide based memristor device to test the typical bipolar
switching operation.
Pt ( 50 nm) M1
Ti ( 10 nm)
GST ( 50 nm) I
Pt ( 50 nm) M2
Ti ( 10 nm)
SiO2 ( 2 μm )
(a)
(b) (c)
Figure 3.12. Germanium Antimony Telluride (GST)based Memristor Device with Identical electrode
combination along memristor top and bottom (a) cross sectional view, electrical characterization
demonstrating variation of (b) device current with applied bias (c) current density with electric field
Positive sweep causes set transition, in other words from amorphous to full
crystallization. Whereas negative pulse induces reset transition with an increase of resistance after
the reset voltage. Such reset transition cannot be assigned as further amorphization state. Because
29
typical amorphization within conventional phase change memory requires very fast quenching
rate (~10 to 100K/ns). This is around 106 times faster than the sweep rate of the input bias applied
for our electrical characterization [69]. Figure 3.12. and 3.13. show plot for device cross
sectional area and corresponding electrical characterization for GST and GeTe based memristor
devices respectively.
Pt (50 nm)
M1
Ti (10 nm)
GeTe (40 nm) I
Pt(50 nm)
M2
Ti (5 nm)
SiO2 ( 2 μm)
(a)
-3 8
10 10
3 1.5
2 1
)
-2
0.5
1
Current density (Am
Current (A)
0
0
-0.5
-1
-1
-2 -2 -1 0 1 2
-1 -0.5 0 0.5 1 -1
7
Electric field (Vm ) 10
Applied Bias(V)
(b) (c)
Figure 3.13. Germanium Telluride (GeTe) based Memristor Device with identical electrode combination
along memristor top and bottom (a) cross sectional view, electrical characterization demonstrating variation
of (b) device current with applied bias (c) current density with electric field.
3.3 Stable Repetitive Characterizations from different MIM Structures
Different MIM combinations have been electrically characterized to investigate the
possibility of non-volatile/ memory effect from the device response. One important attribute of
such characterization is to verify the stability of current-voltage characterization due to
application of repetitive periodic bias. In other words, intra device or cycle to cycle variability
30
can also be investigated from this experiment [70]. Bilayer lithium niobate (Pt/LiNbO3-x /LiNbO3
/Pt), GST (Pt/GST/Pt) and GeTe (Pt/GeTe/Pt) based memristor devices were taken under
consideration in this regard. Figure 3.14., 3.15, 3.16 and 3.17 show repetitive characterization
from lithium niobate, GST and GeTe based memristor devices respectively. Fifty times repeatable
hysteresis was obtained from the bilayer lithium niobate based memristor device. Coefficient of
dispersion for both off and on state device responses were evaluated as 0.371 and 0.32
respectively. Figure 3.15 shows twenty times repeatable, stable hysteresis from a GST based
memristor device. In this case dispersion values for off and on switching states were found as
0.0597 and 0.0881 respectively. Another memristor device with GeTe as switching layer was
taken under consideration for studying the intra-device variability with repetitive cycle to cycle
variation. In this case, experimental results show off and on state switching parameters to have
coefficient of covariance as 0.0995 and 0.1984 respectively.
-3
10
6
2
Current (A)
-2
-4
-6
-1.5 -1 -0.5 0 0.5 1 1.5
Voltage (V)
variability from a bilayer lithium niobate based memristor device with 7.50 µm2 overlap area
31
-3
10
1.5
0.5
Current (A)
0
-0.5
-1
-1.5
-1.5 -1 -0.5 0 0.5 1 1.5
Applied Bias(V)
variability from a GST based memristor device with 7.50 µm2 overlap area
-3
10
4
2
Current (A)
-1
-2
-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8
Applied bias (V)
variability from a GeTe based memristor device with 7.50 µm2 overlap area
32
-4
10
4
Current (A)
0
-1
-2
-3
-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8
Applied bias (V)
variability from a GeTe based memristor device with 7.50 µm2 overlap area
3.4 Detailed Research on Lithium Niobate Memristor Devices
Metal-LiNbO2 -Metal was first recognized as a memristor in 2012 by Greenlee et. al.
[71]. Their device structure consisted of annular geometry with (Ni/Au) metal stack. Such
combination and structure exhibited short term memory which was a volatile device. Another
research found in [72] shows hysteresis from LiNbO2 based memristor with (Au/Al) electrode
stack and annular geometry. Both the research previously reported were focused on the growth of
LiNbO2 based memristor devices using the molecular beam epitaxy technique [73]. Work
mentioned in [71] shows bias applied for sense/read current was in the range of ~1V which would
possibly enhance the level of energy consumption for memristor off state conductivity. Our
(Pt/LiNbO3-x/LiNbO3/Pt) devices were fabricated using standard pulsed laser deposition (PLD)
technique maintaining simple square geometry. The geometric shape of electrode has significant
effect on electric field distribution eventually affecting the bipolar resistive switching [74]. In our
case memristor devices having square dimension ensures homogeneous electric field distribution.
Our device characterization results were found to be non-volatile, stable, and repetitive. Several
other switching layer combinations using lithium niobate (either oxygen deficient or oxygen rich
oxide) were studied to investigate the most stable, repetitive electrical characterization.
33
3.5 Characterization Based on Device Chemistry
This section emphasizes electrical characterization for lithium niobate based memristor
device mainly by modulating proportion of oxide within switching layer. Six different device
structures were examined in this work to characterize devices based on device chemistry. Figure
3.18 shows plot for cross-sectional view of six memristor structures where lithium niobate is the
significant portion of switching layer [62],[75].
The switching layers in Figs. 3.18. (a) and (b) consist of lithium niobate thin film in non-
stoichiometric state. Figure 3.18. a contains highly oxygen deficient oxide layer (LiNbOx)
whereas abundantly oxygen rich one has been shown within fig.3.18.b using the LiNbOy layer.
Fig.3.18. (c) shows a third device where a 2 nm aluminum oxide layer is added between the
switching layer and the bottom electrode. Figs. 3.18. (d) and (e) both have a split switching layer
that consists of 21 nm of LiNbO3 and 21 nm of LiNbOx. However, the order of these layers is
reversed in one of the devices relative to the other. Finally, the device in Fig. 3.18. (f) has both
LiNbO3 and LiNbOx deposited in the same order as in Fig. 3.18. (e), but at a different ratio. All
the characterizations in this section were completed using a cyclic voltammetry setup for more at
least 10 cycles. The positive threshold voltage for all devices was about 1.5 V, and the negative
threshold voltage is varied between -1.5 V and -2 V. The devices with single LiNbOx (Fig.
3.19.a.) and LiNbOy (Fig. 3.19.b.) thin films exhibited the weakest hysteresis loop and switching
resistance. However, in the first few cycles each of these devices displayed a slow transition
while switching between the high and low resistance state.
34
Figure 3.18. Cross sections of the six different device structures studied. The switching layer of each device
(bottom to top) was constructed as follows: (a) LiNbOx (b) LiNbOy (c) Al2O3 / LiNbOx (d) LiNbO3 /
LiNbOx (e) LiNbOx /LiNbO3 and (f) an alternative composition of LiNbOx/LiNbO3
Unfortunately, the hysteresis in these devices weakened as the switching cycles
increased. The devices in Figs. 3.19.d. and 3.19.e. exhibit satisfactory switching cycles during the
first cycle, but performance degrades as more cycles are completed. The I-V characteristic for
each of these two devices shows a diode-like region where resistance becomes very high no
matter what state the device is in. This region becomes larger after more voltage sweeps are
applied to these devices. Finally, after 10 sweeps the I-V characteristic begins to resemble that of
a complementary memristor device. Given this observation, it may be possible that the complex
layer structure of these devices (especially the device in Fig. 3.19.e and f) is causing two different
ion movement processes to occur, leading to this similarity in I-V response. Of the six device
structures tested, the most stable I-V characteristics were observed in the devices that had a
LiNbO3 top layer and a LiNbO3-x bottom layer. After 10 successive voltage sweeps were applied
to each of these devices, some variability was exhibited in hysteresis shape, and stability was
35
displayed in resistance range. This is most likely because the stoichiometric top-layer film
stopped ambient oxygen from reaching the oxygen deficient bottom-layer film. When comparing
the hysteresis shape of the characterizations in Figs. 3.19.e. and 3.19.f., the characterization in
Fig. 3.19.f. shows a much more symmetric operation. Thus, a thinner stoichiometric lithium
niobate top layer aids in symmetric device behavior, making this device most appropriate for
neuromorphic computing.
Figure 3.19. Repetitive Sweep dependent Current Voltage Characterization at room temperature from
Memristor device varying proportion of Lithium niobate within switching layer (a) to (f) to investigate best
possible MIM combination for stable hysteresis
3.6 Repetitive Characterization Based on Device Area
The device characterized in Fig. 3.19.e. displayed the strong IV characterization when
tested for neuromorphic capability. This section presents characterization results where this
device composition was tested for a few different device areas. The results are displayed in
Fig.3.20. In each case in Fig. 3.20, a strong and repeatable hysteresis is observed. However, the
20 μm2 device shows the most symmetry. Also, the 2.5 μm2 device shows the most instability. It
36
is also important to note that the resistance ratio of the devices appears to degrade as device area
is increased. Given this information smaller devices are better. However, patterning devices that
are too small appears to lead to less stability and symmetry. Therefore, if smaller devices are
required, these may require a deposition technique that increases thin film quality, thus improving
stability as we pattern these devices in the nano scale. At this point in time, the device with
composition as shown in Fig. 3.20 (b) with an area of 20 µm2 displayed the strongest results in
terms of stability, repeatability, and symmetry.
Figure 3.20. Repetitive electrical characterization from bilayer lithium niobate based memristor device
varying overlap area size (a) to (d)
3.7 Temperature Dependent Characterization
Variation of current voltage characterization from memristor device has been studied.
Thermal effect has been considered both for low resistive and high resistive states. Figure 3.21.(a)
shows dc characterization for MIM structure maintaining room temperature.
37
o o
(a) 25 C (b) 35
o
(c) 45 C
o
(d) 55 C
o
o
65 C 75 C
o
o
85 C 95 C
Figure 3.21. Electrical characterization of bilayer lithium niobate based memristor device with variable
temperatures (a) room temperature 25oC (b) 35oC (c) 45oC (d) 55oC (e) 65oC (f) 75oC (g) 85oC (h) 95oC
38
As per experiment, memristor conductivity values along high resistive state is not
strongly affected by temperature variation. Current voltage characterization plot from figure (b)
to (h) shows significant change within memristor low resistive state. Device conductivity along
low resistive states show exponential transition other than linear change as found for ohmic
conduction mechanism.
4
Resistance Ratio
0
300 320 340 360 380
temperature (K)
Figure 3.22. Variation of Memristor resistance states (both HRS and LRS) with temperature
Bilayer lithium niobite based memristor device shows decrease of low resistive state with
that of the increase of temperature. We believe the exponential transition along the low bias
region shows semiconducting behavior other than being metallic [76]. This is suggested to be due
to the existence of oxygen vacancies termed as traps/defects within the memristor switching
layer. Figure 3.21. shows variation of memristor on resistive state with seven different
temperatures. Zero crossing pinched hysteresis was found from each characterization
maintaining the compliance current always the same. Increase of thermal condition higher than
room temperature caused the device on state show more exponential transition other than the
linear one as found for room temperature measurements. From experimental point of view, it can
be inferred that thermal change makes significant impact upon the memristor device on state or
39
low resistive state compared to the regular room temperature measurements. Figure 3.22. shows
𝑅𝑅𝑜𝑜𝑜𝑜𝑜𝑜
change of memristor resistive ratio ( )with the variation of temperature up to 95oC.
𝑅𝑅𝑜𝑜𝑜𝑜
3.8 Summary of Electrical Characterization
Purpose for this study is to demonstrate a synthetic synaptic device which would eventually
be able to replicate the functionality of human brain. Voltage at which memristor device starts to
conduct at a greater scale is the set/programming voltage. Read voltage is the low bias across
memristor device. Existence of multiple resistive states is of utmost importance for memristor to
show analog resistive changes. Resistance ratio has been evaluated considering the device
conductivity both for off and on state at the read bias. Higher resistance ratio is expected to
ensure greater number of intermediate resistive states between memristor off and on condition.
Desired power consumption per synaptic activity is in the range of sub-micro joule.
Electrical characterization results for ten different memristor combination have been
populated in the table 3.1. In each case intermediate thickness dielectric has been considered for
characterization.
40
Table 3.1: Tabular representation for electrical characterization results from various MIM structures or
Memristor combinations
No. of MIM Devic Overlap Progra Read Resistan Power Energy
Memri Structure e ped mming Voltag ce Ratio Dissipation Consumption
stor Thick Area Voltage e (~) (P=VI) per Synaptic
Device ness (µm2) (Volt) (Volt) (Watt) Activity (J)
(nm)
1. (Pt/TiOx/Ti 30 20 6.90 0.80 6 2.197𝑥𝑥10−7 3.7349x10−9

O2/Pt)
2. (Pt/LiNbO3 40 5 0.50 0.10 3.37x103 4.8699x10−5 8.2788x10−7

/Au)
3. (Pt/LiNbO3 42 7.50 1.20 0.20 5 9.94𝑥𝑥10−5 1.69𝑥𝑥10−6

-x / LiNbO3
/Pt)
4. (Au/Pt/VO 50 25 1.30 0.25 0.50 5.2317𝑥𝑥10−6 8.9𝑥𝑥10−8

2 /Pt/Au)
5. (Pt/GST/Pt 50 20 1.20 0.20 0.30 3.038𝑥𝑥10−6 5.1658𝑥𝑥10−8

)
6. (Pt/GeTe/P 40 12.50 0.80 0.13 4 1.775𝑥𝑥10−5 3.0176𝑥𝑥10−7

t)
7. (Pt/Ni/SiO2 25 12.50 20 5.0 597 7.217𝑥𝑥10−5 1.23𝑥𝑥10−6

/Pt)
8. (Pt/Ni/HfO 25 20 22.5 6.5 2 9.6478𝑥𝑥10−6 1.64𝑥𝑥10−7

2 /Pt)
9. (Pt/Ni/Al2 25 10 1.0 0.15 32 6.57𝑥𝑥10−7 1.12𝑥𝑥10−8

O3 /Pt)
10. (Pt/TaO2 40 15 0.60 0.12 2 1.83𝑥𝑥10−6 3.11𝑥𝑥10−8

/Pt)
41
CHAPTER 4
INVESTIGATION OF DOMINANT CHARGE TRANSPORT MECHANISM
4.1 State of the Art-Charge Transport Mechanism through MIM Structure
Dielectrics are the materials having high energy band gap typically larger than 3eV or 5eV.
At zero (0) kelvin they have filled valance band and completely empty conduction band. Hence,
there is no transport of carriers for electrical conduction. Increase of temperature or application of
high electric field causes soft breakdown [77]. Such soft breakdown through dielectric is
responsible for memristor device switching from normally off to on state. Memristor devices are
typically made up of three-layered thin films which is metal-insulator-metal (MIM). Study of
various conduction mechanisms through dielectric films is of utmost important for characterizing
this newly proposed electrical circuit element. Charge transport through metal-insulator-metal
structure can be divided mainly into two groups; first one is Interface or Electrode Limited
conduction and the second category is the Bulk limited conduction mechanism [78]. Figure 4.1.
shows diagram for typical current conduction mechanism through metal-dielectric-metal structure.
Different Charge Transport Mechanisms
Interfacial or Non Filamentary Bulk or Filamentary

Conduction Conduction
Schottky Fowler Direct Trap Assisted Poole-Frenkel

Emission Nordheim Tunneling Tunneling Emission
Tunneling
Figure 4.1. Diagram demonstrating Typical Current Conduction Processes through MIM Structure
Interface or electrode limited conduction depends upon the electronic properties of the
metal-dielectric interface layer. Barrier height is one of the controlling aspects for this type of
conduction. Whereas, bulk limited conduction is mainly influenced by the electronic properties of
42
dielectric used within the device. Flow of current due to thermionic emission is highly
temperature dependent. Pictorial Representation of state-of-the-art carrier transport process
through MIM structured device is shown in figure 4.2.
Figure 4.2. Typical charge transport mechanisms through MIM structure (a) Direct Tunneling (b) Fowler-
Nordheim Tunneling (c) Ohmic Conduction (d) Poole-Frenkel (P-F) Emission (e) Schottky Emission
Direct tunneling means the transport of charge carrier responsible for conduction from
the cathode to the anode terminal where the oxide layer is ultra-thin which is much less than 10
nm. Current density (J) for this mechanism has been expressed as mentioned in eqn. (4.1) [79],
8𝜋𝜋�2𝑚𝑚𝑒𝑒𝑒𝑒𝑒𝑒 3� 3�
𝑉𝑉 2
−� Ф𝑏𝑏 2 ��1−�1− � �
3ℎ𝑞𝑞 Ф𝑏𝑏
𝑞𝑞3 Ф 2Ф𝑏𝑏 2
𝐽𝐽 = �8𝜋𝜋ℎФ � � 𝑉𝑉𝑏𝑏 � � 𝑉𝑉
− 1� 𝐸𝐸𝑜𝑜𝑜𝑜 exp( 𝐸𝐸𝑜𝑜𝑜𝑜
) (4.1)
𝑏𝑏
43
Here Ф𝑏𝑏 indicates barrier height, h is the Planck’s constant, Eox is the electric field acted
upon the charge carrier (electron) q and effective mass meff. Fowler-Nordheim tunneling can be
ruled out for our fabricated memristor device as it requires very high electric field (108
>>MeV/cm) along thin (<20nm) dielectrics. For F-N emission, tunneling takes place directly
from cathode to anode maintaining the current voltage relation shown in eqn. 4.2 [80].
� �1 3
𝑞𝑞2 𝐴𝐴2 𝑉𝑉 2 8𝜋𝜋�2𝑚𝑚𝑒𝑒𝑒𝑒𝑒𝑒 𝑞𝑞� 2 Ф𝑏𝑏 2
𝐼𝐼 = 8𝜋𝜋ℎ 𝑠𝑠2 Ф𝑏𝑏
exp(− 3ℎ 𝑉𝑉
) (4.2)
Where q and meff are the charge and effective mass of electron, A is the device area, h is
the Planck’s constant, V is the applied bias, s indicates the thickness of the switching layer and
Фb stands for conduction band offset at the cathode. Ohmic conduction [81] is applicable when
device is completely conducting and there is linear relationship between current and applied bias.
In other words, Ohmic conduction plays well when there is metal fermi level pinning with the
oxide conduction band minima. Device current density equation has been expressed below using
eqn. (4.3)
𝐸𝐸
𝐽𝐽 = 𝑞𝑞𝑁𝑁 ′ µ𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸 � 𝐴𝐴 � (4.3)
𝑘𝑘𝑘𝑘
3�
2𝜋𝜋𝑚𝑚𝑒𝑒𝑒𝑒𝑒𝑒 𝑘𝑘𝑘𝑘 2
Here 𝑁𝑁 ′ = 2 � ℎ2
� ; which defines charge carrier density responsible for device
conduction, µ stands for carrier mobility, E is the electric field acted upon the charge carrier and
EA is the activation energy. Other two well-known charge transport processes are Poole-Frenkel
emission and Schottky emission. P-F is a one-step trap assisted tunneling process having current-
voltage relation expressed in equation (4.4)
𝛽𝛽𝑃𝑃𝑃𝑃 √𝑉𝑉−Ф𝑃𝑃𝑃𝑃
𝐼𝐼~𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 � 𝑘𝑘𝑘𝑘
� (4.4)
For P-F emission [82] the trap density within switching layer is very high. The electrons
in the electrode can transit to the bound states originating from the traps in the insulator close to
44
the metal/insulator junction by quantum-mechanical tunneling. This has a high probability for the
electrons of the electrode near the junction; especially when the traps are located close to the
interface. Therefore, the tunneling can serve as a significant mechanism for supplying electrons to
traps when the trap density is very high. Successively, the trapped electrons can be thermally
activated from the bound states of the traps to the conduction band of the insulator. This thermal
activation becomes easier by virtue of the lowered potential-well height of the traps when an
electric field is applied for PF effect. Schottky emission [83]is the thermally induced flow of
charge carriers over a potential barrier. This occurs because the thermal energy given to the
carrier overcomes the work function of the material. That means injection and tunneling of charge
carriers due to thermal effect. This is also known as thermally activated electrons injected over
the barrier into the conduction band. Device current density (J) equation supporting Schottky
emission can be expressed as shown in eqn. (4.5)
−𝑞𝑞Ф𝐵𝐵 𝑞𝑞𝑞𝑞
𝐽𝐽 = 𝐴𝐴∗ 𝑇𝑇 2 exp �𝑘𝑘𝑘𝑘
� exp( ) (4.5)
𝑘𝑘𝑘𝑘
Here, A* is the Richardson’s constant, T is the experimental temperature, ФB indicates
Schottky barrier height. Another very significant mechanism responsible for conductivity through
metal-oxide layer is the tunneling of charge carriers through the defects or traps within the
insulating layer. Probability of tunneling depends upon the existence of unfilled traps to support
quantum mechanical tunneling along very low bias region. Device current ‘I’ due to trap assisted
tunneling is related to the [84]
1 4 3� 3�
𝐼𝐼~ � E −E −F′ .d′
� �exp �− ′ �2𝑚𝑚𝑒𝑒𝑒𝑒𝑒𝑒 �𝐸𝐸𝑡𝑡 2 − (𝐸𝐸𝑡𝑡 − 𝐹𝐹 ′ . 𝑑𝑑′ ) 2 �� (4.6)
�1+exp� b t �� 3ℎ𝑞𝑞𝐹𝐹
kT
Where the first exponential term in the right-hand side defines the fermi function or the
probability of occupancy of charge carriers which would tunnel through the electrode oxide
interface. The second exponential term defines the tunneling probability of charge carriers. Also,
45
Eb indicates barrier height and Et is the trap energy level within band gap. 𝐹𝐹 ′ is the electric field
acting upon the charge carrier, meff is the effective mass of electron and 𝑑𝑑′ is the trap distance
from the cathode terminal.
Another charge transport mechanism is the Space Charge Limited Current Conduction
(SCLC) which is significant in case of highly non-linear (J-E) characteristics. MIM structure
having a shallow trap distribution existing in the oxide bandgap, allow space charges to be
injected in the dielectric through the ohmic contact. A large fraction of this injected charge, which
is strongly temperature dependent condenses in the insulator , which are the space charges [84].
SCLC conduction can be expressed using the current density (J) equation mentioned below for
the simplest case of monoenergetic shallow traps in oxide bandgap.
9 𝐸𝐸 2 𝑁𝑁𝑐𝑐 𝐸𝐸
𝑎𝑎𝑎𝑎
𝐽𝐽 = 𝜀𝜀µ𝜃𝜃 (4.7) 𝜃𝜃 = exp(− 𝑘𝑘𝑘𝑘 ) (4.8)
8 𝑑𝑑 𝑁𝑁𝑡𝑡
Here, ε is the dielectric permittivity defined as ε= εr εo , µ is the electron mobility, θ is the
ratio between injected carrier density with that of the thermally generated charge carriers, Nc and
Nt denote the injected charge carrier density due to high electric field and thermally generated
charge carrier density. E stands for electric field acted upon the oxide, and d is the thickness of
the oxide layer. Slope for I-V characterization in double logarithmic scale is close to ‘2’ which is
a fingerprint for the SCLC mechanism [85].
4.2 Prior Physical Models for Memristor Conduction
Study of ReRAM has been very fascinating from early 2000. Charge transport phenomena
within MIM micro/nano-structured device has been illustrated using mostly the above-mentioned
typical conduction mechanisms so far. Memristor when utilized as a memory element, can be
named as resistive random-access memory (ReRAM) as well. First physically realizable
memristor was the one with Titanium Oxide as the switching layer [86]. There the switching layer
acted as a bilayer: one part being the oxygen deficient oxide layer (TiOx) which is the less
46
resistive part and the other is the regular insulating layer (TiO2). It was claimed, application of
external bias across the memristor device moves the boundary between these two regions which
eventually causes the charged dopants to drift. In fact, insulating to metallic characteristics were
suggested to be due to the ion migration for the very first memristor device fabricated at HP lab in
2008 [86]. The device resistance was determined by the series connection of a doped region and
an undoped region separated by a movable boundary. Considering total thickness of the switching
layer D and doped region w, voltage drop along the device has been calculated using the
expression mentioned below:
𝑤𝑤(𝑡𝑡) 𝑤𝑤(𝑡𝑡)
𝑉𝑉(𝑡𝑡) = �𝑅𝑅𝑜𝑜𝑜𝑜 𝐷𝐷
+ 𝑅𝑅𝑜𝑜𝑜𝑜𝑜𝑜 �1 − 𝐷𝐷
�� 𝐼𝐼(𝑡𝑡) (4.9)
𝑑𝑑𝑑𝑑(𝑡𝑡) 𝑅𝑅𝑜𝑜𝑜𝑜
= µ𝑣𝑣 𝐼𝐼(𝑡𝑡) (4.10)
𝑑𝑑𝑑𝑑 𝐷𝐷
Which provides the following formula for w(t)
𝑅𝑅𝑜𝑜𝑛𝑛
𝑤𝑤(𝑡𝑡) = µ𝑣𝑣 𝑞𝑞(𝑡𝑡) (4.11)
𝐷𝐷
µ𝑣𝑣 𝑅𝑅𝑜𝑜𝑜𝑜
𝑀𝑀(𝑞𝑞) = 𝑅𝑅𝑜𝑜𝑜𝑜𝑜𝑜 �1 − 𝐷𝐷 2
𝑞𝑞(𝑡𝑡)� (4.12)
Figure 4.3. HP Lab fabricated Memristor device (a) Pt/TiO2 /TiO2-x /Pt structure (b) Proposed Mechanism
for resistivity change
47
In 2010, a research group from University of Toledo [87], proposed a manganese doped
bilayer titanium oxide based memristor device with tungsten as the top and bottom electrodes.
According to their claim, off state current from the memristor device was found to behave like a
diode in each polarization side. Depositing the bilayer (TiO2-x /TiO2) memristor using Manganese
(Mn) reduces off state current eventually resulting less power consumption compared to the one
with no Manganese (Mn). Diode current equation for applied bias V can be expressed as shown
in eqn 4.11. I and V are device current and applied voltage, q is the majority charge carrier, k is
the Boltzmann’s constant.
𝑞𝑞𝑞𝑞
𝐼𝐼~ exp � − 1� (4.13)
𝑘𝑘𝑘𝑘
Figure 4.4. Demonstration of manganese doped bilayer titanium oxide based memristor device (a)
cross sectional view (b) plot for memristor off state currents in both polarity cases
In 2011, a research group at Stanford university [88] proposed a three step Elastic Trap
Assisted Tunneling as the conduction mechanism through ReRAM at HRS , with single layered
oxygen deficient Hafnium Oxide (HfOx). Memristor devices demonstrated by the Stanford group
48
was not reported as forming free device. Figure 4.5 and 4.6 shows plot for HfOx based memristor
device and simulation results for HRS state reported by Yu et. al. in [89].
Figure 4.5. Electrical characterization for Hafnium Oxide based Non-Volatile memory device or Resistive
RAM (RRAM) (Fabricated by Stanford University Research group). Inset shows sandwiched structure for
the RRAM
Figure 4.6. Simulation for Elastic Trap Assisted Tunneling at High Resistive State (HRS) from Hafnium
oxide-based RRAM device
In 2012, another research [90] group proposed a tungsten oxide based memristor device
with palladium and tungsten as top and bottom electrodes respectively. Their memristor off state
current was explained due to the tunneling of charge carriers through Schottky effect.
In 2013, another research group [91] claimed that resistive switching along high resistive
state through ReRAM device (with Zr: SiO2 as the switching layer) is due to the Poole-Frenkel
49
effect; which resulted from the thermal emission of the trapped electrons within the Zr: SiO2 film.
A comprehensive physical model explaining dynamic current conduction mechanism has been
proposed by Wei Lu’s research group in 2014. They claimed flow of current through memristor
as ionic conduction. They utilized the conventional drift diffusion ion transfer model for
memristor device conduction [92]. Their claim was, that the memristor conductivity is due to the
redistribution of ions both along HRS and LRS state. They explained dynamic resistive switching
mechanism for a tantalum oxide-based bilayer memristor device. Diffusivity and migration of
ions was suggested to be responsible for memristor conductivity. Figure 4.7 demonstrates ionic
drift-diffusion mechanism suggested for filamentary conduction through memristor device .
Figure 4.7. University of Michigan fabricated Memristor device (a) Pd/Ta2O5 /TaOx /Pd structure (b) Ionic
Transport Mechanism for Memristor conductivity change
In 2017 , Bousoulas et. al. reported resistive switching from (Au/Ti/TiO2-x /Au) ReRAM
suggesting trap assisted tunneling mechanism responsible for off state conductivity[93]. Metal-
LiNbO2 -Metal was first recognized as a memristor in 2012 by Greenlee et. al. [94] . Research
demonstrated by M. B. Tellekamp suggests conductivity from a (Au/Ti/LiNbO2 /Al/Au)
memristor due to drift and diffusion mechanism modifying local hole doping concentration
through the migration of lithium ions. There they defined such conductivity as the mobile-ion-
50
wavefront memristors [95]. Authors in [96] reported hysteresis characterization from a
Magnesium Oxide based memristor device suggesting filamentary conduction. Drift and diffusion
of metallic Ag+ ions within MgO changes resistivity for the switching layer. We propose a bilayer
lithium niobate based memristor device (Pt/LiNbO3-x /LiNbO3 /Pt) showing stable, repetitive ,
non-volatile resistive switching. A steady state approach demonstrating elastic trap assisted
tunneling mechanism through positively charged oxygen vacancy was found dominant for
memristor high resistive state. ohmic conductivity was found agreeable during low resistive state
for room temperature measurements.
This dissertation explains the dominant current conduction mechanism through a bilayer
lithium Niobate based memristor device using an analytical model. Experimentally obtained
memristor signature characteristics have been scrutinized at different resistive levels. Proposed
steady state electronic transport model [97] characterizes temperature variability as well. Tabular
representation for previous literature review of memristor’s charge transport mechanism have
been shown in table 4.1.
51
Table 4.1: Tabular representation of previous literature review on memristor conductivity
No Year Research Group MIM Mechanism

Structure
1. 2008 HP Lab (Pt/TiO2-x Drift of interface between doped and
/TiO2 /Pt) undoped region of the memristor switching
layer[13].
2. 2010 University of (W/Mn/Ti Flow of current was claimed analogous to
Toledo O2-x characterization of a practical diode [87]
/TiO2/W)
3. 2011 Stanford University (Pt/HfOx ETAT using three steps of charge transport
/TiN) [88]
4. 2012 University of (W/WOx Drift and diffusion of oxygen vacancy within

Michigan, Ann /Pd) memristor switching layer suggesting joule
Arbor heating [90]
5. 2013 National Sun Yat- (Pt/Zr:SiO2 Poole-Frenkel effect responsible for

Sen University, /TiN) memristor off state conductivity [91]
Taiwan
6. 2015 University of (Pd/TaOx Drift and diffusion of oxygen vacancy within
Michigan, Ann /Ta2O5 /Pd) memristor switching layer suggesting joule
Arbor heating [92]
7. 2017 National Technical (Au/Ti/TiO Trap Assisted Tunneling suggesting both

University of 2-x /Au) ionic and electronic contributions for the off-
Athens state conductivity [93]
8. 2017 Georgia Institute of (Au/Ti/LiN Drift and diffusion modifying local hole
Technology bO2 doping concentration through the migration
/Al/Au) of lithium ions [95]
9. 2019 University of Porto, (Pt/MgO/A Drift and diffusion of metallic Ag+ ions
Portugal g/Ru) within MgO changes resistivity for the
switching layer [96]
10. 2020 University of (Pt/LiNbO3 Steady state charge transport suggesting two
Dayton -x /LiNbO3 step ETAT mechanism [100]
/Pt)
52
4.3 Filamentary and Non-Filamentary Switching within MIM Structure
This work focuses on two well defined switching mechanisms namely, interfacial (or
homogeneous) switching and filamentary switching [98].
4.3.1 Filamentary Switching
It is the switching mechanism where defects or oxygen vacancies within oxide/dielectrics
are organized into a filament shape in between two metal electrodes. Usually such bipolar
switching shows sharp transition from HRS to LRS or vice versa.
4.3.2 Non-Filamentary Switching
In this case, oxide defects are homogeneously distributed along the metal-insulator
interface. Smooth, purely voltage controlled bipolar switching is observed in case of non-
filamentary conduction process. Here programming voltage remains almost unchanged
irrespective of switching layer thickness. Tabular representation for the fundamental differences
between these two switching mechanisms are depicted below.
53
Table 4.2: Variation of device attributes for Filamentary and Non-Filamentary Resistive Switching
No Device Attributes Filamentary/ Non-Filamentary/

Inhomogeneous Interfacial/ Homogeneous
Switching Switching
1. Variation of Programing voltage Programing voltage remains

programming has strong dependence almost unchanged/very little
voltage with oxide upon oxide thickness change with variation of
thickness oxide thickness
2. Dispersion for Higher order dispersion Interfacial switching
subsequent both along HRS and LRS provides small dispersion
switching is expected. This would from cycle to cycle
mostly lead to the switching. Memristors
problem of device showing this type of
variability or switching switching would be less
parameter variation in prone to parameter
large memory arrays. variability.
3. Variation of Devices Significant decrease of
switching states with demonstrating filamentary resistivity both in case of
device area switching do not show HRS and LRS with that of
dependence of switching device area can be observed
states with that of the for interfacial switching
device area size. mechanism
4. Variation of Modulation of Strong linear increase
reset current with device area causes or decrease of reset current
device area insignificant change with showing proportional
reset current in case of change with device area is
filamentary switching. found for non-filamentary
or interfacial switching.
4.4 Experimental Verification for Filamentary/Non-Filamentary Switching from

Memristor Device
In case of filamentary switching, defects or oxygen vacancies within oxide/ dielectrics
are organized into a filament shape maintaining inhomogeneous distribution in between two
metal electrodes. Whereas, non-filamentary switching occurs due to dominance of
homogeneously distributed traps along the electrode-oxide interface. Before proceeding to the
discussion of dominant charge transport through the proposed memristor device, first variation of
four different device attributes due to either filamentary/non-filamentary switching have been
scrutinized.
54
4.4.1 Variation of Resistive States with Device Area
Significant linear decrease of memristor resistance ratio with that of device area
can be observed for non-filamentary switching. Devices demonstrating filamentary
switching do not show strong dependence of resistive states with that of the device area
and does not abide by the equation (i) mentioned below [98]. Our research considers
electrical characterization from the bilayer lithium niobate based memristor devices having
different overlap areas [([(5, 7.50, 10, 12.50, 15, 17.50, 20, 22.50, 25, 27.50, 32.50, 35,
37.50 and 40) μm2)]. A set of memristor devices having variable overlap areas and identical
experimental conditions have been taken into consideration. No clear dependence of device
resistance ratio ( ) with device area were observed. According to the expression 𝑅𝑅 =
𝑑𝑑
�𝜌𝜌 𝐴𝐴
� … . (𝑖𝑖) , device resistivity should linearly decrease with the increase of area size
[76][138]. In our case device area has been varied from 5 µm2 to 40 µm2. Increase of area is
supposed to linearly reduce the level of switching parameters. According to the plot shown
in figure 4.8.a, memristor high resistance state varies with device area which does not follow
the condition mentioned in equation (i) . Also, according to the plot in figure 4.8.b there is
irregular increase and decrease of memristor resistance ratio with that of the device area. It
means proposed lithium niobate based memristor structure switching parameters are
independent of device area modulation. This is a fingerprint for filamentary resistive
switching. Results from this experiment shown in figure 4.8, justifies first evidence for
filamentary switching for the proposed MIM structure. A total of 15 devices have been
taken under consideration for this characterization as plotted in figure 4.8. We believe that
in the future, this investigation needs to be done at a larger scale where change of device
55
area would vary from 50nm2 to 50 µm2 . Characterization from a wider scale would enhance
the justification for the fingerprint discussed for filamentary switching applicable for our
bilayer lithium niobate memristor device.
4
10
2
1.8
1.6
1.4
(a)
1.2
)
1
HRS (
0.8
0.6
0.4
0.2
0
0.5 1 1.5 2 2.5 3 3.5 4
-2
-11
Device Areas (m ) 10
(b)
4
Resistance Ratio
0
0.5 1 1.5 2 2.5 3 3.5 4
2 -11
Device Areas (m ) 10
Figure 4.8. Variation of (a) memristor high resistance states and (b) resistance ratio ( ) with different
overlap areas
56
4.4.2 Variation of Programming voltage with oxide thickness
Reducing the thickness of the oxide layer from 42nm to 29nm causes reasonable change in
the forming voltage. This agrees with the drop of potential across the bulk oxide other than being
concentrated at the device top interface. This would indicate filamentary switching , as reported
in [98] for HfO2 based resistive random-access memory device. Experimental results shown in
figure 4.9, shows similarity for filamentary switching from our memristor devices.
Oxide Thickness= 42nm Oxide Thickness= 29nm
(a) (b)
1.2
1.1
1
Programmimg Voltage (eV)
0.9
0.8
0.7
0.6
28 30 32 34 36 38 40 42
Oxide Thickness (nm)
(c)
Figure 4.9. Plot for memristor electrical characterization and evolution of programming voltage with oxide
thickness (a) memristor I-V with thickness 42 nm (b) 29 nm (c) strong dependence of programming voltage
upon switching layer thickness
57
4.4.3 Dispersion for Subsequent Switching
Proposed bilayer lithium niobate based memristor device shows some dispersion,
switching from cycle to cycle. Three different memristor devices having same overlap area (7.50
μm2) were characterized using repetitive sweep bias as plotted in figure 3.14 through 3.19
mentioned in the previous chapter. There, figure 3.14 shows cycle to cycle or intra-device
variability observed from a bilayer lithium niobate based memristor device. Such response is
applicable for filamentary switching according to the research work mentioned in [99] for
resistive switching devices. This would indicate that, application of repetitive sweep bias induces
random filaments responsible of memristor’s off state conductivity. The results explained in
section 4.4, demonstrates existence of filamentary resistive switching from the proposed bilayer
(Pt/LiNbO3-x /LiNbO3 /Pt) memristor device. Hence filamentary switching due to ETAT has been
suggested to be the dominant charge transport process; analyzing suitability of probable other
filamentary conduction mechanism for our memristor device in the following sections.
4.5 Hypothesis for the Proposed Charge Transport Mechanism
In its stoichiometric state, LiNbO3 is a wide band gap semiconductor [100]. This has been
utilized as memristor switching layer incorporating an oxygen deficient thin film during
deposition. Knowledge of electrical characterization and conduction properties through memristor
is very useful in optimizing the devices for various applications mostly for neuromorphic
architecture. In this regard, energy band diagram for the MIM structure has been analyzed first.
According to the cross-sectional structure mentioned in figure 3.6.a. a thin layer of titanium has
been added to promote adhesion. Thickness of the titanium layer in both the cases was small
compared to the platinum electrode used as both the top and bottom electrodes. Also, the work
function value for titanium is 4.33eV which is little less than the work function value of platinum
which is 6.35eV. The bottom electrode layer combination is (Ti/Pt) as deposited on the
polycrystalline silicon di oxide substrate. This means platinum is in direct contact with the sub-
58
stoichiometric oxide layer. Hence for the electrons tunneling from the cathode towards the defect
within switching layer impact of work function of platinum is significant. Therefore, while
drawing the energy band-diagram for the memristor device, only platinum has been considered
according to the effect of work function values and the order of the thin film layers as shown in
the cross-sectional view for the bilayer lithium niobate based memristor device.
Figure 4.10 shows work function values for different thin film layers within the
memristor device. This is shown with a rectangular potential barrier at flat band case. Here, 𝐸𝐸𝑜𝑜 is
the vacuum energy level, 𝜒𝜒 is the oxide electron affinity and ɸ stands for metal work function
[100]. Also, 𝐸𝐸𝑏𝑏 refers to the barrier height at the electrode-oxide interface under flat band
condition. Barrier height 𝐸𝐸𝑏𝑏 = E1 is evaluated as 4.23 eV which is realizable from the plot in
fig.4.10.
Figure 4.10. Energy Band diagram for bilayer Lithium niobate based Memristor device at Flat band condition
Charge transport through metal-insulator-metal structure can be divided mainly into two
groups; first one is electrode limited or non-filamentary conduction and the second category is the
bulk limited or filamentary conduction mechanism [101]. Approximation for either transport
59
mechanism requires study of memristor electrical characterization with modulation of device
dimension. Analysis of device conductivity requires adequate understanding of electronic effect
upon energy band diagram. This report analyses memristor charge transport mechanism
segmenting device conductivity for off and on states in other words high and low resistive states
respectively. First, memristor off state conduction has been investigated. Memristor device is
subject to two different current levels as per electrical characterization mentioned earlier.
Leakage or off state current is suggested to be responsible for intermediate resistive states within
nonvolatile memory device. Poole Frenkel (P-F) emission was claimed to be a dominant
conduction mechanism within Si-LiNbO3 heterostructure fabricated by the sol-gel method and
the ion-beam sputtering method [102]. P-F emission is a means by which an electrical insulator
can conduct electricity. Electron trapped within localized states can achieve energy from thermal
fluctuation and move to the conduction band. Charge transport equation for this mechanism
abides by the current-voltage equation mention as in eqn. 4.12.[103].
𝐼𝐼~𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 (𝛽𝛽𝑃𝑃𝑃𝑃 √𝑉𝑉−𝜙𝜙𝑃𝑃𝑃𝑃 𝑘𝑘𝑘𝑘) (4.12)
I and V carry usual meaning of device current and applied bias and k is the Boltzmann’s
constant. 𝜙𝜙𝑃𝑃𝑃𝑃 is the barrier height an electron needs to overcome and move to the oxide
𝑞𝑞
conduction band. The parameter 𝛽𝛽𝑃𝑃𝑃𝑃 is the P-F coefficient which is defined as � . Here 𝜀𝜀𝑜𝑜 is
𝜋𝜋𝜀𝜀𝑜𝑜 𝜀𝜀𝑟𝑟
the dielectric permittivity of free space and 𝜀𝜀𝑟𝑟 is the relative dielectric constant for the dielectric
used within the MIM structure.
60
Figure 4.11. Standard Logarithmic plot for Conductivity modulation as per Poole Frenkel emission
mechanism
Poole Frenkel emission current density is inversely proportional to the oxide thickness
and it is exponential to the barrier height. Such emission is also temperature dependent, because
thermal excitation can drive an electron over an activation barrier from one trap site to another.
Another research group reported F-N emission for LiNbO3 hetero structure at low temperature
[104]. They claimed that F-N tunneling was dominant due to the presence of deep traps (Et~ 0.93
e V) in the conduction band of LiNbO3 reported thermally activated bulk conductivity with
activation energy of EA= 1.17 e V which was suggested to result from deep donors within lithium
niobate bandgap. Fowler-Nordheim tunneling can be ruled out for our bilayer (Pt/LiNbO3-x
/LiNbO3 /Pt) memristor device as it requires very high electric field (~MeV/cm) along thin
(<20nm) dielectrics. Tunneling takes place directly from cathode to anode in case of Fowler-
Nordheim tunneling.
4.5.1 Investigation of Poole-Frenkel Emission for Memristor Off State
Different studies consider Poole-Frankel (P-F) emission as the principle conduction
mechanism along high resistive state (HRS) through high k dielectrics. Previous literature review
[105] explained memristive effect within LiNbO3 based hetero structures with the motion of
positively charged ‘Li+’ ion as mentioned in [95]. Based on literature sources, initially P-F
61
emission has been scrutinized for its suitability as the transport mechanism through HRS region
of our memristor device. According to the standard quantitative expression for Poole Frenkel
conduction approach, the plot for device conductivity-applied bias curve should be linear.
Fig.4.12.a. shows fitting results for ln(𝐼𝐼/𝑉𝑉) versus √V at high resistance state. It is clearly
observed, at very high resistance state (along Read Voltage) ln(𝐼𝐼/𝑉𝑉) versus (√V) does not show
the desired linear relationship for P-F approach. Figure 4.12.b. shows variation of ln(𝐼𝐼/𝑉𝑉) at
different temperatures (1/𝑘𝑘𝑘𝑘) at various bias conditions. It is found that, the experimental data
shows significant deviation with the prediction of Poole-Frenkel conduction at low bias (HRS)
region. Slope of the plot from figure 4.12.b. should provide activation energy (EA) for the
switching layer. Now obtaining the device activation energy under different bias condition, figure
4.12.c is plotted. The slope of figure 4.12.c provides the value of oxide dielectric constant used
for the proposed memristor device. From the fitted graphs for Poole Frenkel conduction, value of
relative dielectric constant is obtained as ~2.7242 Fm-1 which is much less than the known value
28.5 [106] for LiNbO3. The vertical intercept of the plot in figure 4.12.c provides the value of
estimated trap energy level for the device under consideration, which is found as 0.103 eV. This
implies existence of very shallow trap level below oxide conduction band. Also, the
experimentally known value of activation energy for lithium niobate varies from 1 to 1.20 eV
[107]. This shows much deviation from the fitted plots using Poole-Frenkel approach. Hence
these two unrealistic values for device parameters (activation energy EA, relative dielectric
constant ɛr) make the Poole-Frenkel conduction mechanism most unsuitable for the proposed
memristor device’s charge transport process. Also, there have been some disagreements whether
it is the leakage current density or the conductivity that should be dependent upon electric field.
Unphysical values of defect energy levels and device parameters (i.e. static electric permittivity)
obtained from the plot of P-F emission model, makes it unreasonable as the primary conduction
mechanism through memristor for the high resistive conductivity.
62
(a) (b)
0.11
0.1
0.09 E = 0.102 eV
t
Bias= 0.10 V
0.08
(eV)
= 2.7242
A
0.07 r
E
(c)
0.06
0.05
0.04
0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65
sqrt (V) √ V
Figure 4.12. Verification of Poole Frenkel emission for Memristor high resistive state (HRS) (a)
logarithmic plot for memristor conductivity with square root of applied bias (b) conductivity modulation
for low bias state with temperature variations (c) plot for electron activation energy with bias voltage. Y-
intercept for the plot provides extracted deep trap energy level assumed to be responsible for P-F emission
during HRS
4.5.2 Investigation of Schottky Emission for Memristor Off State Conductivity
Next we investigated the possibility of electrode-oxide interface modulation due to the
accumulation of defects/oxygen vacancies and thus contribute to the existence of the Schottky
emission. Interfacial or homogeneous switching mechanism has been explained as the
modification of Schottky barrier height between the electrode and the switching layer when
defects are attracted to the metal layer through the application of external bias. According to the
Schottky emission, memristor current density (J) can be expressed as in equation 4.13 [108]
63
−𝑞𝑞Ф𝐵𝐵 𝑞𝑞𝑞𝑞
𝐽𝐽 = 𝐴𝐴∗ 𝑇𝑇 2 exp � � exp( ) (4.13)
𝑘𝑘𝑘𝑘 𝑘𝑘𝑘𝑘
Where 𝐴𝐴∗ is the Richardson’s constant, T refers to the experimental temperature and Ф𝐵𝐵 is for
𝐼𝐼 1000
Schottky barrier height. A straight line (linear change) on a ln ( 2 ) vs ( ) plot for any applied bias
𝑇𝑇 𝑇𝑇
serves as strong evidence of Schottky emission. Plots within figure 4.13. investigated the possibility
of Schottky emission for memristor high resistive state (HRS).

-19
-19.5 0.10 V
0.40 V
))
-20
2
(A/K
(a)
-20.5
2
ln(I/T
-21
-21.5
-22
2.7 2.8 2.9 3 3.1 3.2
-1
1000/T (K )
-20 10.5
o
25 C
o
-21 95 C 10
)
)
2
-2
-22
)(A/k
9.5 Slope= -q( B

-V/n)/2.3k B
-2
-23
(b)
2
(c)
J/T 2 (Am
ln(I/T
9
-24
V= 0.1 volt
-25 8.5
-26
8
0 1000 2000 3000 4000
2.7 2.8 2.9 3 3.1 3.2
-1
E 1 / 2 (V/m) 1 / 2 1/T (K 10
-3
)
Figure 4.13. Fitting results for Schottky emission for bilayer lithium niobate based memristor device (a)
logarithmic plot for HRS current with variation of temperature (b) logarithmic plot for off state current with
variation of electric field (c) extraction of Schottky barrier height as per definition mentioned in eqn. 3
Figure 4.13. a. completely deviates from the condition for Schottky process. In other words, to
satisfy the Schottky emission, variation of plot of device current with that of electric field
irrespective of any temperature should be linear. Figure 4.13. (b) correlates the projected parameters
(ln (I/T2) with that of (E1/2) both for room temperature and 95oC measurement. Rather, exponential
64
change was observed from the plot which deviates from the definition of Schottky emission. To
further justify this Schottky emission for memristor off state conductivity, we determined the
Schottky barrier height from the plot in figure 4.13. (c). As per fitting results, Schottky barrier
height evaluated from the slope of figure 4.13. (c) was found as 0.005 eV. Such unrealistic value of
interface layer evaluated from the fitting results demonstrated within figure 4.13. delineates
inapplicability of the Schottky mechanism for the proposed bilayer lithium niobate based memristor
device along off state.
4.5.3 Investigation of Elastic Trap Assisted Tunneling for Memristor Off State
Direct tunneling applies well in case of ultra-thin the oxide layer (<10 nm). This
mechanism can be ignored for our memristor device having 42nm thickness. Schottky emission is
the thermally induced flow of charge carriers over a potential barrier. Impact of temperature
variability has also been studied from electrical characterization. Modulation of resistance states
were studied from a 7.50 µm2 memristor device. Triangular sweep bias having identical amplitude
has been applied to characterize the memristor device. Device temperature was elevated up to 95oC
staring from 35oC. Fowler Nordheim (F-N) tunneling [109] would be dominant where very high
electric field (108>> MeV/cm) acts upon the device. According to the electrical characterization
results mentioned within sections 4.5.1 and 4.5.2 both the Schottky emission and (P-F) mechanism
can be ruled out for the bilayer memristor device presented here. Ohmic conduction is applicable
when device is completely conducting and there is linear relationship between current and applied
bias. Considering these, steady state Elastic Trap Assisted Tunneling (ETAT) mechanism is chosen
to be investigated as the dominant carrier transport mechanism during memristor off state. Fig.
4.14. demonstrates modulation of memristor energy band diagram under triangular sweep bias
condition. Barrier height Eb has been evaluated as 4.20 eV which is essentially a higher value (>1 e
V) for the metal-dielectric interface. During memristor off state condition, charge carriers (here
electrons) do not gain enough energy to travel over such larger barrier. Probability of quantum
65
mechanical tunneling through the interface has been taken into consideration which would explain a
steady state conduction process.
Conduction
Eb BandE Electron (Vacuum Level)
c affinity Eo
(Barrier
qϰ
Height)
E e-1 (i) E
fL t
Energy Bottom Metal Pt Trap/

d'
(eV) (Cathode) defect Fermi
Ev (ii) Level Ef
Valance E fR
Band
Oxide Top Metal Pt
a = 0 nm (Anode)
b=42 nm
L=42 nm
x nm
Distance (nm)
Figure 4.14. Modulation of memristor energy band diagram under external bias condition, supporting two
step ETAT mechanism.
This tunneling would take place from the bottom electrode towards an unoccupied trap or
oxide defect. Within band diagram Et denotes the defect (trap) energy level and 𝑑𝑑′ is the distance
between the bottom electrode and the nearest trap. Arrows from left to right indicate the net flow
of charge carriers through the positively charged oxygen ions (traps/defects). Tunneling of charge
carriers under the applied bias condition can be described in two steps. In step (i), electrons from
the bottom electrode (cathode) travel towards the nearest trap position within the oxide switching
layer. In this case, the trap level is at a distance from the cathode and at an energy level below the
oxide conduction band minima. In step (ii) electrons transit from the defect towards the top
electrode (anode). The transmission probability of an electron (T'), tunneling from the cathode is
evaluated using the standard Wentzel-Kramer-Brillouin (WKB) approximation [110],[111] as
shown in equation (4.15).
4 3� 3�
𝑇𝑇 ′ = exp �− �2𝑚𝑚𝑒𝑒𝑒𝑒𝑒𝑒 �𝐸𝐸𝑡𝑡 2
− (𝐸𝐸𝑡𝑡 − 𝐹𝐹 ′ . 𝑑𝑑′ ) 2 �� (4.15)
3ℎ𝑞𝑞𝐹𝐹 ′
66
where ħ is the reduced Planck’s constant, q is the charge of an electron, F' is the electric field
influencing the charge carriers, and 𝑚𝑚𝑒𝑒𝑒𝑒𝑒𝑒 is the effective mass of an electron. The transition rate
of the charge carriers (𝑣𝑣1 ) has been estimated using eqn. (4.16).
𝑣𝑣1 = 𝑣𝑣𝑜𝑜 . 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 . 𝑇𝑇 ′ (4.16)
𝑣𝑣𝑜𝑜 is the characteristic vibration frequency of a trap within the oxide layer, which is equal to
1013 Hz [112]. Here, 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 denotes the Fermi Dirac distribution [113] for electrons residing in
the bottom electrode. The probability that an empty energy state will be filled by an electron from
the cathode is mathematically expressed in Eqn. (4.17),
1
Ffermi = E −E −F′ .d′
(4.17)
�1+exp� b t ��
kT
Again, the transition rate 𝑣𝑣2 of electrons from the nth trap towards the anode is evaluated
using eqn. 4.18 as follows.
𝑣𝑣2 = 𝑣𝑣𝑜𝑜 . �1 − 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 �. 𝑇𝑇 ′ (4.18)
Here �1 − 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 � refers to the de-trapping probability of charge carriers responsible for
current conduction. Current ‘I’ in both polarity cases is simulated using eqn. 4.19
𝐼𝐼 = 𝑁𝑁 ′ . 𝑞𝑞. 𝑣𝑣 ′ (4.19)
The term 𝑣𝑣 ′ is the transition rate of electrons through the oxide-electrode interface (𝑣𝑣1 for
charge trapping and 𝑣𝑣2 for charge de-trapping). 𝑁𝑁 ′ is the total trap density within memristor
switching layer. As per the ETAT mechanism, activation energy (EA) of electron can be
approximated using equation 4.20.
�Eb −Et −F′ .𝑑𝑑 ′ �

𝐸𝐸𝐴𝐴 = kT
(4.20)
67
Work Ec
function e-1
qФB e-1
Bottom
Metal Oxide
Ev Top
Metal
Figure 4.15. Modulation of memristor energy band-diagram due to Ohmic Conduction
After the set /programing voltage, the memristor device is in a highly conductive state.
Room temperature current voltage characterization shows almost linear relationship which would
suggest ohmic conduction for memristor’s on state or low resistive state (LRS) for room
temperature measurements. Such linear change of device current was observed for memristor
LRS for low bias conductivity. As the applied bias is increased, strong non-linearity for
memristor LRS current was observed for high temperature measurements. Such change in
conductivity was reported by Chu et.al. in [84] demonstrating modulation of device conductivity
from ohmic to SCLC mechanism. The current density (J) for Ohmic conduction can be expressed
as in eqn. 4.21[85]
𝐸𝐸𝐴𝐴
𝐽𝐽 = 𝑞𝑞𝑞𝑞𝐹𝐹 ′ 𝑁𝑁 ′ exp � � (4.21)
2𝑘𝑘𝑘𝑘
Here μ and N' are the electron mobility and trap density respectively. Summary of various
conduction mechanisms and their applicability to the two-layered memristor device are shown in
Table 4.3.
68
Table 4.3: Summary of Suitability of Dominant Charge Transport Mechanism through Memristor
Device
Conduction Relationship between device response and applied Investigation of the

Mechanism stimuli charge transport mechanism for
bilayer lithium niobate based
memristor (Pt/LiNbO3-x
/LiNbO3 /Pt) device
1. Interfacial or
Non filamentary
Conduction[101]
1.a. Schottky/ −𝑞𝑞Ф𝐵𝐵 𝑞𝑞𝑞𝑞 Unsuitable for HRS
Thermionic 𝐽𝐽 = 𝐴𝐴∗ 𝑇𝑇 2 exp � � exp( )
𝑘𝑘𝑘𝑘 𝑘𝑘𝑘𝑘
emission [83]
1.b. Fowler- 1 Applicable for very high
8𝜋𝜋(2𝑞𝑞𝑚𝑚∗𝑇𝑇 )2 32
Nordheim 𝐽𝐽 ∼ exp � Ф𝐵𝐵 �
3ℎ𝐸𝐸 electric field in the range of
tunneling [80]
108>>MeV.
1.c. Direct 3
3 ⎫ Direct tunneling is
⎧
tunneling [79] 4 �2𝑚𝑚∗ Ф2𝐵𝐵 𝑞𝑞𝑞𝑞 2
𝐽𝐽~ exp − �1 − �1 − � � applicable for oxide thickness
⎨ 3 ℏ𝑞𝑞𝐹𝐹 ′ Ф𝐵𝐵 ⎬
⎩ ⎭ less than 10 nm.
2. Bulk or
Filamentary
Conduction[99]
2.a. Trap-Assisted Elastic trap assisted
Tunneling [84] 1
𝐼𝐼~ � � tunneling mechanism without
Eb − Et − F ′ . d′
�1 + exp � ��
kT phonon assisted effect was
4 3� found most dominant for the
�exp �− �2𝑚𝑚𝑒𝑒𝑒𝑒𝑒𝑒 �𝐸𝐸𝑡𝑡 2
3ℎ𝑞𝑞𝐹𝐹 ′ bilayer lithium niobate based
3�
memristor device for HRS
− (𝐸𝐸𝑡𝑡 − 𝐹𝐹 ′ . 𝑑𝑑′ ) 2 ��
conductivity; as per the fitting
results shown.
2.b. Poole-Frenkel 𝛽𝛽𝑃𝑃𝑃𝑃 √𝑉𝑉 − Ф𝑃𝑃𝑃𝑃 P-F emission was

emission [102] 𝐼𝐼~𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 � �
𝑘𝑘𝑘𝑘 investigated as unsuitable
mechanism for memristor HRS
2.c. Ohmic 𝐸𝐸𝐴𝐴 Suitable for LRS @ 25oC

𝐽𝐽 = 𝑞𝑞𝑞𝑞𝐹𝐹 ′ 𝑁𝑁 ′ exp � �
conduction [81] 2𝑘𝑘𝑘𝑘
2.d. Space Charge 9 𝐸𝐸 2 Applicable for non-linear

Limited 𝐽𝐽 = 𝜀𝜀µ𝜃𝜃
8 𝑑𝑑 increase of LRS current at high
Conduction
(SCLC) [85] bias for 95oC temperature
measurements.
69
CHAPTER 5
VERIFICATION OF PROPOSED CONDUCTION MECHANISMS
5.1 HRS Simulation for Room Temperature Measurement
Conduction mechanisms mentioned in chapter four will be verified through appropriate
simulation using the experimental values from memristor electrical characterization. In this case,
device characterization both for room temperature and different elevated temperatures will be
taken into consideration. Standard equations for different electronic conduction along different
resistive states will be utilized as mentioned in Table 4.3. While doing the simulation, extracted
device parameters will be verified to the existing values reported in previous literature [82, 102].
Elastic Trap Assisted Tunneling mechanism has been applied for memristor off state both for
room temperature and different elevated temperature measurements. As per experimental values
at room temperature, projected lithium niobate based memristor device was found to conduct
abruptly at around 1.20 V. In this case memristor off state or high resistance state is considered
up to 0.350 V. ETAT simulation result considering electron effective mass ~ 0.05mo and trap
density of ~1019 cm-3 as fitting parameter has resemblance with that of the one found in previous
literature [114]. Existence of deep unfilled/acceptor trap level at around 1.145 eV below the
oxide conduction band is estimated to be responsible for charge transport during memristor off
state . Figure 5.1 shows ETAT simulation results for memristor HRS conductivity for 25oC and
95oC measurements.
70
Figure 5.1. ETAT Simulation results for memristor high resistive state both for positive and negative polarity.
Experimental values are showed using the dotted points and simulated values are mentioned with line within
the plot.
5.2 HRS Simulation for Elevated Temperature Measurements
Analysis of a solid-state device based only upon room temperature measurements is not
enough. Next simulation result contains validity of ETAT conduction process using lithium
niobate based memristor device for 65oC and 95oC measurements respectively. Experimental data
are plotted with dotted points whereas simulated values are plotted with dashed line. Figure 5.2
shows simulation results using ETAT mechanism for memristor HRS both for positive and
negative bias. During simulation, fitted parameters for deep trap profile was found to be
comparable as obtained for the room temperature simulation results.
(a) (b)
Figure 5.2. ETAT simulation results for memristor HRS at 65oC for (a) positive and(b) negative bias
measurements respectively
71
(a) (b)
Figure 5.3. ETAT simulation results for memristor HRS at 95o C for (a) positive and(b) negative bias
measurements respectively
Combined plot for ETAT Simulation during memristor off state for three different
temperatures maintaining the same experimental condition are plotted in figures 5.1 through 5.3.
From the simulation results it is obvious that memristor HRS or off state current is not strongly
dependent upon thermal variation. This justifies, the existence of deep trap along the same energy
level, dominates the electron/carrier transport for memristor HRS.
-4 -4
10 10
3 3.5
3
2.5
2.5
2
2
(a) (b)
Current (A)
Current (A)
1.5
1.5
1
1
0.5
0.5
0 0
0.1 0.2 0.3 0.4 0.5 0 0.2 0.4 0.6
Applied Bias (V) Applied Bias (V)
Figure 5.4. Combined plot for ETAT simulation for lithium niobite based memristor during device off state
maintaining (a) room temperature 25oC (b) 95oC compared with experimental results (all dotted points
correspond to measured values and line drawn correspond to the simulated values within the plot)
72
To further justify the ETAT process; activation energy of electron is retrieved using
equation 4.20. Considering fitted values for deep trap level at around (Ec - 1.145) eV and at a
distance 6.258nm from the cathode terminal; activation energy for lithium niobate is estimated
and plotted against the variation of electric field. This is shown in figure5.5.
1.15
(eV)
1.1
A
Activation Energy E
1.05
0.95
0 1 2 3
-1
7
Electric Field F (Vm ) 10
Figure 5.5. Plot for Electron Activation energy with variation of electric field
Estimated activation energy of electrons using ETAT mechanism is close to the known
value (~1.20 eV) from literature [115]. Reasonably good agreement is achieved between
experimental data and the approximate response for carrier transport using ETAT conduction
during memristor off state. Reasonably good agreement is achieved between experimental data and
the approximate response for carrier transport in the memristor off state (HRS). It is clear from the
ETAT simulation, memristor off state conductivity is not affected by thermal variation, rather it is
the existence of unfilled deep trap energy level, which initiates electron tunneling from the cathode
terminal.
5.3 ETAT Simulation Results Up to Turn Over Voltage
Threshold or turn over voltage is the amount of bias voltage required to completely turn
the device on; which can be considered as the memristor set voltage as well. As per dc
73
characterization obtained from bilayer lithium niobate based memristor device, change of
measured current values follow an exponential change initiating from the very high resistive state.
Simulation results till memristor turn over voltage have been demonstrated within figure 5.6
using the elastic trap assisted tunneling mechanism, without taking the phonon emission effect
into account. Transition of device current profile have been plotted in figure 5.6 a and b for
positive and negative sweep bias respectively.
-3 -3
10 10
4.5 0
Experimental values Experimental values

4 Simulated values -0.5 Simulated values
3.5
-1
3
-1.5
2.5
Current (A)
Current (A)
-2
-2.5
1.5
-3
1
-3.5
0.5
0 -4
0 0.2 0.4 0.6 0.8 1 1.2 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0
Applied Bias (V) Applied Bias (V)
Figure 5.6. Simulation results for memristor HRS up to Turn over voltage using ETAT process for (a)
Positive (b) Negative polarity bias
5.4 LRS State for Variable Temperature
Having linear change with device current and applied bias, ohmic conduction was investigated
for the room temperature measurements at memristor low resistive state. As per ohmic conduction,
plot for applied bias and device current should show a linear change. Figure 5.7 shows plot for
experimental values for memristor low resistive state. Plot of on state device current with that of
thermal variation using seven distinct marked levels have been demonstrated here. At high bias
high temperature, memristor on state current deviates from unity slope.
74
-5
o
95 C
-6 o
85 C
o
75 C
-7 o
65 C
o
55 C
-8 o
45 C
o
35 C
-9
ln(I)
-10 (a)
-11
-12
-13
-14
-7 -6 -5 -4 -3 -2 -1 0
ln(V)
Figure 5.7. Plot for current voltage change for memristor low resistive state only
5.5 LRS Simulation for Variable Temperature Measurements
Next step is to justify memristor on state conduction both for room temperature and
different elevated temperature measurements. As per experimental values, on state at higher
temperatures showed exponential change with applied bias. In this case the slope from I-V
characterization does not comply with the condition for the ohmic conduction mechanism.
Exponential change of on state current could be due to influence of some thermal effect.
Tunneling of charge carriers have been considered from cathode towards oxide bound state. This
follows emission from the bound state towards the oxide conduction band minima and finally
from the CBM to the anode for the MIM device. As per the expression for ohmic conduction [81]
mentioned in equation. 10, a plot for memristor on state current with an applied bias shows almost a
linear behavior (with a slope of ~1) at room temperature as in fig. 5.8 (a). Dotted points indicate
measured on state device current whereas simulated values of current using ohmic conduction are
plotted with the red line here. Slope of the logarithmic plot of voltage with respect to current was
found around ~1 which is a prerequisite for establishing linear relationship between the two
parameters. Fitted value of electron mobility was found as μ= 25 cm2 V-1 s-1 which is little higher
than the one found from [116] . Simulation result for 95oC measurements is shown in fig. 5.8(b)
75
which demonstrate ohmic conductivity applicable for memristor low bias, low resistive state. Strong
non-linearity with on state current at high bias was observed according to the experimental current
values. This could be due to dominance of thermal effect combining high electric field for the
memristor’s LRS. Elevated temperature at 95oC (for LRS) could enhance the carrier density which
would cause more rapid change of memristor conductivity along the high bias region.
-5 -8
-6
-9
-1 -1 -1 -1
-7 2 s 2 s
= 25 cm V = 21.5 cm V
-10
-8 slope~1 slope~1
-9 -11
ln(I)
ln(I)
-10
-12
-11 (a) (b)

-13
-12
-13 -14
-6 -4 -2 0 -6 -5 -4 -3 -2
ln(V) ln(V)
Figure 5.8. Simulation results using Ohmic conduction for Memristor device at highly conductive state for
(a) room temperature (b) 95oC compared with experimental results (all dotted points correspond to
measured values and line drawn correspond to the simulated values within the plot)
Beyond the low bias (0.25 V) region the memristor LRS conductivity shows strong non-
linearity at high temperature (95oC). Such non-linearity at high bias region can be attributed to the
influence of space charge limited current (SCLC) where the current voltage parameters abide by the
relation (I-Vn; where n is greater than 1). According to SCLC, injected carrier density overtakes the
thermally generated ones which cause strong non-linearity for high bias LRS current (95oC). Fitting
results for SCLC mechanism has been plotted in figure 5.9 using the equations shown as (4.7) and
(4.8) . According to the SCLC mechanism slope from the plot in figure 5.9.a. should be close to 2,
in our case the slope is 1.63.Such a change in conduction from ohmic to SCLC at high bias was also
76
reported by D.P. Chu et.al. in [84]. Fitted values for electron mobility obtained from the LRS
simulations are slightly higher than the one found by Ohmori et al. [116].
-3
10
4
3.5
n
I-V
3
n=1.63
2.5
Device Current I (A) 2
1.5
0.5
0
0.2 0.4 0.6 0.8 1
Applied bias V(V)
Figure 5.9. SCLC simulation result for memristor LRS conductivity at high bias , high temperature; linear
change of device current with applied bias (all black dotted points correspond to the experimental on state
current and the red line drawn indicates simulation result using SCLC process
Our research considers electronic contribution while analyzing the conductivity
mechanism through a bilayer lithium niobate based memristor device. According to the
simulation results existence of unfilled deep trap energy level was found responsible for memristor
HRS conductivity mechanism. Another shallow trap energy level within memristor switching layer
was found to promote low resistance state conductivity. Our proposed steady state analytical model
exhibits the dominance of defect or trap energy level (deep and shallow trap) within memristor
switching layer accountable for charge transport mechanism both for high and low resistance
region. The trap density was estimated as ~1019 cm-3 for the HRS ~ 1021 cm-3 for the LRS
conductivity. Hence it is the trap assisted tunneling which is found the most significant for the
proposed memristor’s charge transport mechanism. Existence of inhomogeneously distributed
unfilled trap/defect energy levels below the oxide conduction band initiate the filamentary
77
conduction through the proposed memristor device. Tabular representation for all the fitting
parameters both for memristor HRS and LRS is populated in the table 5.1.
Table 5.1 : Tabular representation of fitting parameters for a bilayer lithium niobate based memristor
device
Symbol Fitting Parameter Fitted Value Unit
meff Electron Effective 0.05 mo kg

Mass mo = 9.1x10-31
μ Electron Mobility 25 cm2 V-1s-1
Nʹ Trap Density ~1019 cm-3
ET Deep Trap Ec -1.145 eV
dʹ Trap distance 6.2581 nm
Table 5.2: Tabular representation of fitting parameters using SCLC mechanism
Fitting Parameters Symbol Value Unit
Relative Dielectric εr 27.5

Constant
Electron Mobility µ 21.5 cm2 V-1 s-1
Injected Carrier Nc ~ 1021 cm-3

density
Activation Energy Eac 0.48 eV
5.6 Experimental Results for Off State Conductivity using Pulse Measurement
Next experimental results demonstrate feasibility of the lithium niobate based memristor
as a neuromorphic device. Programming protocol mentioned in [117] has been followed here to
78
investigate the proposed memristor’s controllability. A series of positive voltage pulses (1.2 V, 17
ms) or negative voltage pulses (-1.2 V, 17ms) with uniform time interval were applied on the
memristor. Device conductance was measured by a reading voltage pulse (0.2 V, 17 ms)
immediately after each programming pulse. After sixty (60) pulses in both the cases there was
transition from device off state towards different intermediate resistance states. Up to 150 pulses
memristor device sustains its resistive saturation level. Applied experimental condition has been
shown using figure 5.10.
Read= 0.20 V Set = 1.20 V

150 Pulses
17 ms
…….. …….. Time
17 ms
150 Pulses
ReSet =-1.20 V
Figure 5.10. Experimental condition applied for analog programmability from memristor device
Precise analog control was achieved from the bilayer lithium niobate based memristor
device as illustrated within fig. 5.11.b. Such experimental result was found analogous to the
potentiation and depression phenomena observed within human brain [118], [119]. Gradual
increase (Potentiation) and decrease (Depression) of memristor conductivity emphasizes
existence of analog/multiple resistance states during memristor off state.
While characterizing the pulse dependent multilevel resistance states, we were also
interested in determining the number of pulses required for saturation level of device conductivity
after the potentiation phenomena. To avoid excitability of neurons, potentiation of synaptic
weights should possess a saturated value. Also, according to the experimental condition applied
for pulse measurements in figure 6.15, pulse width utilized both for read and write process have
been considered equal (17 ms). This causes some non-linearity in the read current region. Such
79
non-linearity can be reduced at a larger scale by modulating the read pulse width much higher
than the write pulse as reported by Zhang et. el in [139]
-3 -4
10 10
5 1.8
1.6
1.4
Read Current (A)

Current (A)
(a) 1.2
(b)
-5 0.8
-1 0 1 0 100 200 300
Applied Bias(V) No. of Pulses
Figure 5.11. Evidence of Analog Switching from proposed bilayer lithium niobate based memristor having
overlap area of (7.50 µm2) (a) dc characterization from memristor device at room temperature (b) precise
analog control (gradual resistive switching) achieved from memristor device suggesting analogy with
potentiation (increase of resistance states) and depression (decrease of resistance states) phenomena within
human brain.
5.7 ETAT Simulation Result for Multi level Conductivity along HRS
Existence of multiple, analog resistivity is an essential attribute for neuromorphic device.
This supports increased (reset) and decreased (set) device conductivity along memristor HRS.
Conductivity modulation from the bilayer lithium niobate based memristor device for the off state
has been simulated using the ETAT mechanism as shown in figure 5.12. This has been achieved
by changing the distance d' for the nearest (defect) trap energy level from the cathode terminal
while all other device parameters (trap density, electron effective mass and deep trap energy
level) remain the same. In this regard, value of d' was varied from 7.78 nm to 4.45 nm. Multiple
distinct resistance levels for memristor off state conductivity have been simulated by varying the
trap distance (d') only.
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-4
10
1.8
1.6
1.4
Read Current (A)

1.2
1
Experimental values
Simulated values
0.8
0 50 100 150 200 250 300
No. of Pulses
Figure 5.12. Potentiation and depression phenomena simulated with the variation of trap distance d' from
7.78nm to 4.45nm: ETAT simulation result applying identical pulse response for multi-level resistive
switching from memristor device at room temperature
The results in figure 5.12, confirms the multilevel resistive switching with off state
device current. Existence of multiple states along memristor off state ensures less power required
for information storage and processing [120]. Energy consumption per synaptic activity was
evaluated as ~1.69e-6 joule, as the external stimuli required for off state analog modulation was ~
0.20 volt and off state current was in the sub micro-ampere range. Approximation of ETAT
process for HRS and Ohmic conduction for LRS have been studied using two more memristor
devices of the same MIM combination. Figures 5.13 and 5.14 demonstrate simulation results
(ETAT for HRS and Ohmic conduction for LRS) using bilayer lithium niobate based memristors
having overlapped areas 5.0 µm2 and 2.50 µm2 respectively.
81
-3 -5
10 10
4 4 -6
(c)
2 (a) 3 (b)
-8
Current (A)
Current (A)
0 2
ln(I)
-10
-2 1
-4 0 -12
-1 0 1 0 0.2 0.4 0.6 -6 -4 -2 0
Applied bias (V) Applied Bias (V) ln(V)
Figure 5.13. Simulation of charge transport process from a 5 μm2 Memristor device at room temperature
(a) plot for current-voltage characterization (b) ETAT simulation result for HRS (c) simulation for Ohmic
conduction along LRS
-3 -5
10 10
4 2 -6
-8
2 (a) 1.5 (c)
(b)
-10
Current (A)
Current (A)
0 1
ln(I)
-12
-2 0.5
-14
-4 0 -16
-1 0 1 0 0.2 0.4 0.6 -6 -4 -2 0
Applied Bias (V) Applied Bias (V) ln(V)
Figure 5.14. Simulation of charge transport process from a 2.5 μm2 Memristor device at room temperature (a) plot for
current-voltage characterization (b) ETAT simulation result for HRS (c) simulation for Ohmic conduction along LRS
5.8 Validation of Charge Transport Mechanism using Experimental Results from Multiple
Devices
Proposed charge transport mechanism along sub threshold and conducting state has been
estimated using standard transport process within MIM structure. Device parameters have been
estimated using electrical characterization data from a memristor device having 25,10,7.5 and 5
µm2 as the overlap areas. More robust estimation was obtained by validating the simulation using
measured values from six other memristor devices maintaining the same experimental condition
and same overlapped area. Figure 5.15. (a) to (f) shows dc electrical characterization plot for
experimental data points. Experimental values are extracted at room temperature.
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(a) (b)
(c) (d)
(e) (f)
Figure 5.15. Electrical Characterization from Multiple Memristor Devices (a) through (f) maintaining room
temperature and similar experimental condition
5.9 HRS Simulation Results from Multiple Devices
To validate the approximation, six more memristor devices of the same combination and
geometry were characterized at room temperature maintaining the same experimental condition
as shown in figure 5.15. Applying ETAT conduction mechanism, HRS simulation results are
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(a) (b)
© (d)
(e) (f)
Figure 5.16. Simulation results for Elastic Trap Assisted Tunneling mechanism for the HRS region of
bilayer lithium niobate based memristor device (a) to (f). Here simulation has been done for six different
memristor devices of the same MIM structure where the same experimental condition has been maintained
84
plotted for six other memristor devices from the same combination. All the plots comprising
ETAT simulation results for six different bilayer lithium niobate based memristor devices have
been illustrated within figure 5.16. above. Experimental values of current are shown using dotted
points and the HRS simulated values are shown with straight line within each plot. Tabular
representation of the fitted parameters for trap profile are shown in table 5.3.
Table 5.3 : Tabular representation of Trap Energy level and trap distance values from Seven Different
Memristor devices at HRS maintaining room temperature are populated here.
Device No. Deep Trap Energy Level Trap Distance
𝐸𝐸𝑇𝑇1 (eV) 𝑑𝑑′ (nm)
1. Ec – 1.145 6.258
2. Ec – 1.098 6.314
3. Ec – 1.103 6.451
4. Ec – 1.069 6.446
5. Ec – 1.077 6.520
6. Ec – 1.104 6.631
7. Ec – 1.035 7.514
5.10 LRS Simulation Results from Multiple Devices at Room Temperature
Measured data for on state conduction was also investigated from more than one
memristor devices. Figure 5.17 below, shows plot for simulation using ohmic conduction for
three more memristor devices at room temperature. In each case double plot for device current
and applied bias is supposed to have a unity slope which is realized from the plots in figure 5.17.
Electron mobility for memristor on state has been estimated using equation (4.3) for ohmic
conduction. Tabular representation for value of electron mobility at room temperature has been
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extracted from four different memristor structures maintaining the same experimental condition
as presented in table 5.4.
(a)
(b)
(c)
Figure 5.17. Simulation for Memristor LRS or on state using the Ohmic Conduction process. Here
simulation has been shown for three more memristor devices collecting measured data at room temperature
(a), (b) and (c) simulation for three more different devices
86
Table 5.4: Tabular representation of fitted parameter from simulation for Ohmic conduction
Device No. Electron Mobility μ cm2V-1s-1
1 25.0
2 23.4
3 25.8
4 24.2
Average value of electron mobility is estimated as μ =24.5750 cm2V-1s-1 from the simulation
results mention in the table 5.4 for memristor on state conductivity.
5.11 Validation of Fitting Parameters using Statistical Tools
Validation for the prediction of device parameters from the proposed mechanism is essential.
Estimated simulation parameters will be verified using regression analysis [121]. Concept of 95%
confidence interval [122] has been utilized in this regard. Brief description of those statistical
attributes is given below.
5.11.1 Confidence Interval
Confidence Interval is an interval estimate so defined that, there is a specified probability that
the value of a parameter lies within it. It represents the precision of an estimate. For instance, 95%
confidence interval for our estimated parameters would signify; if we used the same sampling
method to select different samples and computed an interval estimate for each sample, we would
expect the true population parameter to fall within the interval estimates 95% of the time. In other
words, confidence interval for individual estimate will be evaluated using the relations for statistical
attributes shown below [123]:
𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼 (𝐶𝐶.𝐼𝐼)=𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃±𝑀𝑀𝑀𝑀𝑀𝑀𝑔𝑔𝑔𝑔𝑔𝑔 𝑜𝑜𝑜𝑜 𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸
Here proportion is the number of samples being utilized from the database.
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5.11.2 Calculation for Error Margin
Error margin or margin of error [124] is a statistic that expresses the amount of random
sampling error resulting in a survey. Lower margin of error indicates more likelihood of relying
on the results of a survey. In statistics margin of error has been defined as follows
Margin of Error=Critical Value x Standard Error of the Sample
5.11.3 Calculation for Critical Value
Critical value is a factor used to compute the margin of error. Critical value is specific to the
type of test and the significance level α which defines the sensitivity of the test [125]. A value of
α=0.05 indicates that a null hypothesis is rejected 5% of the time when it is true. Critical values
are essentially a cutoff value that define regions where the test statistic is unlikely to lie. Steps for
finding critical probability are shown as :
𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙
Compute α: 𝛼𝛼 = (1 − ( ))
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𝛼𝛼
Find the Critical Probability (p*): p* = 1-
2
To express the critical value as a z-score we need to find the z-score having a cumulative
probability equal to the critical probability (p*)
5.11.4 Calculation for Standard Error
Standard error of the estimate is a measure of the accuracy of predictions [125]. It is the
standard deviation of the sampling distribution of a statistic. Larger the sample size, smaller the
sample error is. Standard error explains how precise the mean of sample is, compared to the true
mean of the population. Standard error is calculated by taking the standard deviation and dividing
it by the square root of the sample size. Steps to evaluate standard deviation are as follows:
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 Calculate the number of measurements (n) and the sample mean (µ) of all the
measurements.
 Determine the deviation of each measurement from the mean
 Square all the deviations calculated in the previous step and add them together.
 Divide the sum of square of all the deviations from mean by one less than the total
number of measurements.
The square root of the result from the division provides the standard deviation of the sample.
5.11.5 R-Square
R-squared is a statistical measure [125] of how close the data are, to the fitted regression
line. Regression (R2) compares the distance between the actual values to the ‘mean’ with the
estimated values to the mean or the distance of the estimated value to the mean. R-square value
lies in between 0 to 1. Higher the R-square value, better the estimation.
5.11.6 SSE
SSE is the sum of the squared differences between [125] each observation (Xi) and its
group's mean 𝑋𝑋� It can be used as a measure of variation within a cluster. If all cases within a
cluster are identical, the SSE would then be equal to 0. The formula for SSE is:
𝑛𝑛
𝑆𝑆𝑆𝑆𝑆𝑆 = �(𝑋𝑋𝑖𝑖 − 𝑋𝑋�)2

𝐼𝐼=1
5.11.7 RMSE
Root Mean Square Error (RMSE) [125] is the standard deviation of the residuals
(prediction errors). Residuals are a measure of how far from the regression line data points are;
RMSE is a measure of how spread out these residuals are. Using all these statistical measures,
device parameters are estimated. Average estimated values for deep trap energy level and trap
distance are (Ec – 1.09) eV and 6.5906 nm respectively. Hence ETAT simulation result is verified
89
for seven different memristor devices having the same MIM structure and maintaining the same
experimental condition. Hence approximation for deep trap energy level has been validated from
seven different memristor devices using room temperature measurements.
5.12 Summary of device Simulation
Elastic Trap Assisted Tunneling mechanism has been applied for memristor off state both for
room temperature and different elevated temperature measurements. As per experimental values
at room temperature, projected lithium niobate based memristor device was found to conduct
abruptly at around 1.20 volt. In this case memristor off state or high resistive state is considered
up to 0.50 volt. ETAT simulation result considering electron effective mass ~ 0.050mo and trap
density of ~1019 cm-3 as fitting parameter has resemblance with that of the one found in previous
literature. Existence of deep acceptor trap level at around 1.145 eV below the oxide conduction
band is estimated to be responsible for electron transport from cathode during memristor off state.
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CHAPTER 6
CHARACTERIZATION FOR NEUROMORPHIC ATTRIBUTES
6.1 Background
Present day computers having von-Neumann architecture encompass physically separated
units for computation and information storage. Latency for data transfer between processing unit
and the memory unit bears a fundamental limitation of modern computers , named as memory
wall. On chip memory or in-memory computation with resistive switching devices using non-
von-Neumann architecture in considered to be an eminent approach to address this issue[126].
Different studies present variable memristor structure as the fundamental element for
neuromorphic architecture. Apart from having memory capability , incremental modulation of
device conductance makes this emerging electronic device named ‘Memristor’ suitable for
designing non-von Neumann computer architecture. The conductance-modifying process of
synapses are called potentiation and depression. Modulation of memristor off state conductivity
using repetitive pulse response was reported by several groups [127]. This denotes, synaptic
weight is being strengthened and weakened respectively. Chang et.al. demonstrates analog
resistivity obtained from a Tungsten oxide based memristor device for neuro-morphic
applications[128]. Another report by in [129] shows potentiation of depression phenomena
characterizing a (2µmx2µm) sized (Pd/TaOx/Ta2O5 /Pd) ReRAM device. Ultrafast synaptic events
in a chalcogenide memristor was reported by in [130]. Kim et.al reports synaptic behavior of a
silicon nitride memristor with the modulation of pulse width and amplitude[131].This dissertation
puts effort for verify analog conductivity from a bilayer lithium niobate based memristor device.
Following section briefly mentions several performance criteria for a neuro-morphic device.
91
6.2 Performance Metrics for Neuromorphic Device
Computation using neuromorphic device is like the computing scheme in the human brain.
There information is processed in sparse networks of neurons and synapses without any physical
separation between computation and memory. Hence such new architecture requires
computational memory devices which can store data and compute information at the same time.
Expectations from neuromorphic device is that, it will be a nonvolatile memory by totally
removing the latency and energy burdens of the memory wall. Major performance metrics for a
neuromorphic device are demonstrated below.
6.2.1 Device Dimension
Human brain contains (~1010) neurons having (~1014 synaptic connections. Physical size of
synaptic cleft is <~20 nm [132] with a density of synapses is >~109/mm3. Such large-scale neural
network can be emulated with a compact synaptic device having small device footprint. Hence
device scalability down to sub 10 nm regime is preferred. So far memristor devices fabricated
using different MIM structure have the minimum dimension of 2.50 μm2 as overlap area.
6.2.2 Ultra-low Power Consumption
Human brain consumes ~ 20 W power on an average. Hence the average energy
consumption per synaptic event is around ~10f J [132]. To achieve the same performance using
synthetic synapse, device should be designed in a way so that it ensures such ultra-low power
consumption.
6.2.3 Programming Time
Biological brain of human operates at an average frequency of 1~10 Hz or it takes 0.10s as
the programming time. Fast programming speed in the range of ~ns [132] from the memristor
devices would be able to provide lots of flexibility to design signaling scheme for implementing
learning rules.
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6.2.4 Repeatability
One of the most important criteria for designing synthetic synapse is to have the capability
for repeating the device electrical characteristics. Repeatability [132] of memory storage
phenomena for longer time, ensures robust non volatility of the electronic device. Undistorted,
repeatable response points towards device stability as well.
6.2.5 Analog Resistive Switching
Biological brain shows continuous change of synaptic weight states in between maximum
and minimum conductance states. These are named as intermediate resistive states. Existence of
multi-level states brings advantage in terms of robustness and network capacity. This is a very
important criterion for designing neuromorphic architecture. Overall power consumption can be
reduced if synaptic device is mostly cycled within intermediate resistive states [132].
6.2.6 Endurance and Retention
Data retention is the capability of retaining stored information over time. Endurance refers to
the durability of the medium on which data is stored. Again, long term memory within human
brain considers approximately 10 years of memory capability [132]. This can be replicated with
an endurance of 3x109 synaptic operations from a nonvolatile electronic device.
6.3 Techniques for Determining Multi-Level Resistive Switching
Different techniques have been adopted to explore multiple resistive states from memristor
device fabricated using either oxide or chalcogenide as switching layer. Both sweep and pulse
input dependent conductivity change have been investigated [133], [134]. Here the system
emphasizes on reproducible multilevel switching. Experimental verification of different
techniques would confirm memristor device stability as one of fundamental electronic circuit
components.
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6.3.1 Incremental Bias Dependent MRS
In this technique, memristor device undergoes repetitive sweep bias while maintaining the
compliance current level always the same . Experiment has been conducted at room temperature.
It can be assessed if the memristor device is able to produce stable hysteresis, it can retain a
specific resistive state till the reset voltage is applied. Forming free, sweep voltage dependent
multi-level resistive switching has been observed from both oxide and chalcogenide memristors
fabricated in our lab. First, experimental results from a bilayer Titanium oxide based memristor
device has been plotted here. By sweeping the applied stimuli from 0 to two higher positive
values, TiOx memristor was able to produce stable intermediate resistive states (IRS) in between
device HRS (binary 0) and LRS (binary 1) states. This IRS has been achieved from a TiOx
memristor where the neighboring resistive states maintain a resistance ratio of ~ 6. A current
compliance of 50μA was fixed to keep the memristor device safe from hard dielectric breakdown.
Same phenomena were observed along the negative bias region as well.
Figure 6.1. shows combined current voltage plot for sweep bias dependent multi level
resistive switching from a titanium oxide memristor device. Second combination was a GST
based memristor device. Twenty times repeatable, stable intermediate resistive state was found at
around 0.80 eV sweep bias. In this case memristor device switched to the low resistive state
(LRS) at around 1.20 volt. Figure 6.2. shows combined plot for memristor off state (HRS),
intermediate state (IRS) and on state (LRS) at room temperature.
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(a) (b)
LRS
IRS
HRS
(c)
Figure 6.1. Incremental bias dependent multilevel resistive switching from a bilayer titanium oxide based memristor
device (a)hysteresis with sweep bias V1= 5.60 V(b) hysteresis with sweep bias V2= 7.0 V (c) combined plot
demonstrating formation of intermediate resistive states due to the use of incremental sweep bias along the memristor
device
-5 -3
-2
10 10
10 10 1
-4 0.5
10
5
Current (A)
Current (A)
Current A)
-6 (b) 0 (c)
10 (a)
-8 -0.5
10
-10 -5 -1
10
-1 -0.5 0 0.5 1 -0.5 0 0.5 1 -1 -0.5 0 0.5 1
Applied Bias(V) Applied Bias (V) Applied Bias(V)
Figure 6.2. (a) Logarithmic plot for twenty repeatable current-voltage characterization (b) linear plot for
stable, repeatable, intermediate resistive state at 0.8 0 V (c) combined plot for HRS, IRS and LRS from a
20 μm2, memristor device where GST is the switching layer
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6.3.2 Repetitive Sweep Bias dependent MRS
With this experiment, multiple repetitive sweep bias both along the positive and negative
polarity was applied . First one under consideration was a Hafnium oxide based memristor device
with 25nm thickness for the switching layer. Electrical characterization shows undoped hafnium
oxide based memristor device was found to fully conduct at around 22.50 V. Device was found
to be in the off state (HRS) till 5.0-V dc bias. Application of five (5) repetitive sweep bias lower
than device set voltage was able to produce eight distinct intermediate states between normally
off and on resistive states. In this situation, increase and decrease of resistive states are considered
analogous to potentiation and depression phenomena within human brain respectively. Figure 6.3
shows sweep bias dependent analog modulation of conductivity from the hafnium oxide based
memristor device.
(a) (b)
Figure 6.3. Analog modulation of resistivity from a hafnium oxide based memristor device (a) Plot for
increase (Potentiation) (b) decrease (Depression) of resistive states due to application of repetitive bias
(reset and set respectively)
96
Next memristor combination for this characterization is a GeTe based memristor device.
Nine sequential sweep bias produces eighteen distinct intermediate resistive states in between
HRS and LRS. This has been plotted for two GeTe memristor devices having different overlap
areas as shown in figure 6.4. Variation of resistive states from two individual devices have been
plotted with that of consecutive sweep bias, mentioned in figure 6.5.
(a) (b)
Figure 6.4. Repetitive Sweep voltage dependent Multi level resistive switching from a GeTe memristor
having overlap area (a) 5 µm2 and (b) 20 µm2 respectively
(a) (b)
Figure 6.5. Illustration of memristor (GeTe) resistivity modulation with sequential sweep bias (a) result
from device (a) 5 µm2 and (b) 20 µm2 respectively
97
6.3.3 Compliance Current dependent MRS
Our next experiment was to vary the compliance current level within the experiment
while keeping the sweep bias always the same at room temperature. Both oxide and chalcogenide
based memristor device was taken into consideration. First MIM combination is a bilayer lithium
niobate based memristor device. Here the switching layer comprises of 80% oxygen deficient
layer and rest 20% is the regular LiNbO3. Room temperature electrical characterization was done
by modulating the compliance current level from 100 µA to 5 mA. Four intermediate resistive
states were obtained from this memristor device in between HRS and LRS.
Figure 6.6. Compliance Current dependent multi level resistive switching from a bilayer lithium niobate
based memristor device while keeping the sweep bias always the same.
Same experiment was done for a GeTe based memristor device. In this case, compliance
current levels were 40 µA, 400 µA and 4 mA. Figure 6.7.a shows formation of multiple resistive
states due to variation of compliance current levels. Figure 6.7.b shows impact of compliance
levels upon device off and on conditions. Another chalcogenide (GST) based memristor device
was brought under the same experiment. Device response from this experiment has been
illustrated within figure 6.8.
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(a (b)
Figure 6.7. Compliance current dependent multi level resistive switching from a GeTe based memristor
device (a) Formation of four (4) Intermediate resistive states in between memristor off and on states (b) plot
for variation of HRS and LRS with that of three different compliance current levels.
(a) (b)
Figure 6.8. Compliance current dependent multi level resistive switching from a GST based memristor
device (a) Formation of ten (10) Intermediate resistive states in between memristor off and on states (b)
plot for variation of HRS and LRS with that of six (6) different compliance current levels.
6.3.4 Set/Reset Voltage Dependent MRS
Other than applying full cycle sweep bias, this experiment was done to observe change of
device conductivity with the application of same polarity bias repeatedly [135]. In this case, both
oxides and chalcogenide based memristor devices were taken under consideration. First
experimental result was obtained from a memristor device, where GeTe was used as the
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switching layer. Plot in figure 6.9. shows six level hysteresis along the same SET voltage (0.8 e
V). In this case, ten intermediate resistive states are obtained in between memristor off and on
state. Same set voltage produces six different set current levels. Keeping the SET voltage same,
another experiment was done on the same device where application of repetitive negative bias
produces multiple hysteresis, defining distinct intermediate resistive states with two different
reset voltages. Result from this experiment using GST based memristor device has been plotted in
figure 6.10. In this case first we applied positive bias to initiate the set process. Compliance
current was set at 1 m A as the voltage was swept to 2.20 V. The resistance value of the on state
was approximately 0.375kΩ. Next negative voltage was applied to operate Reset process.
(a) (b)
Figure 6.9. Repetitive Set voltage dependent multiple resistive states from a memristor device having area 5
µm2 where GST is the switching layer (a) formation of four intermediate resistive states in between
memristor off and on states due to the repetitive set bias along positive polarity (b) Reset bias dependent
MRS from a GeTe memristor having area 20 µm2 while keeping the set bias the same
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overlapped area of 7.50 µm2.
As the voltage was swept to -1.50 V, the current abruptly decreased around -0.75 V (1st
Reset process). Subsequently we applied negative voltage again to sweep until -2.0 V and the
resistance further decreased around -1.25 V (2nd reset process). The resistance values were
approximately 0.94kΩ and after 1st Reset and approximately 1.57kΩ after 2nd Reset. Hence
two-level reset process was observed from the GST based memristor device as shown in figure
6.10. Another memristor device with GST as the switching layer was taken under the same
experiment demonstrating reset voltage dependent multi-level resistive switching as shown in
figure 6.11.
101
(a) (b)
overlapped area of 15.0 µm2 (a) formation of stable hysteresis loops with repetitive reset bias showing
distinct resistive levels along the negative polarity (b) variation of HRS and LRS along the reset area
The experiment was then conducted for a bilayer lithium niobate memristor. Application
of repetitive negative bias produces ten hysteresis loops holding nonvolatile device property.
Among oxide based memristor devices, sequential reset bias dependent multi level resistive
switching was achieved from bilayer lithium niobate based memristor device having 10 µm2
overlap area. In this case, keeping the Set bias unchanged repetitive negative bias was applied.
This produces ten repetitive negative hysteresis with ten distinct reset voltages. In other words, in
can be said such characterization is able to produce eighteen intermediate resistive states in
between memristor off and on states. Figure 6.12.a shows experimental result for multi state
resistive switching from the oxide memristor mentioned above. Figure 6.12.b shows gradual
change of both HRS and LRS with multiple hysteresis for the reset negative polarity bias.
Modulation of conductivity for HRS region was much prominent compared to the change for
LRS region using the reset sweep dependent multi-level resistive switching scheme as presented
in figure 6.12.
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(a) (b)
Figure 6.12. Reset Transition for multi level states (b) Modulation of HRS and LRS along negative polarity
Next device for this reset bias dependent characterization was a Tantalum oxide (TaO2)
based memristor. Multiple resistive states were achieved by applying same repetitive negative
bias which produces eight distinct level hysteresis loops with the negative polarity bias as plotted
in figure 6.13. It also means, fourteen (14) intermediate resistance states can be achieved from
this TaO2 based memristor device. Here RS1 to RS8 indicates eight different resistive states from
the hysteresis loops.
(a) (b)
Figure 6.13. Characterization for Reset voltage dependent Multiple resistive states from a memristor device
with TaO2 as the switching layer (a) modulation of conductivity from fourteen intermediate states
demonstrating repetitive reset bias dependent MLS (b) change of HRS and LRS with repetitive reset bias
along the negative polarity
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6.3.5 Temperature dependent MRS
Thermal dependence of multi-level resistive states from GST memristor was characterized
[135]. Applying the same sweep voltage (0.80 V positive and 0.60 V negative) and keeping
compliance current (3 mA) the same, current voltage characterization was done with three
different temperatures (room temperature: 25oC, 55oC and 85oC ) . Fig.6.14. shows logarithmic
plot for multiple resistive switching states within a GST based memristor device which varies with
the temperature. Elevated temperature characterization shows, increase of temperature increases
magnitude of resistive level. Four intermediate resistive states in between HRS and LRS can be
retrieved by modulating the temperature. Bipolar resistivity within such GST memristor device is
assumed to be due to the formation of conduction filament. As the resistance of LRS increases
with the increase of temperature it can be inferred that conduction filament consists of metal
precipitates or CF is mainly metallic. Figure 6.14.b shows modulation of both LRS and HRS
from device characterization with that of three different temperatures. Change of resistivity for
the same experimental condition ensures multiple resistive state from the same memristor device.
(a) (b)
Figure 6.14. Logarithmic plot for modulation of memristor’s current voltage characterization with variation
of temperature (b) Modulation of resistance levels (both HRS and LRS) with varying temperature
104
6.3.6 Pulse Measurement for MRS
Besides sweep bias, device conductance can gradually be modulated using pulses.
Response from pulse stimulation can emulate long term potentiation (LTP) and long-term
depression (LTD) functions of bio-synapse [136]. Synaptic plasticity [137] can be modulated
from short term to long term with the use of identical repeated pulse stimuli. These functions
were implemented by applying a series of negative voltage pulses (-1.20 V, 17 ms) and a series of
positive voltage pulses (1.20 V, 17 ms) respectively. Device conductance was measured by
reading a voltage pulse (0.20 V) immediately after each programming pulse. It was clearly
observed that device conductance increased or decreased gradually by increasing negative or
positive pulse number respectively. It is notable that, device potentiation is observed after around
fifty (50) consecutive pulses. Consecutive application of pulse stimuli would enhance the
excitability of post neurons. In this case, potentiation of synaptic weight should have a saturated
value to avoid excessive excitability of neurons. Here we investigate multi level capability of
memristor device using pulse programing/measurement. In this case, same pulse duration was
maintained both for read and programming voltage measurements. Figure 6.16. and 6.17. show
conductance saturation characteristics after first fifty pulses applied along the device. First
experiment was done on a bilayer lithium niobate based memristor where the thickness of the
oxide layer was 42nm. The same experiment was done on same MIM structure but with a thinner
oxide dimension (29 nm). Figure 6.16 and 6.17 show formation of multiple resistive levels during
memristor off state with the modulation of read current levels.
105
Figure 6.15. Experimental condition applied for investigating Potentiation and Depression phenomena from
a bilayer lithium niobate based memristor device using 17ms pulse as the external stimuli.
(a) (b)
current voltage characterization from a 7.50 µm2 memristor device at room temperature (b) modulation of
device conductivity for memristor off state
(a) (b)
current voltage characterization from a 2.5 µm2 memristor device at room temperature (b) modulation of
memristor off state current
106
Above results signify that our lithium niobate based memristor device can vividly
emulate potentiation and depression mechanism of bio-synapse. In other words, increase of
stimulation strengthens memory effect. Such experimental result not only enhances device
conductance but also results in prolonged retention time. Conductivity modulation was observed
with prominent appearance of multiple resistive states. It can be inferred that bilayer lithium
niobate based memristor device with reduced oxide thickness is able to exhibit bio-synaptic
attributes with less energy consumption at each intermediate state. In short, gradual resistance
modulation capability within memristor has been utilized for emulating analog synapses. Same
pulse measurements were done with the GST based memristor device where the set voltage for
the device was 1.25 V and read bias was fixed at 0.20 V. Read current was recorded in between
each consecutive write pulse applied at room temperature. Keithley 2400 SMU was utilized to
apply the 17ms pulse across the memristor device. This time, it required almost 500 pulses to
change the conductivity from the high resistive to an intermediate saturated level of conduction as
illustrated within figure 6.18. Even after 500 pulses no significant modulation presenting
depression phenomena was observed from the experimental result obtained using GST memristor
as shown in the figure 6.18.
-4
10
6.2
5.8
Read Current (A)
5.6
5.4
5.2
0 100 200 300 400 500
No. of Pulses #
Figure 6.18. Gradual conductivity modulation from a GST based memristor device using 17ms pulse
measurement
107
6.3.7 Alternate Representation of Multiple Resistive States
Another step wise conductivity change demonstrating multi level resistivity has been
observed from a GST based memristor device. Logarithmic plot for memristor current voltage
characterization has been projected here. Figure 6.19.a. shows till low bias (0.15 V) at the
positive direction device stays in the high resistive state. After 0.20 V, there is incremental
change of conductivity. At 0.60 to 0.85V memristor output current stays almost at 0.2 mA scale.
Immediately after 0.85 V there is an abrupt increase of memristor current. Device sustains this
conductive state till 1.0 V applied bias. The third conductivity level sustains till 1.20V bias. At
around 1.20V memristor device is set and reaches the low resistive state. Hence in between HRS
and LRS, three distinct intermediate resistive states were obtained at the positive polarity bias.
Now to turn the device Off, an opposite polarity external bias was provided. This showed gradual
change of resistance during the Reset phase. In this case, GST based memristor device shows step
wise delayed resistive change for positive polarity and gradual decrease of conductivity for Reset
mode of operation. Such phenomena were observed from GST based memristor devices having
different overlap areas. Such is the demonstration of an alternative resistive switching experiment
other than the usual pulse and sweep bias dependent resistive change as plotted in figure 6.19.
Figure 6.19. Formation of three Intermediate resistive states in between memristor off and on states where
GST is the switching layer (a) from device with overlapped area 5 µm2 (b) 15 µm2
108
Due to having multi-level capability and low power/energy consumption, memristor can
behave like an analog memory emulating the function of synthetic synapse in a neural network
[142]. Therefore, there is enormous opportunity to completely rethink the design of embedded
system within non-volatile memory.
6.4 Summary of Memristor as Synthetic Synapse
Different memristor structures have been explored for the potential use of neuromorphic
architecture. First, different attributes required for a neuromorphic device has been studied.
Objective is to develop a synthetic synapse using resistive random-access memory, here a
‘Memristor’. Among various requirements, existence of multiple resistive states in other words
intermediate resistive states in between normally off and on states is desired for ensuring low
power consumption for neuromorphic computation. Chapter six focuses upon different techniques
for determining such intermediate resistive states from various memristor combinations and
vividly explains relevant experimental results.
109
CHAPTER 7
CONCLUSION AND OUTLOOK
7.1 Summary of Research Contribution
This thesis presents a systematic study of the dominant charge transport mechanism from
an oxide memristor devices using a simple steady state approach. Additionally, it also explores
the potential for using memristor device as the fundamental element for neuromorphic
architecture. Main contribution of this Ph.D. dissertation includes:
1. Study of electrical characterization for multiple combinations of memristor device using
oxide and chalcogenide as switching layer.
2. Development of an analytical model comprehending conductivity mechanism through a
bilayer lithium niobate based memristor device. Elastic trap assisted tunneling
mechanism was found suitable for memristor high resistive state (HRS) and the low
resistive state (LRS) abides by the signature characterizations of ohmic conductivity for
room temperature measurements. HRS current was found uninterrupted with thermal
variation. Whereas, conductivity at low resistive state was found consistent with ohmic
process using high temperature measurements. Strong exponential change in LRS
conductivity for high temperature, high bias region has been explained due to the space
charge limited current conduction mechanism.
3. Simulation results for memristor charge transport mechanism both for high and low
resistive states have been populated investigating experimental results from multiple
memristor devices of the same combinations maintaining similar experimental
conditions.
4. One of the important attributes for device with the capability of on-chip memory is the
existence of stable intermediate resistive states in between regular off and on states which
110
would be able to replace current flash memory with the design of non-von Neumann
architecture in other words a neuromorphic computing platform . This thesis explores
different techniques for characterizing multiple resistive states from single memristor
device using standard programming schemes presented in previous research works on
resistive random-access non-volatile memory .
7.2 Future Work
This thesis provides a comprehensive study of the emerging electronic device ‘memristor’
using dc analysis. This provides a solid foundation for more exciting future work connecting
various directions.
Different memristor combination has been characterized in this report , where minimum
device area was 2.50 µm2 . To utilize this emerging device as a synthetic synapse and integrate
large data density, memristor overlap area needs to be reduced in the 10nmx10nm scale. Even
though this report presents no dependence of resistive parameters with that of device area ,
extensive studies could be made in this aspect designing much smaller devices.
Primary target of memristor research is to replace existing flash memory as it is facing the
challenges to keep Moore’s law alive. So far, no memristor device reported in previous literature,
is completely able to act as synthetic synapse having all the attributes of neuromorphic device.
Hence in future it requires extensive studies of materials, used as thin film layers of a two
terminal memristor device projected for neuromorphic application. This thesis presents
characterization results from different memristor combinations. Few MIM structures showed very
high resistance ratio which was evaluated in the low bias region. But no significant existence of
intermediate state or multiple resistive states were achieved using 17ms input pulse. Again,
111
lithium niobate based memristor having low resistance ratio showed multiple resistive capability
using both variable compliance current level and pulse input bias.
This dissertation shows experimental verification of filamentary conduction through lithium
niobate based memristor device and justifies with simulation accordingly. We have measured
single memristor device for approximating conductivity mechanism. A simple steady state
approach is probably not enough to provide extended statistics on the filament profile (filament
shape, area). A time dependent 3D dynamic model would act as a compact one. Apart from
analyzing conductivity mechanism in dynamic scale our next step would be to validate different
learning algorithms like Hebbian learning rule using spike timing dependent plasticity approach
on a larger scale crossbar memristor structure.
112
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MODELING AND EXPERIMENTAL CHARACTERIZATION OF MEMRISTOR

DEVICES FOR NEUROMORPHIC COMPUTING

The School of Engineering of the

In Partial Fulfillment of the Requirements for

Doctor of Philosophy in Engineering

Ayesha Zaman, M.S.

DEVICES FOR NEUROMORPHIC COMPUTING

Name: Zaman, Ayesha

Guru Subramanyam, Ph.D. Tarek M. Taha, Ph.D.

Andrew Sarangan, Ph.D. Ahmed Ehteshamul Islam, Ph.D.

Sabyasachi Ganguli, Ph.D.

Robert J. Wilkens, Ph.D., P. E. Eddy M. Rojas, Ph.D., M.A., P.E.

All rights reserved

MODELING AND EXPERIMENTAL CHARACTERIZATION OF MEMRISTOR

DEVICES FOR NEUROMORPHIC COMPUTING

Name: Zaman, Ayesha

Advisor: Dr. Guru Subramanyam

This thesis presents systematic study on the fundamental understanding of an emerging

electronic device; memristor. First, different metal-switching layer-metal combinations were

combinations for neuromorphic computing applications.

appreciate the degrees of freedom he offered on conducting my research. I would like to

Malia Harvey, Jinchenn Zhao and Jinjing Li.

CHAPTER 5 VERIFICATION OF PROPOSED CONDUCTION MECHANISMS ........................ 70

causes the loop area to shrink. ........................................................................................................3

computing by Shimeng Yu, July, 2013 retrieved from http://purl.stanford.edu/xh257vm1382

Copy right (2013) Stanford University. .........................................................................................5

cleaning 2. Dehydration bake 3. Photoresist coating 4. Pre-exposure bake 5. UV exposure 6.

Photoresist developing 7. O2 asher treatment 8. Metallization 9. Lift-off & cleaning 10. O2

Metallization 26. Lift off and cleaning ......................................................................................... 14

micro positioner and LMS-91A thermal module system ............................................................. 17

density with electric field ............................................................................................................. 20

electrode(a) cross sectional view, electrical characterization demonstrating variation of

density with electric field ............................................................................................................. 29

density with electric field. ............................................................................................................ 30

investigate best possible MIM combination for stable hysteresis ................................................ 36

varying overlap area size (a) to (d)............................................................................................... 37

85oC (h) 95oC ............................................................................................................................... 38

Schottky Emission ........................................................................................................................ 43

Mechanism for resistivity change................................................................................................. 47

sandwiched structure for the RRAM ............................................................................................ 49

Hafnium oxide-based RRAM device ........................................................................................... 49

Ionic Transport Mechanism for Memristor conductivity change ................................................. 50

different overlap areas .................................................................................................................. 56

programming voltage upon switching layer thickness ................................................................. 57

assumed to be responsible for P-F emission during HRS ............................................................ 63

definition mentioned in eqn. 3...................................................................................................... 64

two step ETAT mechanism. ......................................................................................................... 66

mentioned with line within the plot.............................................................................................. 71

values within the plot) .................................................................................................................. 72

Positive (b) Negative polarity bias ............................................................................................... 74

(decrease of resistance states) phenomena within human brain. .................................................. 80

level resistive switching from memristor device at room temperature......................................... 81

(c) simulation for Ohmic conduction along LRS ......................................................................... 82

(c) simulation for Ohmic conduction along LRS ......................................................................... 82

room temperature and similar experimental condition ................................................................. 83

condition has been maintained ..................................................................................................... 84