S-87.

3182 Digital Microelectronic Design

Cadence Tutorial 1
Schematic Entry and Simulation
v 1_0

Electronic Circuit Design Laboratory

Helsinki University of Technology
Developed by: Matthew Turnquist

This tutorial will provide step-by-step instruction (section A-D) to create and simulate a push-pull
inverter in CMOS 65nm. Section E will provide guidance on how to simulate with design kit
preconstructed components.

Contents:
A Getting Started
B Schematic Capture
C Symbol Cellview
D Simulation
E Simulation with Preconstructed Components

Important notes:
● Commands to put in UNIX are in italics
● All software instructions are in “brackets”
● A review of basic UNIX commands will help
● Window names will be in blue bold
● Important topics in red

Useful commands:
● When moving a component, type F3 to rotate or flip
● Change the amount of allowed UNDO steps by first clicking “Options” menu from the CIW
window. Then select “User Preferences ...”. Finally change the Undo Limit to the desired value
(i.e. 10).

More help:
● For additional help on using pre-constructed components type unidoc
A Getting Started
Log in to unix account. Open an xterm or terminal and create a new directory to run Cadence in.
Never run Cadence from the root directory since it creates many extra files that clutter the directory.

Start Cadence by typing

use cmos065_421
Type
icfb

The main Cadence window (Command Interpreter Window or CIW) should appear as shown in Fig.
1 after some delay. The “What's New in ...” window that appears can be closed. It is important that all
Cadence files only be moved with CIW. All Cadence files, applications, and libraries are managed
through the CIW window.

Fig. 1: CIW

Create a new library by selecting in the CIW window “File>New>Library ...”. As shown in Fig. 2,
Type “first” for the name and select “Attach to an existing techfile”. Select OK.

Fig. 2:
The window should appear as in Fig. 3. Select from Technology Library “cmos065” and click OK.

Fig. 3:

B Schematic Capture
B.1 Initial Setup
First, open the Library Manager from the CIW window using “Tools>Library Manager” (see Fig. 4).

Verify that the new “first” library just created is listed here in Fig. 4.

It is VERY IMPORTANT to check that the CORE65LPHVT library is listed here also. This is the
library from which standard circuits (i.e. latches, inverters, flip-flops, etc) can be chosen for the project.

Fig. 4: Library Manager

In the Library Manger window, first select your new library called “first”. Then create a new Cell by
“File>New>Cellview”. Make sure the options are the same as in Fig. 5.

Fig. 5: New File

There will be a delay before the Virtuoso Schematic Editing window appears as in Fig. 6. On the left
are helpful shortcut buttons. The tools can be accessed from the menu and through shortcut keys.
Notice that on the top bar of the window appears the library name (first), cellview (inverter), and
schematic at the end.

Fig. 6: Virtuoso Schematic Editing Window

B.2 Creating the First Schematic
Select “Add>Instance...” and the window in Fig. 7 should appear. Select “Browse”.

Fig. 7:

After selecting “Browse” the Library Browser window in Fig. 8 will result. Make sure “Show
Catagories” is checked at the top. As shown in Fig. 8, select:
cmos065 (library column)
cmos (category column)
phvtlp (cell column)
symbol (view column)

After selecting the correct values in each column, select “Close”. Place the mouse over the Virtuoso
Schematic Editing window and the new part is ready to place. Left click to place the part. Hit escape
so that more parts are not placed.

Note: The Cell column has many different types of NMOS and PMOS. For this tutorial (and project)
use the only the following:
PMOS (phvtlp)
NMOS (nhvtlp)
Fig. 8: Library Browser
Repeat the previous procedure to add a nhvtlp transistor and the schematic should look similar to Fig.
9.

Fig. 9:
Now that the PMOS and NMOS transistors have been placed, the properties need to be changed.
Select the PMOS transistor and middle-click with mouse or type “q”. The Edit Object Properties
window will appear as in Fig. 10.

Change the PMOS width from 0.120 to 0.45 as shown in Fig. 10. Select OK.

Fig. 10: Editing properties

Next, wire the components together as shown in Fig. 11. Type “w” or use the shortcut buttons (i.e.
narrow wire symbol). When you are done making a wire, use “Esc” to stop.

Fig. 11:

Adding Pins
To add input/output pins select the pin symbol from the shortcut menu. Type “in” into Pin Names and
Direction to “input” as shown in Fig. 12. Use your mouse to place “in” pin to left side of the
transistors. Repeat this procedure and place and “out” pin (with directino “out”) on the right side of the
transistors as shown in Fig. 13. Finally close the Add Pin window.

Fig. 12:
 Fig. 13:

Adding Vdd, Vss

First a new instance should be added as earlier explained (i.e. “Add>Instance ...”). Select the following
in the Library Browser window to add Vdd:
analogLib (Library column)
Sources>Global (Category column)
vdd (Cell column)

Place Vdd at the top of the PMOS. Go back to the Library Browser and select “vss” in the Cell column
and place at the bottom of the NMOS. The circuit should look the same as in Fig. 14.

Make sure the bulk for the PMOS and NMOS is connected to the vdd and vss, respectively.
 Fig. 14:

Check and Save

Select the “Check and Save” button from the top of the shortcut button menu. If there are no errors or
warnings then everything works great!

Check the CIW window for details about any errors or warnings.

C Symbol Cellview
To create a useful symbol, the schematic needs to be edited first. Remove Vdd and Vss and replace
with two input pins: Vdd and Vss. See Fig. 15.
 Fig. 15:

After the check/save works correctly, a symbol of the push-pull inverter needs to be created. This will
be of use for simulation.

Select “Design>Create Cellview>From Cellview ...”. Make sure the correct options are selected as
shown in Fig. 16 and click OK. A Symbol Generation Options window will appear. Click OK.

Fig. 16:
A symbol view will appear as shown in Fig. 17. Change the labels to those shown in Fig. 17 by
selecting the text to be changed and then “Edit>Properties>Objects ...”. This can also be achieved by
selecting the text to be changed and clicking the middle mouse button and choosing “Properties”.

Check/save and then close this window.

Fig. 17:

Create a new schematic called “testbench”. Add the inverter symbol created in the last exercise (i.e.
use “Add Instance”) into the new schematic.

First add a voltage pulse (as before add instance and in Library Manager window choose
“analogLib>Sources>Independent>vpulse). Select the voltage pulse and type “q” to view its
properties. The voltage pulse should have the same values as in Fig. 18.
 Fig. 18:

Next add components to match Fig. 19. Note that the capacitor at the output is 1fF. Don't forget to
check/save.
Fig. 19:
D Simulation
From the Virtuoso Schematic Editing window select “Tools>Analog Environment” and the Viruoso
Analog Design Environment window appears as in Fig. 20.

Fig. 20:

From the Viruoso Analog Design Environment window select “Setup>Simulator/Directory/Host ...”
and Fig. 21 should appear. Chose “spectre” as the simulator and click OK.

Fig. 21:

The proper model library now needs to be added. From the Viruoso Analog Design Environment
window select “Tools>Setup Corners ...” and Fig. 22 should result. Select “typ” under the CORNERS
column. Then select “Save Model File” at the top. Close this window.
 Fig. 22:

Next the type of simulation needs to be setup. From the Viruoso Analog Design Environment
window choose “Analyses>Choose ...” and Fig. 23 will appear. Choose “trans” for Analysis type and
add “60n” to the Stop Time. Click OK.

Fig. 23:
Now the outputs to be saved and displayed during the simulation should be chosen. From the Viruoso
Analog Design Environment window select “Outputs>To be plotted>Select on Schematic”. Move the
mouse to the Virtuoso Schematic Editing window and choose to measure the voltage at the output
node by selecting only on the blue wire at the output as shown in Fig 24. The node that is selected to
measure the voltage on should change color. Repeat this step for the input node. Note: to measure
currents select the red dot.

Fig. 24:

Finally, select from the Viruoso Analog Design Environment window choose “Simulation>Netlist
and Run”. This will take some time so be patient. Fig. 25 should appear. Congratulations if your
output looks the same as Fig. 25!
Fig. 25:
E Simulation with Preconstructed Components
First, add a preconstructed XOR component into a new schematic by using “Add Instance” and find
HS65_LH_XOR2x18 within the CORE65LPHVT library.

Next, add two input ports A and B, two input ports gnd and vdd, and an output port Z as in Fig. 26.

Fig. 26:

Now the supplies need to be taken care of. After selecting the XOR component, choose from the
Virtuoso Schematic Editing window “*Tempo Environment>Digital Multiple Supply>Add Supply to
Instance (s)” and Fig. 27 should appear. Change the gnd, gnds, vdd, and vdds as shown in Fig. 27. Do
not modify the SupplyName.

Select OK and see that gnd, gnd, vdd, vdd now appear in your schematic as in Fig. 26. If so,
check/save.
 Fig. 27:

Make a symbol of the XOR as in Fig. 28. Check/save and close. The symbol in Fig. 28 can now be
used in any standard schematic.

Fig. 28:
References
[1] Cadence Tutorial 2 http://ece.uwaterloo.ca/~ece438/projects/CadenceTut.pdf