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Silicon Photonics Platform For 50G
Silicon Photonics Platform For 50G
OPTICAL INTERCONNECTS
MICHAL RAKOWSKI
IMEC, LEUVEN, BELGIUM
Package [1cm-10cm]
Source: Intel
1Tbps+/mm
Board
1 Mbps Logic Package-to-Package
Interposer/Chip [1mm-2cm]
Copper Logic-DRAM array
[5cm-0.5m] 10Tbps+/mm
Source: LightCounting
Link distance
M. Rakowski Photonics Summit and Workshop 2017 3
OPTICAL I/O MODULE ROADMAP
NEED FOR WAVELENGTH DIVISION MULTIPLEXING
Host IC CMOS node 28-20nm 16/14nm iN10 iN7 iN5
Switch I/O Bandwidth 3.2Tb/s 6.4Tb/s 12.8Tb/s 25.6Tb/s 51.2Tb/s
Year of Introduction 2016 2018 2020 2022 2024
Optical I/O
100-200Gb/s 400Gb/s 800Gb/s 1.6Tb/s 3.2Tb/s
Module Bandwidth
Channel Data Rate 25Gb/s NRZ 50Gb/s NRZ 50Gb/s NRZ 50Gb/s NRZ 50Gb/s NRZ
50Gb/s PAM-4 100Gb/s PAM-4 100Gb/s PAM-4 100Gb/s PAM-4 100Gb/s PAM-4
Optical I/O Energy 10pJ/bit <5pJ/bit <2pJ/bit <1pJ/bit <500fJ/bit
WDM Channels
Duplex fiber, PAM-4 4 4 8 16 32
8x fiber (PSM-4), NRZ 1 2 4 8 16
16x fiber (PSM-8), NRZ 1 2 4 8
1. Unclear if future CMOS nodes will support baud rates beyond 50Gbd
2. PAM-4 acceptable for long links, but NRZ modulation preferred for short, latency sensitive links
At 50Gb/s channel speed, Wavelength Division Multiplexing is essential for module scaling
• 8+ WDM-channels likely required, even if 2x 8-parallel fibers are used per module DWDM
Silicon PICs
Fabrication in CMOS fabs [200mm/300mm]
Large Si/SiO2 refractive index contrast of ~2 [scalable PIC density]
Advanced Si patterning capability [193(i), nanometer scale accuracy]
(Si)Ge epitaxy [photodetectors/modulators]
Low resistance contacts to Si [high-speed optical devices]
Volume scalability [>1M units/year] & Efficiencies of scale [cost]
Wafer-scale 3-D packaging and assembly [TSVs, micro-bumps, ...]
No monolithic integrated optical gain/lasing [need for hybrid solution]
Co-integration of high performance 50G active and passive blocks in a single platform
Implemented in 200mm SOI (90/130nm) and 300mm (<28nm)
220nm
Si
SiO2
nSi~3.45
nSiO2~1.45
Fiber Grating Couplers: <3dB insertion loss over 30nm optical bandwidth to
Standard Single Mode Fiber
M. Rakowski Photonics Summit and Workshop 2017 9
FIBER COUPLING INTERFACES
EDGE COUPLERS
Broadband
Relatively insensitive for polarization
Smaller spot size complicate packaging
Additional process steps and stack layers Si Oxy-Nitride Edge Couplers: <2dB insertion loss
over 100nm
Wafer-scale testing not straightforward
to Specialty Fiber (3um Mode Field Diameter)
M. Rakowski Photonics Summit and Workshop 2017 10
SILICON WAVELENGTH MULTIPLEXING DEVICES
RING-BASED DWDM FILTERS
Input Waveguide 8x Cascaded Ring Filters
8x Drop Waveguides
lres Ring
Waveguide
Drop Waveguide
IL
PIN P1
IL ER
P0
P1
ER Modulation ~ER
efficiency (pm/V)
P0 ~IL
Vpp Applied Voltage λr
g w g 0
Trench
Normalized S21[dB]
width -5
Ground Signal Ground
Waveguide
Body width
width -10
P+ PBODY P N NBODY N+
BOX
-15
Substrate
Phase
-20
shifter 0 10 20 30 40 50
Parameter Typ. Value Frequency [GHz]
Input
Output Operation Wavelength 1550nm
EO Bandwidth (S21) f3dB 27GHz (at -1V)
Optical Loss 8.2 dB/cm (at 0V)
Modulation efficiency V𝜋 11 V
PGSGSGP
Optical Insertion Loss IL -2dB (excludes bias-included loss)
Dynamic Extinction Ratio ER ~2.2dB (for 2.5Vpp single-ended drive) 50Gb/s Eye diagram with
50Gb/s Eye diagram with
2.5Vpp
Phase-Shifter Length L 1.5mm 2.5Vpp
Heaters
DESIGN SPECIFICATIONS
Transmission spectra
Tungsten Heater
IL (dB)
Pout (dBm)
Modulation efficiency
(pm/V)
Transmission [dBm]
20
-3 -5
-35
ER/IL/TP [dB]
-40 15 -6 -10
-45 -15
-2.0V -9 S11-measurement 0V
10 0.25 V
-50 -1.5V -20 0.5 V
Extinction ratio
-1.0V -12 1552.85 nm 0.75 V
Insertion loss
-55 -0.5V 1552.95 nm -25 1V
5 Tx penalty 1.25 V
0.0V -15 1553.05 nm
-60 1.5 V
1553.15 nm -30
0.5V 1.75 V
-65 0 -18 -35
1552.8 1553.0 1553.2 1553.4 1553.6 1553.8 1552.8 1553.0 1553.2 1553.4 1553.6 0 10 20 30 40 50 1550 1555 1560 1565
Wavelength [nm] Wavelength [nm] Frequency [GHz] Wavelength [nm]
Voltage
Heating
swing Modulation ER at min TP IL at min TP Min Transmitter *3dB BW
Q-factor efficiency
(-1V to efficiency (pm/V) (dB) (dB) Penalty (dB) (GHz)
(nm/mW)
0.5V)
3200 1.5 45 2.6 6.0 11 47 0.284
*Modulation bandwidth reported at wavelength with maximum S21 magnitude
Electrical S11
RSi RS S11-measurement
Cm Cj S11-measurement S11-fitting
COX S11-fitting
Fitted parameters
Bias Cj (fF) RS (Ohm) Cox (fF) RSi (Ohm) Cm (fF)
f 3dB _ RC 1 / 2pRC
56Gb/s, 1Vpp
Vbias= 0V, ER=4.5dB, SNR=4.7, 1544.67
Absorption coefficient increases with applied field ER = 5.3dB and IL =5.2dB 𝑷𝑶𝒖𝒕 𝟏 −𝑷𝑶𝒖𝒕 (𝟎)
Sub-picosecond effect (2Vpp swing at 1555nm) LPP = 𝟐 𝑷𝒊𝒏
Optimum operation point close to 1550nm for GeSi EAM (where ER=4.6dB, IL=4.2dB for 2Vpp)
DFB LD Array
DRV TIA CTRL
LC MOD PD (de)MUX FC
TSV
Si Photonics Interposer
16core
Channel Modulation
100GbE 4x25Gb/s NRZ
200GbE 4x50Gb/s PAM-4
Channel Modulation
8x50Gb/s NRZ or PAM-4
400GbE
4x100Gb/s PAM-4
16x50Gb/s NRZ
800GbE
8x100Gb/s PAM-4
M. Rakowski Photonics Summit and Workshop 2017 33
TSV INTEGRATION WITH
SILICON PHOTONICS
TSV INTEGRATION CMOS
WITH SILICON PHOTONICS DRV TIA CTRL Fiber Array Coupler
Si Photonics Interposer
LC MOD PD (de)MUX FC
100µm
10x100 TSV integration TSV
Pitch 20-60µm
10µm BSRDL
BSRDL and passivation
TSV 100µm
Si Photonics interposer on
carrier wafer
100µm
L
Small Signal (measured) Large Signal (simulated)
L=100µm
Insertion loss (dB)
L=300µm
L=300µm
L=1000µm
Very low RF losses for TSV at 50GHz High-signal integrity at 50Gb/s NRZ
M. Rakowski Photonics Summit and Workshop 2017 36
SIPH TRANSCEIVER DEMONSTRATORS
ULTRA-COMPACT 16X 56GB/S GESI EAM-PD ARRAY
1x16 MMI splitter tree 100𝜇m pitch
0.7mm
16x 56Gb/s
GeSi EAM
array
1 input,
16 TX output
16 RX input
16x 56Gb/s
GeSi PD array
3mm
0.7mm
3.0mm
PROFA and Packaging by Chiral Photonics
M. Rakowski Photonics Summit and Workshop 2017 39
GESI EAM TO GESI PD LOOPBACK TRANSMISSION TEST
16 CHANNEL LINK UNIFORMITY ANALYSIS AT 56GB/S NRZ
GeSi EAM array Dynamic extinction ratio (ER) in the range of 2.7-3.3dB
GeSi EAM to GeSi PD array SNR in the range of 3.05-3.92
GeSi EAM optical transmission GeSi EAM to GeSi PD Loopback
100Gb/s Eye Diagrams BER below threshold for FEC Collaboration with
(III-V discrete PD)
M. Rakowski Photonics Summit and Workshop 2017 41
RING MODULATOR DRIVER IN 28NM CMOS
CIRCUIT CONCEPT AND WIRE-BONDED PROTOTYPE
Invertor-based Differential Driver Concept Wire-bonded CMOS-SiPh Prototype
Anode Stage VDD SiPh die with ring modulator array
MP1
MP3
MP5 MP4 MN2 Fiber in
AE MP2 Fiber out
Bond Pad
Wirebond Wirebond
drv2 MN3 Polarization
Anode EDFA (6dB)
drv1 controller
MN1
En Cpad =60fF
VSS
Tunable Optical Filter
data Bond Pad Laser
(12dBm)
Cathode Ring
Cathode Stage Modulator
Sampling
Cpad =60fF Oscilloscope
PPG + MUX 40GHz BW
Anode Stage 56 Gb/s
En data -
Cathode Stage
67GHz - 50Ω GSG probe
65µm
50Gb/s NRZ, PRBS07
V
Driver supply:
Target load per stage: C=150fF Differential voltage
VDD swing VDD=1.1V
Target data rate = 50Gb/s (1.1V)
Voltage swing (~1.7 VDD)
Ebit = 610 fJ/bit
Single driver supply
t
50Gb/s NRZ
-VDD
Interconnect requirements for high bandwidth density, low-power and low-cost are pushing
optical interconnects to shorter distances
Supporting many modulation schemes & wavelength bands considered for future datacenters
single-mode interconnects
Silicon Photonics for short-reach optical interconnects
50G NRZ optical modulation and detection rates are readily achieved
SiPh active devices can be directly driven by advanced CMOS: low capacitance and low drive voltages
Tight integration with host CMOS ICs using 3-D assembly
Low die cost and volume scalability (Spatial and Wavelength Division Multiplexing)
Main challenges
Low-cost laser array integration on SiPh interposer
Self-aligned fiber array assembly
Thermal stability (passive and active devices) and optical insertion loss