Design of an Ultra-low power voltage

regulator for RFID applications

MP3a-06
Thesis researcher: Fung Sheung Wai Supervisor : Professor Philip K.T. Mok
 OverView
Radio Frequency Identification (RFID) is a wireless communication
system that commonly used in many areas, such as assess system or
tracking of object. RFID mainly consist of two parts, a reader and a tag.
There are two kinds of tags, which is an active one and a passive one. For
the passive tag, it does not use any battery and the power is comes form
the RF (radio frequency) energy transmitted from the reader. So the
power in passive tag is very limited. In addition, for the passive tag to
operate properly, a more regulated DC power supply is required. Thus a
Low dropout voltage regulator (LDO) is always used inside the passive
tag and it is a great interest to design a LDO for passive tag.

Low Dropout voltage regulator is popularly used in many portable

electronic, as it can provide a low noise and regulator power supply.
However, a conventional LDO is not suitable for passive tag. It is because
the specifications of an LDO for passive tag are very different from the
conventional one (shown in table below). Thus we need to design a new
LDO for passive tag.

Specifications An LDO for passive A conventional LDO

tag
Output 250 pF 5µF
capacitance
Load current 0.1 µA– 25µA 0.1mA– 100mA
range
Quiescent current < 400nA < 100µA
Memory Read: Load current Load current is 100mA
operation is 0.5µA for 2.5ms
Write: Load current
is 25µA for 6ms
PSRR @100kHz < -20dB @1kHz < -20dB
Temperature ( -20 o C – 70 o C ) ( 0 o C – 100 o C )
Coefficient < 100ppm/ o C < 50ppm/ o C
Unregulated 1.3 to 1.8 V 3 to 3.3V
supply voltage
Regulated output 1V ( lower than 2.7V
voltage band gap voltage )
Design & Implementation
The schematic of an LDO
for a passive tag is shown on
the figure on the left which is
a three stage amplifier. A
NMOS input differential-pair
amplifier is the first stage, a
NMOS buffer is the second
stage and the power PMOS is
the third stage. As a buffer is
used in the second stage, the
buffer will separate the large
capacitor Cgp from the low
resistive node Ro1 of the
diff-pair amplifier, resulting
in a more stable system.

As a typical band gap voltage

reference cannot de designed to have a
reference voltage lower than 1.205V.
However the voltage reference used for
the LDO in passive tag needed a
reference voltage is equal to 1V. In
addition, because of the chip area of a
passive tag is limited and the layout of
BJT is quite large, so using BJT to
generate a PTAT current is not good in
this case. Thus, we used MOSFETs on
sub threshold region rather than BJTs to
generate a PTAT current and a new
design of voltage reference is introduced
as shown on the figure on the left and
⎡ ⎛ (W / L )6 ⎞ R2 ⎤ R3
Vref = ⎢Vgs 6 + nVT ln⎜⎜ ⎟⎟ ⋅ ⎥ ⋅
⎣ ⎝ (W / L )7 ⎠ R1 ⎦ R2
 Simulation Results
The performance of the LDO for passive tag during
operation (class 0)

The performance of the LDO for passive tag during

operation (class 1 or 2)

During the operation of the passive tag, the

supply voltage Vin will drop from 1.8V, as the
input capacitor is discharging. Also, we can see
the output voltage is regulated around our
desired value = 1V.