LTC1742

14-Bit, 65Msps Low Noise ADC

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FEATURES DESCRIPTIO
■ Sample Rate: 65Msps The LTC ®1742 is an 65Msps, sampling 14-bit A/D con-
■ 76.5dB SNR and 90dB SFDR (3.2V Range) verter designed for digitizing high frequency, wide dy-
■ 72.8dB SNR and 90dB SFDR (2V Range) namic range signals. Pin selectable input ranges of ±1V
■ No Missing Codes and ±1.6V along with a resistor programmable mode
■ Single 5V Supply allow the LTC1742’s input range to be optimized for a wide
■ Power Dissipation: 1.275W variety of applications.
■ Selectable Input Ranges: ±1V or ±1.6V
The LTC1742 is perfect for demanding communications
■ 240MHz Full Power Bandwidth S/H
applications with AC performance that includes 76.5dB
■ Pin Compatible Family
SNR and 90dB spurious free dynamic range. Ultralow jitter
25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit)
of 0.15psRMS allows undersampling of IF frequencies with
50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit)
excellent noise performance. DC specs include ±3LSB INL
65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit)
and ±1LSB DNL.
80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit)
■ 48-Pin TSSOP Package The digital interface is compatible with 5V, 3V, 2V and
U LVDS logic levels. The ENC and ENC inputs may be driven
APPLICATIO S differentially from PECL, GTL and other low swing logic
families or from single-ended TTL or CMOS. The low
■ Telecommunications noise, high gain ENC and ENC inputs may also be driven
■ Receivers by a sinusoidal signal without degrading performance. A
■ Cellular Base Stations separate output power supply can be operated from 0.5V
■ Spectrum Analysis to 5V, making it easy to connect directly to low voltage
■ Imaging Systems DSPs or FIFOs.
, LTC and LT are registered trademarks of Linear Technology Corporation.
The TSSOP package with a flow-through pinout simplifies
the board layout.

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BLOCK DIAGRA
65Msps, 14-Bit ADC with a 2V Differential Input Range
OVDD
0.5V
TO 5V
0.1µF
0.1µF
AIN+
OF
±1V CORRECTION 14 D13
DIFFERENTIAL S/H 14-BIT LOGIC AND OUTPUT •
•
ANALOG INPUT AMP PIPELINED ADC SHIFT LATCHES •
AIN– D0
REGISTER
CLKOUT
OGND
SENSE

BUFFER
VDD
5V
RANGE 1µF 1µF
SELECT
DIFF AMP
1µF
VCM GND
2.35VREF
CONTROL LOGIC
4.7µF
1742 BD

REFLB REFHA REFLA REFHB ENC ENC MSBINV OE

4.7µF
0.1µF 0.1µF DIFFERENTIAL
1µF 1µF ENCODE INPUT

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LTC1742
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ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ............................................. 5.5V TOP VIEW ORDER PART
Analog Input Voltage (Note 3) .... – 0.3V to (VDD + 0.3V) SENSE 1 48 OF NUMBER
VCM 2 47 OGND
Digital Input Voltage (Except OE) GND 3 46 D13 LTC1742CFW
AIN+ 4 45 D12
(Note 3) ...................................... – 0.3V to (VDD + 0.3V) AIN– 5 44 D11 LTC1742IFW
OE Input Voltage (Note 4) ........ – 0.3V to (OVDD + 0.3V) GND 6 43 OVDD
VDD 7 42 D10
Digital Output Voltage ................. – 0.3V to (VDD + 0.3V) VDD 8 41 D9
GND 9 40 D8
OGND Voltage ..............................................– 0.3V to 1V REFLB 10 39 D7
Power Dissipation ............................................ 2000mW REFHA 11 38 OGND
GND 12 37 GND
Operating Temperature Range GND 13 36 GND
LTC1742C ............................................... 0°C to 70°C REFLA
REFHB
14
15
35
34
D6
D5
LTC1742I ............................................ – 40°C to 85°C GND 16 33 D4
VDD 17 32 OVDD
Storage Temperature Range ................. – 65°C to 150°C VDD 18 31 D3
Lead Temperature (Soldering, 10 sec).................. 300°C GND
VDD
19
20
30
29
D2
D1
GND 21 28 D0
MSBINV 22 27 OGND
ENC 23 26 CLKOUT
ENC 24 25 OE
FW PACKAGE
48-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 35°C/W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

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CO VERTER CHARACTERISTICS The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) ● 14 Bits
Integral Linearity Error (Note 6) –3 ±0.75 3 LSB
Differential Linearity Error ● –1 ±0.5 1 LSB
Offset Error (Note 7) – 35 ±5 35 mV
Gain Error External Reference (SENSE = 1.6V) – 3.5 ±1 3.5 %FS
Full-Scale Drift Internal Reference ±40 ppm/°C
Full-Scale Drift External Reference (SENSE = 1.6V) ±20 ppm/°C
Offset Drift Internal Reference ±20 µV/°C
Input Referred Noise (Transition Noise) SENSE = 1.6V 0.82 LSBRMS
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A ALOG I PUT The ● indicates specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (Note 8) 4.75V ≤ VDD ≤ 5.25V ● ±1 to ±1.6 V
IIN Analog Input Leakage Current 0 < AIN+, AIN– < VDD ● –1 1 µA
CIN Analog Input Capacitance Sample Mode ENC < ENC 8 pF
Hold Mode ENC > ENC 4 pF
tACQ Sample-and-Hold Acquisition Time ● 5 7.3 ns
tAP Sample-and-Hold Acquisition Delay Time 0 ns
tJITTER Sample-and-Hold Acquisition Delay Time Jitter 0.15 psRMS
CMRR Analog Input Common Mode Rejection Ratio 1.5V < (AIN– = AIN+) < 3V 80 dB
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 LTC1742
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DY A IC ACCURACY TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 5MHz Input Signal (2V Range) 72.8 dB
5MHz Input Signal (3.2V Range) 75 76.5 dB
30MHz Input Signal (2V Range) 72.5 dB
30MHz Input Signal (3.2V Range) 74 76.5 dB
70MHz Input Signal (2V Range) 72.2 dB
70MHz Input Signal (3.2V Range) 75.8 dB
SFDR Spurious Free Dynamic Range 5MHz Input Signal (2V Range) 90 dB
5MHz Input Signal (3.2V Range) (2nd and 3rd) 90 dB
5MHz Input Signal (3.2V Range) (Other) 95 dB
30MHz Input Signal (2V Range) 90 dB
30MHz Input Signal (3.2V Range) (2nd and 3rd) 80 88 dB
30MHz Input Signal (3.2V Range) (Other) 85 95 dB
70MHz Input Signal (2V Range) 83 dB
70MHz Input Signal (3.2V Range) (2nd and 3rd) 75 dB
70MHz Input Signal (3.2V Range) (Other) 95 dB
S/(N + D) Signal-to-(Noise + Distortion) Ratio 5MHz Input Signal (2V Range) 72.6 dB
5MHz Input Signal (3.2V Range) 74.5 76.2 dB
30MHz Input Signal (2V Range) 72.3 dB
30MHz Input Signal (3.2V Range) 76.0 dB
70MHz Input Signal (2V Range) 71 dB
70MHz Input Signal (3.2V Range) 71 dB
THD Total Harmonic Distortion 5MHz Input Signal, First 5 Harmonics (2V Range) –90 dB
5MHz Input Signal, First 5 Harmonics (3.2V Range) –90 dB
30MHz Input Signal, First 5 Harmonics (2V Range) –90 dB
30MHz Input Signal, First 5 Harmonics (3.2V Range) –85 dB
70MHz Input Signal, First 5 Harmonics (2V Range) –78 dB
70MHz Input Signal, First 5 Harmonics (3.2V Range) –74 dB
IMD Intermodulation Distortion fIN1 = 2.52MHz, fIN2 = 5.2MHz (2V Range) 97 dBc
fIN1 = 2.52MHz, fIN2 = 5.2MHz (3.2V Range) 93 dBc
Sample-and-Hold Bandwidth RSOURCE = 50Ω 240 MHz

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I TER AL REFERE CE CHARACTERISTICS (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 2.30 2.35 2.40 V
VCM Output Tempco IOUT = 0 ±30 ppm/°C
VCM Line Regulation 4.75V ≤ VDD ≤ 5.25V 3 mV/V
VCM Output Resistance 1mA ≤ IOUT ≤ 1mA 4 Ω

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LTC1742
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DIGITAL I PUTS A D DIGITAL OUTPUTS The ● indicates specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VDD = 5.25V, MSBINV and OE ● 2.4 V
VIL Low Level Input Voltage VDD = 4.75V, MSBINV and OE ● 0.8 V
IIN Digital Input Current VIN = 0V to VDD ● ±10 µA
CIN Digital Input Capacitance MSBINV and OE Only 1.5 pF
VOH High Level Output Voltage OVDD = 4.75V IO = –10µA 4.74 V
IO = – 200µA ● 4 4.74 V
VOL Low Level Output Voltage OVDD = 4.75V IO = 160µA 0.05 V
IO = 1.6mA ● 0.1 0.4 V
IOZ Hi-Z Output Leakage D13 to D0 VOUT = 0V to VDD, OE = High ● ±10 µA
COZ Hi-Z Output Capacitance D13 to D0 OE = High (Note 8) ● 15 pF
ISOURCE Output Source Current VOUT = 0V – 50 mA
ISINK Output Sink Current VOUT = 5V 50 mA
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POWER REQUIRE E TS The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Positive Supply Voltage 4.75 5.25 V
IDD Positive Supply Current ● 255 275 mA
PDIS Power Dissipation ● 1.275 1.375 W
OVDD Digital Output Supply Voltage 0.5 VDD V
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TI I G CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t0 ENC Period (Note 9) ● 15.3 2000 ns
t1 ENC High (Note 8) ● 7.3 1000 ns
t2 ENC Low (Note 8) ● 7.3 1000 ns
t3 Aperture Delay (Note 8) 0 ns
t4 ENC to CLKOUT Falling CL = 10pF (Note 8) ● 1 2.4 4 ns
t5 ENC to CLKOUT Rising CL = 10pF (Note 8) t1 + t 4 ns
For 65Msps 50% Duty Cycle CL = 10pF (Note 8) ● 8.7 10.1 11.7 ns
t6 ENC to DATA Delay CL = 10pF (Note 8) ● 2 4.9 7.2 ns
t7 ENC to DATA Delay (Hold Time) (Note 8) ● 1.4 3.4 4.7 ns
t8 ENC to DATA Delay (Setup Time) CL = 10pF (Note 8) t0 – t 6 ns
For 65Msps 50% Duty Cycle CL = 10pF (Note 8) ● 8.2 10.5 13.4 ns
t9 CLKOUT to DATA Delay (Hold Time), (Note 8) ● 7 ns
65Msps 50% Duty Cycle
t10 CLKOUT to DATA Delay (Setup Time), CL = 10pF (Note 8) ● 3 ns
65Msps 50% Duty Cycle
t11 DATA Access Time After OE CL = 10pF (Note 8) 10 25 ns
t12 BUS Relinquish (Note 8) 10 25 ns
Data Latency 5 cycles
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 LTC1742
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life Note 5: VDD = 5V, fSAMPLE = 65MHz, differential ENC/ENC = 2VP-P 65MHz
of a device may be impaired. sine wave, input range = ±1.6V differential, unless otherwise specified.
Note 2: All voltage values are with respect to ground with GND Note 6: Integral nonlinearity is defined as the deviation of a code from a
(unless otherwise noted). straight line passing through the actual endpoints of the transfer curve.
Note 3: When these pin voltages are taken below GND or above VDD, they The deviation is measured from the center of the quantization band.
will be clamped by internal diodes. This product can handle input currents Note 7: Bipolar offset is the offset voltage measured from – 0.5 LSB
of greater than 100mA below GND or above VDD without latchup. when the output code flickers between 00 0000 0000 0000 and 11
Note 4: When this pin voltage is taken below GND or above OVDD, it will be 1111 1111 1111.
clamped by internal diodes. This product can handle input currents of Note 8: Guaranteed by design, not subject to test.
>100mA below GND or above OVDD without latchup. Note 9: Recommended operating conditions.

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TYPICAL PERFOR A CE CHARACTERISTICS
8192 Point FFT,
Input Frequency = 15MHz,
INL, 3.2V Range DNL, 3.2V Range –1dB, 3.2V Range
2.5 1.0 0
TA = 25°C TA = 25°C TA = 25°C
2.0 0.8 –10
–20
1.5 0.6
–30
1.0 0.4

AMPLITUDE (dBFS)
–40
ERROR (LSB)

ERROR (LSB)

0.5 0.2 –50

0 0 –60
–0.5 –0.2 –70
–80
–1.0 –0.4
–90
–1.5 –0.6
–100
–2.0 –0.8 –110
–2.5 –1.0 –120
0 4096 8192 12288 16384 0 4096 8192 12288 16384 0 5 10 15 20 25 30
OUTPUT CODE OUTPUT CODE FREQUENCY (MHz)
1742 G01 1742 G02 1742 G03

8192 Point FFT, 8192 Point FFT, 8192 Point FFT,

Input Frequency = 15MHz, Input Frequency = 15MHz, Input Frequency = 30MHz,
–10dB, 3.2V Range –20dB, 3.2V Range –1dB, 3.2V Range
0 0 0
TA = 25°C TA = 25°C TA = 25°C
–10 –10 –10
–20 –20 –20
–30 –30 –30
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

–40 –40 –40

–50 –50 –50
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
0 5 10 15 20 25 30 0 5 10 15 20 25 30 0 5 10 15 20 25 30
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
1742 G04 1742 G05 1742 G06

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 LTC1742
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TYPICAL PERFOR A CE CHARACTERISTICS
8192 Point FFT, 8192 Point FFT, 8192 Point FFT,
Input Frequency = 30MHz, Input Frequency = 30MHz, Input Frequency = 40MHz,
–10dB, 3.2V Range –20dB, 3.2V Range –1dB, 3.2V Range
0 0 0
TA = 25°C TA = 25°C TA = 25°C
–10 –10 –10
–20 –20 –20
–30 –30 –30
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–40 –40 –40
–50 –50 –50
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
0 5 10 15 20 25 30 0 5 10 15 20 25 30 0 5 10 15 20 25 30
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
1742 G07 1742 G08 1742 G09

8192 Point FFT, 8192 Point FFT, 8192 Point FFT,

Input Frequency = 40MHz, Input Frequency = 40MHz, Input Frequency = 50MHz,
–10dB, 3.2V Range –20dB, 3.2V Range –1dB, 3.2V Range
0 0 0
TA = 25°C TA = 25°C TA = 25°C
–10 –10 –10
–20 –20 –20
–30 –30 –30
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

–40 –40 –40

–50 –50 –50
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
0 5 10 15 20 25 30 0 5 10 15 20 25 30 0 5 10 15 20 25 30
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
1742 G10 1742 G11 1742 G12

8192 Point FFT, 8192 Point FFT, 8192 Point FFT,

Input Frequency = 50MHz, Input Frequency = 50MHz, Input Frequency = 70MHz,
–10dB, 3.2V Range –20dB, 3.2V Range –1dB, 3.2V Range
0 0 0
TA = 25°C TA = 25°C TA = 25°C
–10 –10 –10
–20 –20 –20
–30 –30 –30
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

–40 –40 –40

–50 –50 –50
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
0 5 10 15 20 25 30 0 5 10 15 20 25 30 0 5 10 15 20 25 30
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
1742 G13 1742 G14 1742 G15

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 LTC1742
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TYPICAL PERFOR A CE CHARACTERISTICS
8192 Point FFT, 8192 Point FFT, 8192 Point 2-Tone FFT,
Input Frequency = 70MHz, Input Frequency = 70MHz, Input Frequency = 5MHz and
–10dB, 3.2V Range –20dB, 3.2V Range 7MHz, –7dB, 3.2V Range
0 0 0
TA = 25°C TA = 25°C TA = 25°C
–10 –10 –10
–20 –20 –20
–30 –30 –30
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
–40 –40 –40
–50 –50 –50
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
0 5 10 15 20 25 30 0 5 10 15 20 25 30 0 5 10 15 20 25 30
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
1742 G16 1742 G17 1742 G18

8192 Point 2-Tone FFT, 8192 Point 2-Tone FFT,

Input Frequency = 25MHz and Input Frequency = 68MHz and
30MHz, –7dB, 3.2V Range 70MHz, –7dB, 3.2V Range SFDR vs 15MHz Input Level
0 0 120
TA = 25°C TA = 25°C TA = 25°C
–10 –10 110
–20 –20 100
dBFS
–30 –30 SFDR (dBc AND dBFS) 90
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

–40 –40 80
–50 –50 70
dBc
–60 –60 60
–70 –70 50
–80 –80 40
–90 –90 30
–100 –100 20
–110 –110 10
–120 –120 0
0 5 10 15 20 25 30 0 5 10 15 20 25 30 –80 –70 –60 –50 –40 –30 –20 –10 0
FREQUENCY (MHz) FREQUENCY (MHz) INPUT LEVEL (dBFS)
1742 G19 1742 G20 1742 G21

SFDR vs 30MHz Input Level SFDR vs 50MHz Input Level SFDR vs 70MHz Input Level
120 120 120
TA = 25°C TA = 25°C TA = 25°C
110 110 110
dBFS dBFS
100 100 100
dBFS
90 90 90
SFDR (dBc AND dBFS)

SFDR (dBc AND dBFS)

SFDR (dBc AND dBFS)

80 80 80
70 70 70
dBc
60 60 60
dBc dBc
50 50 50
40 40 40
30 30 30
20 20 20
10 10 10
0 0 0
–80 –70 –60 –50 –40 –30 –20 –10 0 –80 –70 –60 –50 –40 –30 –20 –10 0 –80 –70 –60 –50 –40 –30 –20 –10 0
INPUT LEVEL (dBFS) INPUT LEVEL (dBFS) INPUT LEVEL (dBFS)
1742 G22 1742 G23 1742 G24

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LTC1742
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TYPICAL PERFOR A CE CHARACTERISTICS
SFDR vs Input Frequency and SFDR vs Input Frequency and
Amplitude, 3.2V Range, Amplitude, 2V Range,
2nd and 3rd Harmonic 2nd and 3rd Harmonic Shorted Input Histogram
100 100 35000
TA = 25°C TA = 25°C TA = 25°C
–20dB –20dB
95 95 30000
–10dB
90 90 –10dB
–6dB –6dB 25000
85 85

SFDR (dBFS)
SFDR (dBFS)

–1dB 20000

COUNT
80 80
–1dB 15000
75 75
10000
70 70

65 65 5000

60 60 0
0 20 40
60 80 100 0 20 40 60 80 100 8140 8141 8142 8143 8144 8145 8146 8147
INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) CODE
1742 G25 1742 G26 1742 G27

SNR vs Input Frequency SNR vs Sample Rate, 5MHz Input, –

3.2V and 2V Range 1dB, 3.2V Range
77.0 78
TA = 25°C TA = 25°C
76.5
3.2V RANGE
76.0 77

75.5
76
75.0
SNR (dBFS)

SNR (dBFS)

74.5
75
74.0
73.5
74
73.0
2V RANGE
72.5 73
72.0
71.5 72
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90
INPUT FREQUENCY (MHz) SAMPLE RATE (Msps)
1742 G28 1742 G29

SFDR vs Sample Rate, 5MHz Input,

–1dB, 3.2V Range Supply Current vs Sample Rate
100 270
TA = 25°C TA = 25°C
95
260
SUPPLY CURRENT (mA)

90
250
SFDR (dBFS)

85

80 240

75
230
70
220
65

60 210
0 10 20 30 40 50 60 70 80 90 0 20 40 60 80
SAMPLE RATE (Msps) SAMPLE RATE (Msps)
1742 G30 1742 G31

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PI FU CTIO S
SENSE (Pin 1): Reference Sense Pin. Ground selects ±1V.
VDD selects ±1.6V. Greater than 1V and less than 1.6V
applied to the SENSE pin selects an input range of ±VSENSE,
±1.6V is the largest valid input range.
VCM (Pin 2): 2.35V Output and Input Common Mode Bias.
Bypass to ground with 4.7µF ceramic chip capacitor.
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC Power
Ground.
AIN+ (Pin 4): Positive Differential Analog Input.
AIN– (Pin 5): Negative Differential Analog Input.
VDD (Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to AGND
with 1µF ceramic chip capacitors at Pin 8 and Pin 18.
REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11
with 0.1µF ceramic chip capacitor. Do not connect to
Pin␣ 14.
REFHA (Pin 11): ADC High Reference. Bypass to Pin 10 with
0.1µF ceramic chip capacitor, to Pin 14 with a 4.7µF ceramic
capacitor and to ground with 1µF ceramic capacitor.
REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15 with
0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF ce-
ramic capacitor and to ground with 1µF ceramic capacitor.
REFHB (Pin 15): ADC High Reference. Bypass to Pin 14
with 0.1µF ceramic chip capacitor. Do not connect to
Pin␣ 11.
LTC1742
MSBINV (Pin 22): MSB Inversion Control. Low inverts
the MSB, 2’s complement output format. High does not
invert the MSB, offset binary output format.
ENC (Pin 23): Encode Input. The input sample starts on the
positive edge.
ENC (Pin 24): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1µF
ceramic for single-ended ENCODE signal.
OE (Pin 25): Output Enable. Low enables outputs. Logic
high makes outputs Hi-Z. OE should not exceed the
voltage on OVDD.
CLKOUT (Pin 26): Data Valid Output. Latch data on the
rising edge of CLKOUT.
OGND (Pins 27, 38, 47): Output Driver Ground.
D0-D3 (Pins 28 to 31): Digital Outputs.
OVDD (Pins 32, 43): Positive Supply for the Output Driv-
ers. Bypass to ground with 0.1µF ceramic chip capacitor.
D4-D6 (Pins 33 to 35): Digital Outputs.
D7-D10 (Pins 39 to 42): Digital Outputs.
D11-D13 (Pins 44 to 46): Digital Outputs.
OF (Pin 48): Over/Under Flow Output. High when an over
or under flow has occurred.
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LTC1742
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TI I G DIAGRA
N •
ANALOG
INPUT t3

t1 t2 t0

ENC

t7
t8
DATA (N – 5) DATA (N – 4)
DATA DATA (N – 3)
DB13 TO DB0 DB13 TO DB0
t6

CLKOUT

t4
t5 t10 t9

OE

t11 t12

DATA N
DATA
DB13 TO DB0, OF AND CLKOUT
1742 TD

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APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
V22 + V32 + V 42 + ...Vn2
THD = 20Log
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
1742f

10
 LTC1742
U U W U
APPLICATIO S I FOR ATIO
Spurious Free Dynamic Range (SFDR) when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component SNRJITTER = –20log (2π) • FIN • TJITTER
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input CONVERTER OPERATION
signal.
The LTC1742 is a CMOS pipelined multistep converter.
Input Bandwidth The converter has four pipelined ADC stages; a sampled
analog input will result in a digitized value five cycles later,
The input bandwidth is that input frequency at which the see the Timing Diagram section. The analog input is
amplitude of the reconstructed fundamental is reduced by differential for improved common mode noise immunity
3dB for a full scale input signal. and to maximize the input range. Additionally, the differen-
tial input drive will reduce even order harmonics of the
Aperture Delay Time
sample-and-hold circuit. The encode input is also
The time from when a rising ENC equals the ENC voltage differential for improved common mode noise immunity.
to the instant that the input signal is held by the sample and
The LTC1742 has two phases of operation, determined by
hold circuit.
the state of the differential ENC/ENC input pins. For brev-
Aperture Delay Jitter ity, the text will refer to ENC greater than ENC as ENC high
and ENC less than ENC as ENC low.
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.

AIN+
FIRST PIPELINED SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED
INPUT
ADC STAGE ADC STAGE ADC STAGE ADC STAGE
S/H
AIN– (5 BITS) (4 BITS) (4 BITS) (4 BITS)

VCM 2.35V
REFERENCE
4.7µF

RANGE SHIFT REGISTER

SELECT AND CORRECTION

REFL REFH INTERNAL CLOCK SIGNALS OVDD 0.5V TO

REF 5V
SENSE BUF OF
D13
DIFFERENTIAL
INPUT CONTROL LOGIC
DIFF OUTPUT
LOW JITTER AND
REF DRIVERS
CLOCK CALIBRATION LOGIC D0
AMP
DRIVER
CLKOUT

1742 F01

REFLB REFHA REFLA REFHB ENC ENC MSBINV OE OGND

4.7µF
0.1µF 0.1µF
1µF 1µF

Figure 1. Functional Block Diagram

1742f

11
LTC1742
U U W U
APPLICATIO S I FOR ATIO
In operation, the ADC quantizes the input to the stage and LTC1742
VDD
the quantized value is subtracted from the input by the CSAMPLE
4pF
DAC to produce a residue. The residue is amplified and
AIN+
output by the residue amplifier. Successive stages operate CPARASITIC
out of phase so that when the odd stages are outputting VDD 4pF
CSAMPLE
their residue, the even stages are acquiring that residue 4pF
and visa versa. AIN–
CPARASITIC
When ENC is low, the analog input is sampled differentially 4pF

directly onto the input sample-and-hold capacitors, inside 5V

the “Input S/H” shown in the block diagram. At the instant

BIAS
that ENC transitions from low to high, the sampled input 2V
is held. While ENC is high, the held input voltage is
6k
buffered by the S/H amplifier which drives the first pipelined
ENC
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low, ENC
the first stage produces its residue which is acquired by 6k

the second stage. At the same time, the input S/H goes 2V
back to acquiring the analog input. When ENC goes back 1742 F02

high, the second stage produces its residue which is
acquired by the third stage. An identical process is re-
peated for the third stage, resulting in a third stage residue
that is sent to the fourth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC1742
CMOS differential sample-and-hold. The differential ana-
log inputs are sampled directly onto sampling capacitors
(CSAMPLE) through CMOS transmission gates. This direct
capacitor sampling results in lowest possible noise for a
given sampling capacitor size. The capacitors shown
attached to each input (CPARASITIC) are the summation of
all other capacitance associated with each input.
During the sample phase when ENC/ENC is low, the
transmission gate connects the analog inputs to the sam-
pling capacitors and they charge to, and track the differen-
tial input voltage. When ENC/ENC transitions from low to
Figure 2. Equivalent Input Circuit
high the sampled input voltage is held on the sampling
capacitors. During the hold phase when ENC/ENC is high
the sampling capacitors are disconnected from the input
and the held voltage is passed to the ADC core for
processing. As ENC/ENC transitions from high to low the
inputs are reconnected to the sampling capacitors to
acquire a new sample. Since the sampling capacitors still
hold the previous sample, a charging glitch proportional to
the change in voltage between samples will be seen at this
time. If the change between the last sample and the new
sample is small the charging glitch seen at the input will be
small. If the input change is large, such as the change seen
with input frequencies near Nyquist, then a larger charging
glitch will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential drive
to achieve specified performance. Each input should swing
±0.8V for the 3.2V range or ±0.5V for the 2V range, around
a common mode voltage of 2.35V. The VCM output pin
(Pin␣ 2) may be used to provide the common mode bias level.
VCM can be tied directly to the center tap of a transformer
to set the DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 4.7µF or greater capacitor.
1742f

12

U U W U
APPLICATIO S I FOR ATIO
Input Drive Impedance
As with all high performance, high speed ADCs the dy-
namic performance of the LTC1742 can be influenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and input reactance can
influence SFDR. At the falling edge of encode the sample-
and-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when encode rises, holding the sampled input
on the sampling capacitor. Ideally the input circuitry
should be fast enough to fully charge the sampling capaci-
tor during the sampling period 1/(2FENCODE); however,
this is not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recomended to have a
source impedence of 100Ω or less for each input. The S/H
circuit is optimized for a 50Ω source impedance. If the
source impedance is less than 50Ω, a series resistor
should be added to increase this impedance to 50Ω. The
source impedence should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC1742 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
VCM
4.7µF
0.1µF 12pF
25Ω 25Ω AIN+ LTC1742
ANALOG 1:1
INPUT
100Ω 100Ω 12pF
25Ω AIN–
25Ω
12pF
LTC1742
source impedence seen by the ADC does not exceed
100Ω for each ADC input. A disadvantage of using a
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequen-
cies below 1MHz.
Figure 4 demonstrates the use of operational amplifiers to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
The 25Ω resistors and 12pF capacitors on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input. For input
frequencies higher than 100MHz, the capacitors may need
to be decreased to prevent excessive signal loss.
Reference Operation
Figure 5 shows the LTC1742 reference circuitry consisting
of a 2.35V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage refer-
ence can be configured for two pin selectable input ranges
of 2V(±1V differential) or 3.2V(±1.6V differential). Tying
the SENSE pin to ground selects the 2V range; tying the
SENSE pin to VDD selects the 3.2V range.
The 2.35V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
VCM
4.7µF
5V
SINGLE-ENDED
INPUT 12pF
2.35V ±1/2
+
25Ω 25Ω AIN+
RANGE 1/2 LT1810
– LTC1742
12pF
100Ω
+
25Ω 25Ω AIN–
1/2 LT1810
– 12pF

500Ω 500Ω
1742 F04
1742 F03

Figure 3. Single-Ended to Differential Conversion

Using a Transformer Figure 4. Differential Drive with Op Amps
1742f

13
LTC1742
U U W U
APPLICATIO S I FOR ATIO
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry.
An external bypass capacitor is required for the 2.35V
reference output, VCM. This provides a high frequency low
impedance path to ground for internal and external cir-
cuitry. This is also the compensation capacitor for the
reference. It will not be stable without this capacitor.
The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins: REFHA and REFHB
for the high reference and REFLA and REFLB for the low
reference. The doubled output pins are needed to reduce
package inductance. Bypass capacitors must be con-
nected as shown in Figure 5.
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 6a. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device since the logic threshold is close to ground and
LTC1742
VDD. The SENSE pin should be tied high or low as close to
the converter as possible. If the SENSE pin is driven
externally, it should be bypassed to ground as close to the
device as possible with a 1µF ceramic capacitor.
Input Range
The input range can be set based on the application. For
oversampled signal processing in which the input fre-
quency is low (<10MHz), the largest input range will
provide the best signal-to-noise performance while main-
taining excellent SFDR. For high input frequencies
(> 40MHz), the 2V range will have the best SFDR perfor-
mance for the 2nd and 3rd harmonics, but the SNR will
degrade by 3.5dB. See the Typical Performance Charac-
teristics section.
Driving the Encode Inputs
The noise performance of the LTC1742 can depend on the
encode signal quality as much as on the analog input. The
ENC/ENC inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a 2V
bias. The bias resistors set the DC operating point for
transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.

VCM 4Ω 2.35V BANDGAP

2.35V 2.35V VCM
REFERENCE
4.7µF
1.6V 1V 4.7µF
12.5k
LTC1742
RANGE 1.1V SENSE
DETECT
AND 11k 1µF
CONTROL
TIE TO VDD FOR 3.2V RANGE;
TIE TO GND FOR 2V RANGE; SENSE
RANGE = 2 • VSENSE FOR 1742 F06a

1V < VSENSE < 1.6V REFLB BUFFER

INTERNAL ADC
1µF 0.1µF HIGH REFERENCE
Figure 6a. 2.2V Range ADC
REFHA

VCM
2.35V
4.7µF
DIFF AMP 4.7µF

1µF LTC1742
4 6 1.25V SENSE
REFLA 5V LT1790-1.25
0.1µF 1, 2 1µF
0.1µF INTERNAL ADC
REFHB LOW REFERENCE

1742 F06b
1742 F05

Figure 5. Equivalent Reference Circuit Figure 6b. 2.5V Range ADC with External Reference
1742f

14
 LTC1742
U U W U
APPLICATIO S I FOR ATIO
LTC1742 5V

BIAS

TO INTERNAL
VDD 2V BIAS ADC CIRCUITS

6k
ANALOG INPUT ENC
0.1µF
CLOCK 1:4
INPUT
50Ω VDD 2V BIAS

6k
ENC

1742 F07

Figure 7. Transformer Driven ENC/ENC

3.3V

3.3V
MC100LVELT22 130Ω 130Ω
ENC Q0
VTHRESHOLD = 2V
ENC
D0
2V ENC LTC1742
ENC LTC1742
0.1µF Q0
83Ω 83Ω
1742 F08a

1742 F08b

Figure 8a. Single-Ended ENC Drive,

Not Recommended for Low Jitter Figure 8b. ENC Drive Using a CMOS-to-PECL Translator

Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at
both inputs as common mode noise.
The encode inputs have a common mode range of 1.8V to
VDD. Each input may be driven from ground to VDD for
single-ended drive.
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC1742 is 65Msps. For
the ADC to operate properly the encode signal should have
a 50% (±5%) duty cycle. Each half cycle must have at least
7.3ns for the ADC internal circuitry to have enough settling
time for proper operation. Achieving a precise 50% duty
cycle is easy with differential sinusoidal drive using a
transformer or using symmetric differential logic such as
PECL or LVDS. When using a single-ended encode signal
asymmetric rise and fall times can result in duty cycles that
are far from 50%.

1742f

15
LTC1742
U U W U
APPLICATIO S I FOR ATIO
At sample rates slower than 65Msps the duty cycle can
vary from 50% as long as each half cycle is at least 7.3ns.
The lower limit of the LTC1742 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC1742 is 1Msps.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
Output Loading
As with all high speed/high resolution converters the
digital output loading can affect the performance. The
digital outputs of the LTC1742 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
VDD
DATA PREDRIVER
FROM LOGIC
LATCH
OE
Figure 9. Equivalent Circuit for a Digital Output Buffer
16
output may be used but is not required since the ADC has
a series resistor of 43Ω on chip.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Format
The LTC1742 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MSBINV pin; high selects offset binary.
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. When OF outputs a logic high
the converter is either overranged or underranged.
Output Clock
The ADC has a delayed version of the ENC input available
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system.
This is necessary when using a sinusoidal encode. Data
will be updated just after CLKOUT falls and can be latched
on the rising edge of CLKOUT.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 3V
supply then OVDD should be tied to that same 3V supply.
LTC1742
OVDD
0.5V TO
VDD VDD
0.1µF
OVDD
43Ω TYPICAL
DATA
OUTPUT
OGND
1742 F09
1742f

U U W U
APPLICATIO S I FOR ATIO
OVDD can be powered with any voltage up to 5V. The logic
outputs will swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE low disables all data outputs including OF and
CLKOUT. The data access and bus relinquish times are too
slow to allow the outputs to be enabled and disabled
during full speed operation. The output Hi-Z state is
intended for use during long periods of inactivity. The
voltage on OE can swing between GND and OVDD. OE
should not be driven above OVDD.
GROUNDING AND BYPASSING
The LTC1742 requires a printed circuit board with a clean
unbroken ground plane. A multilayer board with an inter-
nal ground plane is recommended. The pinout of the
LTC1742 has been optimized for a flowthrough layout so
that the interaction between inputs and digital outputs is
minimized. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, VCM, REFHA, REFHB, REFLA and REFLB pins as
shown in the block diagram on the front page of this data
sheet. Bypass capacitors must be located as close to the
pins as possible. Of particular importance are the capaci-
tors between REFHA and REFLB and between REFHB and
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recomended. The large 4.7µF capacitor between REFHA
and REFLA can be somewhat further away. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
LTC1742
The LTC1742 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
An analog ground plane separate from the digital process-
ing system ground should be used. All ADC ground pins
labeled GND should connect to this plane. All ADC VDD
bypass capacitors, reference bypass capacitors and input
filter capacitors should connect to this analog plane. The
LTC1742 has three output driver ground pins, labeled
OGND (Pins 27, 38 and 47). These grounds should con-
nect to the digital processing system ground. The output
driver supply, OVDD should be connected to the digital
processing system supply. OVDD bypass capacitors should
bypass to the digital system ground. The digital process-
ing system ground should be connected to the analog
plane at ADC OGND (Pin 38).
HEAT TRANSFER
Most of the heat generated by the LTC1742 is transferred
from the die through the package leads onto the printed
circuit board. In particular, ground pins 12, 13, 36 and 37
are fused to the die attach pad. These pins have the lowest
thermal resistance between the die and the outside envi-
ronment. It is critical that all ground pins are connected to
a ground plane of sufficient area. The layout of the evalu-
ation circuit shown on the following pages has a low ther-
mal resistance path to the internal ground plane by using
multiple vias near the ground pins. A ground plane of this
size results in a thermal resistance from the die to ambient
of 35°C/W. Smaller area ground planes or poorly connected
ground pins will result in higher thermal resistance.
1742f
17
 Evaluation Circuit Schematic of the LTC1742

5V

18
R5 U3
1Ω LT1521-3 3V
3 1 U2 3V
IN OUT
10T74ALVC1G86
C3 4 2 C4 C23 R9
R8 TAB GND CLKOUT JP2 33Ω
10µF 4.7µF 0.1µF
LTC1742

0Ω CLKOUT J2
C28 3201S-40G1
0.1µF
R1** RA
1 2
J1 0Ω 24.9Ω
OPTIONAL 3 4
+INPUT 5 6
C24 C1 U5 U4
T1 R2 7 8
12pF 2µF LTC1742 P174VCX16373V
J3 MINICIRCUITS T1-1T 24.9Ω 9 10
ANALOG 1 48 25 24 11 12
U U

• • C8 SENSE OF 2LE 2OE 13 14

INPUT R3 R4 4.7µF 2 47 26 23 RN5A 33Ω 15 16
100Ω 100Ω VCM OGND 2D8 2Q8 17 18
C5
12pF RN5B 33Ω 19 20
C29 R7 3 46 27 22
GND D13 2D7 2Q7 21 22
1µF 24.9Ω C13 23 24
0.1µF 4 45 28 21 25 26
R10** AIN+ D12 GND GND
W

27 28
J4 0Ω 5 44 29 20 RN5C 33Ω 29 30
OPTIONAL AIN– D11 2D6 2Q6 31 32
– INPUT C18 R
B RN5D 33Ω 33 34
C25 4.7µF 24.9Ω 6 43 C12 0.1µF 30 19
12pF GND OVDD 2D5 2Q5 35 36
37 38
APPLICATIO S I FOR ATIO

7 42 31 18
VDD D10 VCC VCC 39 40
U

RN6A 33Ω
8 41 32 17
RX* VDD D9 2D4 2Q4
9 40 33 16 RN6B 33Ω
C26
GND D8 2D3 2Q3
0.1µF
10 39 34 15
REFLB D7 GND GND
RN6C 33Ω
11 38 35 14
REFHA OGND 2D2 2Q2
12 37 36 13 RN6D 33Ω
C8 C7
4.7µF 0.1µF GND GND 2D1 2Q1
13 36 37 12 RN7A 33Ω
ENCODE C9
T2 GND GND 1D8 1Q8
INPUT 0.1µF
MINICIRCUITS T1-1T 14 35 38 11 RN7B 33Ω
J5 REFLA D6 1D7 1Q7
• •
R21 15 34 39 10
100Ω JP5 R22 REFHB D5 GND GND
OPTIONAL 100Ω RN7C 33Ω
XTAL CLK C27 16 33 40 9
0.1µF GND D4 1D6 1Q6
C15
17 32 C10 0.1µF 41 8 RN7D 33Ω
0.1µF
VDD OVDD 1D5 1Q5
C11
C30 1µF 18 31 42 7
5V 0.1µF VDD D3 VCC VCC
C14
1 14 RN8A 33Ω
4.7µF 19 30 43 6
GND D2 1D4 1Q4
C31 20 29 44 5 RN8B 33Ω
0.1µF VDD D1 1D3 1Q3
4 11
Y1 21 28 45 4
C2 GND D0 GND GND
R6 0.1µF 22 27 46 3 RN8C 33Ω
C32
7 8 200Ω MSBINV OGND 1D2 1Q2
30pF
23 26 47 2
ENC CLKOUT 1D1 1Q1
JP1
C17 24 25 48 1
ENC OE E1 1LE 1OE
0.1µF
5V
5V
E3 E4 E5 E4
JP3 JP4 C16
GND GND GND RY* PGND C19 C20 C21 C22
10µF
0.1µF 0.1µF 0.1µF 0.1µF

INPUT TWOS 1742 TA01

*RX, RY = OPTIONAL INPUT RANGE SET RANGE COMPLEMENT

**DO NOT INSTALL R1 AND R10 SELECT SELECT

1742f
 LTC1742
U U W U
APPLICATIO S I FOR ATIO

Silkscreen Top Layer 1 Component Side

Layer 2 GND Plane Layer 3 Power Plane

Layer 4 Solder Side

1742f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19
LTC1742
U
PACKAGE DESCRIPTIO
FW Package
48-Lead Plastic TSSOP (6.1mm)
(Reference LTC DWG # 05-08-1651)

12.4 – 12.6*
(.488 – .496)

0.95 ±0.10 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

8.1 ±0.10 6.2 ±0.10

7.9 – 8.3
(.311 – .327)

0.32 ±0.05 0.50 TYP

RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

1.20
6.0 – 6.2**
(.0473)
(.236 – .244)
MAX
0° – 8°
-C- -T-
.10 C
0.45 – 0.75 0.50 0.17 – 0.27 FW48 TSSOP 0502
0.09 – 0.20 (.018 – .029) (.0197) (.0067 – .0106) 0.05 – 0.15
(.0035 – .008) BSC (.002 – .006)

NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

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LTC1412 12-Bit, 3Msps, Sampling ADC ±5V, No Pipeline Delay, 72dB SINAD
LTC1414 14-Bit, 2.2Msps ADC ±5V, 81dB SINAD and 95dB SFDR
LTC1420 12-Bit, 10Msps ADC 71dB SINAD and 83dB SFDR at Nyquist
LT®1461 Micropower Precision Series Reference 0.04% Max Initial Accuracy, 3ppm/°C Drift
LTC1666 12-Bit, 50Msps DAC Pin Compatible with the LTC1668, LTC1667
LTC1667 14-Bit, 50Msps DAC Pin Compatible with the LTC1668, LTC1666
LTC1668 16-Bit, 50Msps DAC 16-Bit, No Missing Codes, 90dB SINAD, –100dB THD
LTC1741 12-Bit, 65Msps ADC Pin Compatible with the LTC1742
LTC1743 12-Bit, 50Msps ADC Pin Compatible with the LTC1742
LTC1744 14-Bit, 50Msps ADC Pin Compatible with the LTC1742
LTC1745 12-Bit, 25Msps ADC Pin Compatible with the LTC1742
LTC1746 14-Bit, 25Msps ADC Pin Compatible with the LTC1742
LTC1747 12-Bit, 80Msps ADC Pin Compatible with the LTC1742
LTC1748 14-Bit, 80Msps ADC Pin Compatible with the LTC1742
LT1807 325MHz, Low Distortion Dual Op Amp Rail-to-Rail Input and Output
1742f

Linear Technology Corporation LT/TP 0603 1K • PRINTED IN THE USA

20 1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ●
www.linear.com  LINEAR TECHNOLOGY CORPORATION 2003
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Datasheets for electronics components.