2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)

A New Generalized Grounded Impedance

Scaling Configuration with Electronic/Resistor
Tunability
Suraj Das K Kogara Naveen Kumar
Department of ECE Department of ECE
NIT Jamshedpur NIT Jamshedpur
Jamshedpur, India Jamshedpur, India
ksuraj98@gmail.com kogaranaveenkumar@gmail.com

Pappala Chandra Mouli Mayank Srivastava

Department of ECE Department of ECE
NIT Jamshedpur NIT Jamshedpur
Jamshedpur, India Jamshedpur, India
chandramouli.pappala@gmail.com mayank2780@gmail.com

Abstract— In this research article, an active configuration
is proposed which acts similar to a impedance multipliar
configuration. This configuration is able to increase or
decrease the impedance of any grounded passive network . The
presented circuit configuration employs two VDCCs and three
grounded resistances along with the impedance to be
multiplied. The scaling of impedance can be achieved through
resistance variation or bias current variation. The use of only
grounded passive elements enhance the suitability for on-chip
integration. The working of the presented design has been
investigated under non-ideal environment. The validation of
behavior of the proposed multiplier circuit has been confirmed
by designing and simulating an active filter. All the simulations
have been performed in PSPICE Environment with 0.18μm
CMOS technology.
with electronic/ resistive scaling. The developed circuit
configuration employs only two VDCCs and three grounded
resistances. This circuit is free from passive/active element
matching constraints and works satisfactorily non-ideal
conditions.
II. CIRCUIT IDEA VDCC
VDCC is a modern active component described in
[15] very first time. It can be viewed as a cascaded
combination of an operational transconductance amplifier
and 2nd generation current conveyor. It is a 6-terminal
device. The generalized block representation of VDCC is
given in Figure 1.

Keywords—Electronic tuning, Grounded impedance scaling,

Resistive tuning, VDCC.

I. INTRODUCTION
Active realization of passive elements is a very
widespread research problem among circuit designers and
scientists. The on-chip realization of inductors, large value
capacitors and resistances is not recommended from the
viewpoint of efficient chip area realization, as large Fig.1. Block representation of VDCC
impedances consume significant area on the chip. Therefore,
impedance scaling circuits/ multipliers employing active The realization of VDCC using CMOS transistors
elements are very useful for such applications. In literature, is described in Fig.2[16]. The terminals N and P are input
numerous impedance simulation circuits have been voltage ports while Wp, Wn are output current ports. The
proposed by several researchers [1-14]. Some of these terminals Z and X are auxiliary terminals.
impedance simulation circuits are able to realize grounded
impedance multiplication also. But these circuits have one
or more following given disadvantages.
1. Employment of passive elements (Resistances and
Capacitances) in floating form [1-6], [7-9], [10],
[11-14].
2. Non-electronic scaling [1-5], [6], [7-9], [10], [11-
14].
3. Requirements for matched active/passive elements
[1-3], [7], [10], [12-14].

Therefore, the main aim of this research effort is to

present a VDCC based impedance (grounded) scaling circuit Fig.2. CMOS realization of VDCC[21]

XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE

978-1-7281-1380-7/19/$31.00 ©2019 IEEE 811
1
 Currents and voltages at different ports of VDCC
can be described by equations (1), (2), (3) & (4). Where ‘gm’ (7)
is transconductance gain of VDCC. (8)
(9)
(1) (10)
(2)
To study the effects of non-ideal conditions, the
(3) developed configuration is evaluated using non-ideal VDCC
equations (7), (8), (9), (10). The expression of input
(4) impedance in this case can be found as,
In the last one decade, several analog processing/
signal generation configurations have been developed by = (11)
several circuit designers [17-22].

III. PROPOSED GROUNDED IMPEDANCE SCALING Where (12)

CONFIGURATION
The developed impedance multiplier circuit
Where Į1 and Į2 are transconductance errors, ȕ1 and ȕ2 are
configuration consisting two VDCCs along with three
voltage transfer errors associated with VDCC1 and VDCC2
grounded resistances has been illustrated in Fig 3.
respectively.
Where is the current transfer error of VDCC-1.
So, from expression (11), it can be observed that
the behavior of designed multiplier configuration is
unaffected under non-ideal environment as no lossy term is
added. The sensitivity values of multiplication factor “K1”
corresponding to passive/active parameter values can be
evaluated as,
, , , ,
, , , ,
(13)
As magnitudes of all the sensitivity indexes are equal to
or less than one, the proposed configuration is less sensitive.

Fig.3. Proposed Grounded Impedance scaling configuration.
On circuit analysis of configuration of Fig 3,the impedance
of this configuration is evaluated as
(5)
V. APPLICATION EXAMPLE
The working of developed impedance scaling
circuits is validated by an active filter design example.
A simple single order high-pass filter is derived
employing the proposed configuration as a grounded
resistor. The conventional RC high-pass filtering circuit is
given in Fig.4.

Where (6)

Where gm1 and gm2 are transconductance gains associated

with VDCC-1 and VDCC-2 respectively.
Now it can be shown from equation (5) that
presented configuration can scale down or scale up the
impedance of “Z” by a multiplication factor of K.
From equation (6), it can be seen that the value of
‘K’ can be varied by gm1/gm2/R2/R3. Therefore, both resistive
as well as electronic scaling is possible. ‘Z’ can be a single
passive element or a combination of passive elements.

IV. NON-IDEAL PERFORMANCE

On considering non ideal voltage-current transfer
Fig.4. Conventional RC High-Pass Filtering circuit
constants among various VDCC terminals, the defining
equations of VDCC can be modified as

812
 6
10
R2=1KOhm R2=4KOhm
R2=2KOhm

Impedance(Ohm)
4
10

2
10

0
10 4 5 6 7 8
10 10 10 10 10
Frequency(Hz)

Fig.7. Resistive scaling of Z = through resistance R2.

8
10

R2=4KOhm

Impedance(Ohm)
6 R2=2KOhm
10 R2=1KOhm

4
10

2
10 4 5 6 7 8
10 10 10 10 10
Frequency(Hz)
Fig.8. Resistive scaling of Z = SL1 through resistance R2.
To show the electronic scaling of Z through bias
currents of employs VDCC, the simulations were executed
for various values of biasing currents. To demonstrate the
electronic scaling of 1 KŸ resistor connected at the place of
Fig.5. Active implementation of passive RC High Pass Filtering circuit
Z1, simulations have been performed for Ib1 of both VDCCs
using proposed configuration. equal to 50μA, 30μA, 10μA keeping Ib2 at a constant value
of 10μA. The frequency response plots are shown in Fig.9.
The active equivalent of the filtering configuration 10
6

of Fig.4 is illustrated in Fig.5 by replacing passive resistance Ib1=10uA

by presented configuration working in grounded resistance Ib1=50uA

Im pedance(Ohm )

mode.
5
10 Ib1=30uA

VI. SIMULATION RESULTS 10

4

To validate the performance of the developed 10 4

3
5 6 7
circuit as a grounded-impedance scaling configuration, the 10 10 10
Frequency(Hz)
10

simulations in PSPICE tool have been executed. For Fig.9. Electronic scaling of Z=R1 through different bias currents (Ib1) of
PSPICE simulations CMOS model of VDCC is VDCC -1 and VDCC-2
demonstrated in Fig 2. To study the electronic scaling of grounded
To demonstrate the working of the developed circuit capacitance C1 (C1=0.01mF) connected in place of Z1, again
configuration as a grounded resistance scaling circuit, Z1 is the simulations were run for different set of biasing currents
considered as resistance of value of 1KŸ. The scaling of (I1 of both VDCCs equal to 50μA, 30μA and 10μA keeping
this grounded resistance through R2 is demonstrated in Fig.6 Ib2 at a constant value of 100μA). The simulation results are
which indicates the input impedances at different values of given in Fig.10. Similarly, electronic scaling of grounded
R2 with R3 equal to 1KŸ, gm1=gm2=277μA/v (Ib1=50μA, inductance value 0.1mH is demonstrated in Fig.11.
8
Ib2=100μA). If we consider , the scaling of Z with 10
Ib1=10uA
Ib1=30uA
Co=0.01nF through R2 has been shown in Fig 7. On Ib1=50uA
Im pedance(O hm )

considering Z=LoS the scaling of Z through R2 has been

6
10

shown in Fig 8.
4
x 10
3.5 4
10
3
Impedance(Ohm)

2.5
R2=1KOhm 2
2 R2=4KOhm 10 4 5 6 7 8
1.5 R2=2KOhm 10 10 10 10 10
Frequency(Hz)
1
Fig.10. Electronic scaling of Z = through different bias currents (Ib1) of
0.5

0 4
VDCC -1 and VDCC-2.
5 6 7
10 10 10 10
Frequency(Hz)
Fig.6. Resistive scaling of Z=R1 through resistance R2.

813
 10
8 [4] Senani R, ‘Active simulation of inductors using current
Ib1=10uA
Ib1=50uA
conveyors’ Electronics Letters, volume-14, no. 15, pp. 483-484,
Im p e d a n ce (O h m ) 1976.
6
10
Ib1=30uA [5] Dutta Roy S.C, ‘On operational amplifier simulation of
grounded Inductance’ Archiv fuer Elektronik und
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4 Uebertragungstechnik, volume-29, pp. 107-115, 1975.

[6] Paul A. N. and Patranabis D., ‘Active simulation of grounded

10 4
2 inductors using a single current conveyor’ IEEE Transactions on
5 6 7 8
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10
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