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Experiment 1:: Design All Gates Using VHDL
Experiment 1:: Design All Gates Using VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity and_2 is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC
);
end and_2;
begin
c <= a and b;
end and_2_dataflow;
// Waveform
// Design and verify for the operation of OR gate
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity or_2 is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC
);
end or_2;
begin
c <= a or b;
end or_2_dataflow;
// Waveform
// Design and verify for the operation of XOR gate
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity xor_2 is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC
);
end xor_2;
begin
c <= a xor b;
end xor_2_dataflow;
// Waveform
Experiment 2: Write VHDL programs for the following circuits, check the
waveforms and hardware generated
// Design and verify the operation of a half adder
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity half_adder is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
);
end half_adder;
begin
end half_adder_dataflow;
// Design and verify the operation of a full adder
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity full_adder is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
);
end full_adder;
begin
end full_adder_dataflow;
Experiment 3: Write a VHDL program and check the waveform and hardware
generated for a 4:1 multiplexer.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity multiplexer4_1 is
port(
i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3 : in STD_LOGIC;
);
end multiplexer4_1;
begin
i3;
end multiplexer4_1_dataflow;