-- Company: unad

-- Engineer: Carlos Arturo Fajardo

-- alumno:Carlos Andres Gonzalez

-- Create Date: 11/19/2018 08:40:22 PM

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity alto_nivel is

Port (

ENTRADA_COMPONENTE_1,RESET,CLK : in STD_LOGIC;

COMPONENTE_2 : out STD_LOGIC_VECTOR (3 downto 0);

COMPONENTE_3 : out STD_LOGIC_VECTOR (3 downto 0));

end alto_nivel;

architecture Behavioral of alto_nivel is

component componente1

Port ( sensor :in STD_LOGIC;

clk:in STD_LOGIC;

reset:in STD_LOGIC;

Q:out STD_LOGIC);

end component;

component componente2

Port (
 clk:in STD_LOGIC;

reset:in STD_LOGIC;

enable:in STD_LOGIC;

comp:out STD_LOGIC;

Q:out STD_LOGIC_VECTOR (3 downto 0));

end component;

component componente3

Port(

clk:in STD_LOGIC;

enable:in STD_LOGIC;

reset:in STD_LOGIC;

salida:out STD_LOGIC_VECTOR (3 downto 0));

end component;

signal A0,A1:STD_LOGIC;

begin

UO: componente1 Port map(

sensor => ENTRADA_COMPONENTE_1,

clk => CLK,

reset => RESET,

Q => A0

);

U1:componente2 Port map(

enable => A0,

clk => CLK,

reset => RESET,

comp => A1,

Q => COMPONENTE_2

);

U2:COMPONENTE3 Port map(

enable => A1,

clk => CLK,

reset => RESET,

salida => COMPONENTE_3

);

clk: in STD_LOGIC;

enable: in STD_LOGIC;

reset: in STD_LOGIC;

salida:out STD_LOGIC_VECTOR (3 downto 0));

end component;

signal A0,A1 :STD_LOGIC;

begin

UO: COMPONENTE_1 Port map(

sensor => ENTRADA_componente_1,

clk => CLK,

reset => RESET,

Q => A0
);

U1:COMPONENTE_2 Port map(

enable => A0,

clk => CLK,

reset => RESET,

comp => A1,

Q => componente

);

U2:COMPONENTE_3 Port map(

enable => A1,

clk => CLK,

reset => RESET,

salida => componente

end Behavioral;