5 4 3 2 1

D D

C C

B B

A A

Title REV: V10

Page Name = 00_Block Diagram
DOCUMENT NO.: Size
Design Name = 98870_1_11_201906141113 D

DEPARTMENT: DEPARTMENT = WINGTECH-SZ

DESIGNER: DESIGNER = YANGSHAOYU

Date: Page Modify Date = Friday, June 14, 2019 Sheet 1 of 65

5 4 3 2 1
 5 4 3 2 1

I2C AP, SCP, SSPM Function I2C Spec. Budget Timing I2C Address

D I2C-0 AP CTP Yes. ILI9881H I2C address: Write:0xAA, Read:0xAB D

400 Kbps
TMD27504 I2C Address ：Write: 0x92, Read: 0x93
ALS and P Sensor 400 Kbps Yes. MN58406DKDN I2C Address ：Write: 0x82, Read: 0x83
I2C-1(I3C) TSL2560 I2C address: (Write:0x72, Read:0x73
AP ,SCP Yes.
Ambient Light Sensor 400 Kbps MN26005UKDN I2C address: Write:0x92, Read:0x93

Front Camera - 8M 400 Kbps S5K4H7YX03-FGX9 I2C address: Write:0x20, Read:0x21

Yes.
I2C-2 (I3C) AP
Main Camera - 13M 400 Kbps Yes. S5K3L6XX03-FGX9 I2C address: Write:0x5A, Read:0x5B

DRV2624 I2C address: Write:0xB4, Read:0xB5

HAPTIC DRIVER 400K bps Yes. AW8624 I2C address: Write:0xB4, Read:0xB5

400K bps Yes. A96T346DFP I2C address: Write:0x40, Read:0x41

Sar Sensor
I2C-3 AP
400K bps Yes. TAS2563 I2C address: Write:0x9A, Read:0x9B
Smart PA1

C
Smart PA2 400K bps Yes. TAS2563 I2C address: Write:0x9C, Read:0x9D C

400 Kbps Yes. S5K4H7YX03-FGX9 I2C address: Write:0x20, Read:0x21

Wide Camera - 8M
I2C-4 (I3C) AP
400 Kbps Yes. OV02A10-GA4A I2C address: Write:0x7A, Read:0x7B
Depth Camera - 2M

Charger 400 Kbps Yes. RT9471D I2C address: Write:0xA6, Read:0xA7

I2C-5 TUSB320 I2C address: Write:0x8E, Read:0x8F

SSPM
CC Logic 400 Kbps Yes. RT1711 address: Write:0x9C, Read:0x9D

LCD Bias 400 Kbps Yes. SM5109 I2C address: Write:0x7C, Read:0x7D
OCP2131 I2C address: Write:0x7C, Read:0x7D

Note : I2C Spec. : Standard mode (100 kbps) and Fast mode (400 kbps), Fast mode Plus (1 Mbps) and High-speed mode (3.4 Mbps)

B
SPI B

A A

Title REV: V10

Page Name = 00_I2C_SPI_Overview
DOCUMENT NO.: Size
Design Name = 98870_1_11_201906141113 D

DEPARTMENT: DEPARTMENT = WINGTECH-SZ

DESIGNER: DESIGNER = YANGSHAOYU

Date: Page Modify Date = Friday, June 14, 2019 Sheet 2 of 65

5 4 3 2 1
 5 4 3 2 1

[9] DVDD_MODEM
[9] DVDD_GPU
U101E
C101 22uF;20%;6.3V;0603 MT6771-DDR4 C102 22uF;20%;6.3V;0603

C103 22uF;20%;6.3V;0603 MT6771-SBS C104 22uF;20%;6.3V;0603

Schematic design notice of "10_BB_POWER_PDN" page.
[9] DVDD_MODEM_PMIC_FB
[9] DVDD_MODEM_PMIC_GND
Note: 10-3 VMODEM VGPU Note: 10-1 DVDD_GPU_PMIC_FB
DVDD_GPU_PMIC_GND
[9]
[9]
AA15 J19
AA19 DVDD_MODEM1 DVDD_GPU1 J20 Note 10-1: Differential pair of DVDD_GPU remote sense
DVDD_MODEM2 DVDD_GPU2
SH101 1 L1 2 SH102 1 L1 2
AB16
AB20 DVDD_MODEM3 DVDD_GPU3
L19
M20 SH103 1 L1 2 SH104 1 L1 2
must be close to BB's ball.
AC15 DVDD_MODEM4 DVDD_GPU4 N19
AC19 DVDD_MODEM5 DVDD_GPU5 P20 Remote sense trace with GND shielding to PMIC (Differential)
D
C105 1.0UF;20%;6.3V;0201 AD16 DVDD_MODEM6 DVDD_GPU6 R19 C106 1.0UF;20%;6.3V;0201 D
DVDD_MODEM7 DVDD_GPU7 T20
C107 1.0UF;20%;6.3V;0201 DVDD_GPU8 C108 1.0UF;20%;6.3V;0201
Note 10-2: Differential pair of DVDD_PROC remote sense
C109 1.0UF;20%;6.3V;0201 C110 1.0UF;20%;6.3V;0201 must be close to BB's ball
C111 1.0UF;20%;6.3V;0201 C112 1.0UF;20%;6.3V;0201
Remote sense trace with GND shielding to PMIC (Differential)
C113 1.0UF;20%;6.3V;0201 C114 1.0UF;20%;6.3V;0201

C115 1.0UF;20%;6.3V;0201 C116 1.0UF;20%;6.3V;0201

Note 10-3: Differential pair of DVDD_MODEM remote sense must be
close to BB's ball.
[4,9] DVDD_CORE
Remote sense trace with GND shielding to PMIC (Differential)
[10] DVDD_VSRAM_GPU_PMU
VCORE VGPU SRAM
C117 22uF;20%;6.3V;0603 H21 T18 C118 0.1uF;20%;6.3V;0201
J11 DVDD_CORE1 DVDD_SRAM_GPU Note 10-4: Differential pair of DVDD_CORE remote sense must be
DVDD_CORE2
C119 22uF;20%;6.3V;0603 J16
K12 DVDD_CORE3
C120 0.1uF;20%;6.3V;0201 close to BB's ball.
K16 DVDD_CORE4
L11 DVDD_CORE5 [9] DVDD_PROC_B Remote sense trace with GND shielding to PMIC (Differential)
L15 DVDD_CORE6
[9] DVDD_CORE_PMIC_FB Note: 10-4 M12 DVDD_CORE7
[9] DVDD_CORE_PMIC_GND DVDD_CORE8
M16 C121 10uF;20%;6.3V;0402
N11 DVDD_CORE9
N15 DVDD_CORE10 C122 22uF;20%;6.3V;0603
SH106 1 2L1 SH105 1 L1 2 P7 DVDD_CORE11
P12 DVDD_CORE12 C123 10uF;20%;6.3V;0402
DVDD_CORE13
VPROC1
P16
C124 1.0UF;20%;6.3V;0201 P21 DVDD_CORE14
R7 DVDD_CORE15 AA10
Note: 10-2 DVDD_PROC_B_PMIC_FB [9]
DVDD_CORE16 DVDD_PROC_B1 DVDD_PROC_B_PMIC_GND [9]
C125 1.0UF;20%;6.3V;0201 R8 AB9
R11 DVDD_CORE17 DVDD_PROC_B2 AC9
C126 1.0UF;20%;6.3V;0201 R15 DVDD_CORE18 DVDD_PROC_B3 AC10
DVDD_CORE19 DVDD_PROC_B4 L1
C T7 AC11 SH107 1 L1 2 SH108 1 2 C
C127 1.0UF;20%;6.3V;0201 T8 DVDD_CORE20 DVDD_PROC_B5 AD9
T12 DVDD_CORE21 DVDD_PROC_B6 AD10
C128 1.0UF;20%;6.3V;0201 T16 DVDD_CORE22 DVDD_PROC_B7 C129 1.0UF;20%;6.3V;0201
U15 DVDD_CORE23
C130 1.0UF;20%;6.3V;0201 U19 DVDD_CORE24 C131 1.0UF;20%;6.3V;0201
U21 DVDD_CORE25
V16 DVDD_CORE26 C132 1.0UF;20%;6.3V;0201
V20 DVDD_CORE27
W15 DVDD_CORE28 C133 1.0UF;20%;6.3V;0201
W19 DVDD_CORE29
Y16 DVDD_CORE30 C134 1.0UF;20%;6.3V;0201
Y20 DVDD_CORE31
AB7 DVDD_CORE32 C135 1.0UF;20%;6.3V;0201
AB22 DVDD_CORE33
AC22 DVDD_CORE34 C136 1.0UF;20%;6.3V;0201
AD7 DVDD_CORE35
DVDD_CORE36 C137 1.0UF;20%;6.3V;0201

C138 1.0UF;20%;6.3V;0201

[10] DVDD_SRAM_CORE [10] DVDD_SRAM_PROC_B

VCORE SRAM VPROC1 SRAM
J12 AC13 C139 0.1uF;20%;6.3V;0201
T11 DVDD_SRAM_CORE1 DVDD_SRAM_PROC_B
C140 0.1uF;20%;6.3V;0201 V21 DVDD_SRAM_CORE2 C141 0.1uF;20%;6.3V;0201
Y15 DVDD_SRAM_CORE3
C142 0.1uF;20%;6.3V;0201 AC14 DVDD_SRAM_CORE4
DVDD_SRAM_CORE5

[9] DVDD_PROC_L

B B

[9,10,19,20] EMI_VDD2 C143 22uF;20%;6.3V;0603

VDD2 VPROC2 C144 22uF;20%;6.3V;0603

G18 U7 DVDD_PROC_L_PMIC_FB [9]

H11 AVDD2_EMI1 DVDD_PROC_L1 U8
C145 22uF;20%;6.3V;0603 H13 AVDD2_EMI2 DVDD_PROC_L2 U9
Note: 10-2 DVDD_PROC_L_PMIC_GND [9]
H16 AVDD2_EMI3 DVDD_PROC_L3 U10
C146 10uF;20%;6.3V;0402 AVDD2_EMI4 DVDD_PROC_L4 W9
DVDD_PROC_L5 W11
DVDD_PROC_L6 SH109 1 L1 2 SH110 1 L1 2

C147 1.0UF;20%;6.3V;0201

C148 1.0UF;20%;6.3V;0201 C149 1.0UF;20%;6.3V;0201

C150 1.0UF;20%;6.3V;0201 C151 1.0UF;20%;6.3V;0201

C152 1.0UF;20%;6.3V;0201 C153 1.0UF;20%;6.3V;0201

C154 1.0UF;20%;6.3V;0201

C155 1.0UF;20%;6.3V;0201

C156 1.0UF;20%;6.3V;0201
[10,19,20] EMI_VDDQ
C163 1.0UF;20%;6.3V;0201

[10] DVDD_SRAM_PROC_L

VDDQ VPROC2 SRAM

C157 1.0UF;20%;6.3V;0201 G14 W7 C158 0.1uF;20%;6.3V;0201
G15 AVDDQ_EMI1 DVDD_SRAM_PROC_L
C159 1.0UF;20%;6.3V;0201 H10 AVDDQ_EMI2 C160 0.1uF;20%;6.3V;0201
A A
H12 AVDDQ_EMI3
C161 1.0UF;20%;6.3V;0201 H17 AVDDQ_EMI4
H19 AVDDQ_EMI5
C162 1.0UF;20%;6.3V;0201 AVDDQ_EMI6
Title REV: V10
01_BB_POWER_PDN
DOCUMENT NO.: Design Name Size C

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 3 of 65

5 4 3 2 1
 5 4 3 2 1

U101F
MT6771-DDR4 VA12_PMU [4,10]

MT6771-SBS C201

GND AVDD 0.1uF;20%;6.3V;0201

Schematic design notice of "11_BB_POWER_IO" page.
A21 AH20
B9 DVSS1 AVDD12_MD
B13 DVSS2
B21 DVSS3
DVSS4 AVDD18_MD
AH19
AVDD18_SOC [4,10]
Note 11-1: C216 closed DVDD18_MSDC0 150mil
B23
D
B25 DVSS5
DVSS6 AVDD18_CPU
AC7 AVDD18_SOC [4,10]
C217 closed DVDD18_MSDC1 150mil D
C3
C6 DVSS7 AH21
DVSS8 AVDD18_AP AVDD18_SOC [4,10]
C10
C11 DVSS9
DVSS10 AVDD18_DDR
G9 EMI_VDD1 [17,19]
Note 11-2: C218 closed DVDD28_MSDC1 150mil
C18
C19 DVSS11
C24 DVSS12 C202 C203 C204 C205 C206
D3 DVSS13
DVSS14 0.1uF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
D12
D16 DVSS15
DVSS16
Note 11-3: Connects "AVDD09_SSUSB" to GND
PLL
D21
E2 DVSS17
DVSS18
when USB3.0 is not used.
E3 AA13
DVSS19 AVDD12_PLLGP VA12_PMU [4,10]
E4
E14 DVSS20 AB13
E15 DVSS21
DVSS22
AVDD18_PLLGP AVDD18_SOC [4,10]
Note 11-4: Connects "AVDD09_UFS" to GND when UFS is not used.
E26
F3 DVSS23 C207 C208
F4 DVSS24
DVSS25 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 [4] VIO18_PMU_AP
F5
F9 DVSS26
DVSS27
PERI_D
F10
F11 DVSS28
F17 DVSS29 L2
F18 DVSS30 DVDD18_IORT AA1
F19 DVSS31 DVDD18_IORB
G3 DVSS32 W27 SH201 1 2
DVSS33 DVDD18_IOLM VIO18_PMU [5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63]
G4 M27
DVSS34 DVDD18_IOLT SINGLE-GND-L4
G5
G6 DVSS35 AJ21
G21 DVSS36 DVDD18_IOBL
H2 DVSS37
H24 DVSS38 C209 C210 C211 C212 C213 C214 C215
H25 DVSS39
DVSS40 NF_0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201
H26
J3 DVSS41
J8 DVSS42
C C
J10 DVSS43
J13 DVSS44 F24
DVSS45 DVDD_VQPS VEFUSE_PMU [10]
J17
J23 DVSS46
J26 DVSS47 E27
DVSS48 DVDD18_MSDC0 VIO18_PMU_AP [4]
K10
K14 DVSS49 AA27
DVSS50 DVDD18_MSDC1 VIO18_PMU_AP [4]
K18
K24 DVSS51 AB27
DVSS52 DVDD28_MSDC1 VMC_PMU [10]
K25
L1 DVSS53
L9 DVSS54 C216 C217 C218 C219
L13 DVSS55
L17 DVSS56 Note: 11-1 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
M5 DVSS57
M10 DVSS58
M14 DVSS59 Note: 11-2
M18 DVSS60 AG27
DVSS61 DVDD18_SIM VIO18_PMU_AP [4]
N9
N13 DVSS62 AF25
DVSS63 DVDD28_SIM1 VSIM1_PMU [10,31]
N17
N21 DVSS64 AE27
DVSS65 DVDD28_SIM2 VSIM2_PMU [10,31]
P10
P14 DVSS66
P18 DVSS67 C220 C221 C222
R9 DVSS68
DVSS69 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201
R13
R17 DVSS70
DVSS71
PERI_A
R26
T10 DVSS72
T14 DVSS73 V27
DVSS74 AVDD04_DSI DVDD_CORE [3,9]
T21
U5 DVSS75 V23
U13 DVSS76 AVDD12_DSI
U17 DVSS77
U23 DVSS78 W3
DVSS79 AVDD12_CSI VA12_PMU [4,10]
V5
B
V8 DVSS80 B
V9 DVSS81 C223 C224 C225
V10 DVSS82
DVSS83 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
V12
V14 DVSS84
V18 DVSS85
V26 DVSS86
W1 DVSS87 H22
DVSS88 AVDD12_USB VA12_PMU [4,10]
W12
W13 DVSS89 F27
DVSS90 AVDD18_USB AVDD18_SOC [4,10]
W17
W21 DVSS91 F25
DVSS92 AVDD33_USB VUSB_PMU [10]
Y8
Y9 DVSS93 K27
Y10 DVSS94 AVDD09_SSUSB
Y14 DVSS95 H23
DVSS96 AVDD18_SSUSB AVDD18_SOC [4,10]
Y18
AA12 DVSS97
AA17 DVSS98
AA21 DVSS99 Note: 11-3 C226 C227 C228 C229
AB8 DVSS100
DVSS101 0.1uF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
AB14
AB18 DVSS102
AB21 DVSS103
AC12 DVSS104
AC17 DVSS105
AD8 DVSS106
AE10 DVSS107 C2
DVSS108 AVDD12_WBG VA12_PMU [4,10]
AE14
AE15 DVSS109 B2
DVSS110 AVDD18_WBG AVDD18_SOC [4,10]
AE16
AF8 DVSS111
AF9 DVSS112 C230 C231
AF15 DVSS113
DVSS114 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201
AG8
AG9 DVSS115
AG15 DVSS116
AH8 DVSS117
A A
AH9 DVSS118 C22
AH15 DVSS119 AVDD09_UFS
AH18 DVSS120 C23
Note: 11-4
DVSS121 AVDD12_UFS VA12_PMU [4,10]
AJ9
DVSS122 Title REV: V10
AVDD18_UFS
D23 AVDD18_SOC [4,10] 02_BB_POWER_IO
DOCUMENT NO.: Design Name Size C

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 4 of 65

5 4 3 2 1
 5 4 3 2 1

VIO18_PMU U101A U101B

Note: 12-1 MT6771-DDR4 MT6771-DDR4

R301
MT6771-DDR4 MT6771-SBS
12K;5%;0201
PMU_IF SIM 26M
[11] SYSRSTB K23 [31] SIM1_SCLK AE23 AE17 PMIC_CLK_BB [13]
SYSRSTB AF24 SIM1_SCLK MAIN_X26M_IN
[31] SIM1_SIO SIM1_SIO
[11] WATCHDOG M23 [31] SIM1_SRST AE22
WATCHDOG SIM1_SRST
R302 PWRAP_SPI0_CSN AG24
[31] INT_SIM1 INT_SIM1
NF_12K;5%;0201
ABB_IF
N23
[11] PWRAP_SPI0_CSN PWRAP_SPI0_CSN AD23
[31] SIM2_SCLK SIM2_SCLK
P23 [31] SIM2_SIO AE24 AG11
[11] PWRAP_SPI0_CK PWRAP_SPI0_CK AE25 SIM2_SIO TX_BB_IP1 AF11
7,40,41,46,49,63 VIO18_PMU [31] SIM2_SRST SIM2_SRST TX_BB_IN1
P25
D [11] PWRAP_SPI0_MO PWRAP_SPI0_MO AG25 D
[31] INT_SIM2 INT_SIM2
Note: 12-2 P24 AF12
[11] PWRAP_SPI0_MI PWRAP_SPI0_MI TX_BB_QP1 AG12
TX_BB_QN1
R303

RFI_C
NF_12K;5%;0201 [12] AUD_CLK_MISO M25 AF13 LTE_TX_BB_IP0 [37]
AUD_CLK_MISO TX_BB_IP0 AG13
TX_BB_IN0 LTE_TX_BB_IN0 [37]
N24 [37] RFIC0_BSI_EN AE21
AUD_DAT_MISO0 [12] AUD_DAT_MISO0 AUD_DAT_MISO0 RFIC0_BSI_EN
L23 [37] RFIC0_BSI_CK AF21 AF14 LTE_TX_BB_QP0 [37]
AUD_DAT_MISO1 [12] AUD_DAT_MISO1 AUD_DAT_MISO1 RFIC0_BSI_CK TX_BB_QP0 AG14
TX_BB_QN0 LTE_TX_BB_QN0 [37]
[12] AUD_SYNC_MISO M26 [27] REAR_CAM_DVDD_EN AG20
AUD_SYNC_MISO RFIC0_BSI_D2
R304 R305 AE20 AF16
[37] RFIC0_BSI_D1 RFIC0_BSI_D1 PRX_BB_I1 LTE_PRX_BB_I1 [37]
12K;5%;0201 AJ16 LTE_PRX_BB_I0 [37]
M24 AF20 PRX_BB_I0
12K;5%;0201 [12] AUD_CLK_MOSI AUD_CLK_MOSI [37] RFIC0_BSI_D0 RFIC0_BSI_D0

[12] AUD_DAT_MOSI0 J22 AG16 LTE_PRX_BB_Q1 [37]

AUD_DAT_MOSI0 PRX_BB_Q1 AJ15
PRX_BB_Q0 LTE_PRX_BB_Q0 [37]
[12] AUD_DAT_MOSI1 N27
7,40,41,46,49,63 VIO18_PMU AUD_DAT_MOSI1

RF MIPI
[12] AUD_SYNC_MOSI L26 AG17 LTE_DRX_BB_I1 [37]
AUD_SYNC_MOSI DRX_BB_I1 AH16
DRX_BB_I0 LTE_DRX_BB_I0 [37]
AD6
AE6 MISC_BSI_CK_3
R306 MISC_BSI_DO_3 AF17
DRX_BB_Q1 LTE_DRX_BB_Q1 [37]
NF_12K;5%;0201 [34,49] MIPI2_SCLK AF6 AH17 LTE_DRX_BB_Q0 [37]
AG6 MISC_BSI_CK_2 DRX_BB_Q0
[34,49] MIPI2_SDATA MISC_BSI_DO_2
AUD_DAT_MOSI0 AH7 AH12
[41] MIPI1_SCLK MISC_BSI_CK_1 DET_IP1
BC_IF [41] MIPI1_SDATA AG7 AH11
MISC_BSI_DO_1 DET_IN1
R307 [15] CHD_DP G25 [46] MIPI0_SCLK AJ7
CHD_DP AJ8 MISC_BSI_CK_0 AH10
12K;5%;0201 [46] MIPI0_SDATA MISC_BSI_DO_0 DET_QP1
[15] CHD_DM G24 AJ10
CHD_DM DET_QN1

SCP_IF BPI
C AJ13 LTE_DET_BB_IP0 [37] C
DET_IP0 AJ12
DET_IN0 LTE_DET_BB_IN0 [37]
[13] SCP_VREQ_VAO N25 AG4
SCP_VREQ_VAO BPI_PA_VM1
Note: 12-1 AH3 AH14
BPI_PA_VM0 DET_QP0 LTE_DET_BB_QP0 [37]
32K
AH13 LTE_DET_BB_QN0 [37]
AJ25 DET_QN0
[48] BPI_ANT2 BPI_ANT2
[13] RTC32K_CK K26
RTC32K_CK AJ4 AE13
[52] BPI_ANT1 BPI_ANT1 APC APC1 [41]

SRCLKEN [48] BPI_ANT0 AJ24

BPI_ANT0
R24 [28] TORCH_EN AH26
[13,37] SRCLKENA1 SRCLKENA1 BPI_OLAT1
R23 [26] BL_ISET_EN AH4
[13] SRCLKENA0 SRCLKENA0 BPI_OLAT0

[40] BPI_BUS10
AJ22 ET
BPI_BUS10
SRCLKEN AI
AE11
AH22 RFIC_ET0_P AE12
[15] EINT_CHG_0 BPI_BUS9 RFIC_ET0_N
W5
SRCLKENAI AJ26
[48] BPI_BUS8 BPI_BUS8

[51] BPI_BUS7 AH6

BPI_BUS7
PLLs Test Pin [26] GPIO_CTP_RSTB AJ5
Y13 BPI_BUS6
TP_PLLGP1 AD5
[41] BPI_BUS5 BPI_BUS5
Y12
TN_PLLGP1
AUX IN
[41] BPI_BUS4 AE5
BPI_BUS4
J15 AF5 AG18
Note: 12-3
EMI_TP [40] BPI_BUS3 BPI_BUS3 AUXIN4 HW_ID [8]
J14 [40] BPI_BUS2 AG5 AE18 BAT_ID [8,22]
EMI_TN BPI_BUS2 AUXIN3

[41] BPI_BUS1 AH5 AE19

BPI_BUS1 AUXIN2 AUX_IN2_NTC [8]
AF7
CDM3P5A AC6 AF18
[51] BPI_BUS0 BPI_BUS0 AUXIN1 AUX_IN1_NTC [46]
AE7
B CDM5P5A AF19 B
AUXIN0 AUX_IN0_NTC [8]
C305
TEST MODE
C304
1.0UF;20%;6.3V;0201
L24 1.0UF;20%;6.3V;0201
TESTMODE

REF POWER C306 C301 C302

NC
AJ18 REFP1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
REFP
A1
A27 NC1 C303
AJ1 NC2
NC3 0.1uF;20%;6.3V;0201
AJ27
NC4

Note: 12-4
Schematic design notice of "12_BB_1" page.
Note 12-1: "PWRAP_SPI0_CSN" and "AUD_DAT_MOSI0" are bootstrap pins to select which interface will be the JTAG pin out. Note 12-3: To shunt a 1uF capacitor in the AUXIN ADC input to prevent noise coupling. It should be placed
PWRAP_SPI0_CSN AUD_DAT_MOSI0 AP_JTAG IO_JTAG as close to BB as possible. Connect the unused AUX ADC input to GND.
HI LO N/A N/A
Note 12-4: The de-coupling cap. for REFP (AJ18 ball) have to be placed as close to BB as possible.
HI HI SPI_CSB/SPI_CLK/ N/A
SPI_MO/SPI_MI/EINT8
Note 12-5: AUD_SYNC_MISO and AUD_CLK_MISO are DDR type feature in bootstrap
LO SPI_CSB/SPI_CLK/
LO DPI_11/DPI_HSYNC/DPI_VSYNC/DPI_DE/
SPI_MO/SPI_MI/EINT8 DPI_CK/DPI_D8/DPI_D9 AUD_SYNC_MISO AUD_CLK_MISO DDR
LO LO LPDDR4X
A
MSDC1_CLK/CMD/ N/A A

LO HI DAT0/DAT1/DAT2 LO HI LPDDR4X(Ext x 2 EN)

HI LO LPDDR3
Note 12-2: "AUD_DAT_MISO0" is bootstrap pin to enable serial JTAG output over USB2.0 interface or not.
HI HI LPDDR4X(Ext x 1 EN)
When "AUD_DAT_MISO0" is pulled to high in system start up and then USB2.0 interface will be switched into serial JTAG mode.
Title REV: V10
"AUD_DAT_MISO1" is bootstrap pin to select system booting up from eMMC or UFS device. 03_BB_1_RF&SIM_IF
AUD_DAT_MISO1 Booting device DOCUMENT NO.: Design Name Size C

LO eMMC
DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI
HI UFS

5 4 3 2 1
Date: Friday, June 14, 2019 Sheet 5 of 65
 5 4 3 2 1

U101C U101D
MT6771-DDR4 MT6771-DDR4

MT6771-SBS MT6771-SBS
CSI DSI USB 2.0 MSDCs
[27] RDP2 P4 U25 DSI0_CKP [26] [22,33,34] USB_DP R421 0;0.5A;0201 G26 D25 MSDC0_RSTB [20]
P3 CSI0A_L0P_T0A DSI0_CKP U24 USB_DP MSDC0_RSTB
[27] RDN2 CSI0A_L0N_T0B DSI0_CKN DSI0_CKN [26]
[22,33,34] USB_DM R422 0;0.5A;0201 F26 C27 MSDC0_CMD [20]
USB_DM MSDC0_CMD
[27] RDP0 R2 T25 DSI0_D3P [26] D24 MSDC0_CLK [20]
R1 CSI0A_L1P_T0C DSI0_D3P T24 AF23 MSDC0_CLK E25
[27] RDN0 CSI0A_L1N_T1A DSI0_D3N DSI0_D3N [26] [34] USB_ID IDDIG MSDC0_DSL MSDC0_DSL [20]
[21] CODEC_IRQ_N AF26 D26
DRVBUS MSDC0_DAT7 MSDC0_DAT7 [20]
D
[27] RCP P5 V25 DSI0_D2P [26] G23 MSDC0_DAT6 [20]
D
N5 CSI0A_L2P_T1B DSI0_D2P V24 MSDC0_DAT6 C25
[27] RCN CSI0A_L2N_T1C DSI0_D2N DSI0_D2N [26] MSDC0_DAT5 MSDC0_DAT5 [20]
C26 MSDC0_DAT4 [20]
MSDC0_DAT4 E24
MSDC0_DAT3 MSDC0_DAT3 [20]
[27] RDP1 R3 U26 DSI0_D1P [26] A26 MSDC0_DAT2 [20]
R4 CSI0B_L0P_T0A DSI0_D1P T26 MSDC0_DAT2 B27
[27] RDN1 CSI0B_L0N_T0B DSI0_D1N DSI0_D1N [26] MSDC0_DAT1 MSDC0_DAT1 [20]
USB 3.0
B26 MSDC0_DAT0 [20]
MSDC0_DAT0
[27] RDP3 T2 T27 DSI0_D0P [26] J25
T1 CSI0B_L1P_T0C DSI0_D0P R27 SSUSB_TXP AC24
[27] RDN3 CSI0B_L1N_T1A DSI0_D0N DSI0_D0N [26] MSDC1_CLK MSDC1_CLK [31]
J24
SSUSB_TXN AD26
MSDC1_CMD MSDC1_CMD [31]
Note: 13-1 T3 AH23 DISP_PWM [26]
T4 CSI0B_L2P_T1B DISP_PWM AD27
CSI0B_L2N_T1C MSDC1_DAT3 MSDC1_DAT3 [31]
AG26 DSI_TE [26] H27 AC23 MSDC1_DAT2 [31]
DSI_TE SSUSB_RXP MSDC1_DAT2 AE26
MSDC1_DAT1 MSDC1_DAT1 [31]
[27] CAM_CLK0 R420 0;1A;0402 AA4 AH27 LCM_RST [26] J27 AD24 MSDC1_DAT0 [31]
CAM_CLK0 LCM_RST SSUSB_RXN MSDC1_DAT0
AA3
C421 CAM_RST0

KEYPAD WBG_IQ
[27] CAM_PDN0 W6
CAM_PDN0
NF_18pF;5%;50V;0201
AH1 B1 WF_IP [56]
[33] HW_ID1 KPROW1 WF_IP
DPI
Note: 13-1 M2 C1 WF_IN [56]
M1 CSI1A_L0P AA5 WF_IN
CSI1A_L0N AC25 [29] FP_1V8_EN KPROW0 D1
DPI_CK HAC_EN [23] WF_QP WF_QP [56]
D2 WF_QN [56]
M3 AC26 AE3 WF_QN
[27] RDP0_A CSI1A_L1P DPI_DE AMP1_IRQN [23] [26] SPI2_MI KPCOL1
[27] RDN0_A M4
CSI1A_L1N AA24 AC4 F2
DPI_VSYNC EINT_SD [31] [32] KPCOL0 KPCOL0 BT_IP BT_IP [56]
F1 BT_IN [56]
N1 Y23 BT_IN
[27] RCP_A CSI1A_L2P DPI_HSYNC KPCOL2 [32]
[27] RCN_A N2 G1 BT_QP [56]
CSI1A_L2N BT_QP
UART
G2 BT_QN [56]
AA23 BT_QN
DPI_D11 SPI3_CODEC_CLK [21]
N3 [33] UTXD0 AD1
N4 CSI1B_L0P AA26 UTXD0 J2
CSI1B_L0N DPI_D10 SPI3_CODEC_MOSI [21] GPS_I GPS_I [56]
[33] URXD0 AD2 J1
URXD0 GPS_Q GPS_Q [56]
U401 Y26 SPI3_CODEC_CSN [21]
DPI_D9
I2C CONN_IF
Note: 13-1 P2 [4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63] VIO18_PMU R401 NF_2.2K;5%;0201
CSI2_LANE3_P_F [27] A3 A2 P1 CSI1B_L1P AB24 R402 NF_2.2K;5%;0201
CLKAP CLKP RDP3_B [6] CSI1B_L1N DPI_D8 SPI3_CODEC_MISO [21]
CSI2_LANE3_N_F [27] B3 A1 RDN3_B [6] AB6 J4
CLKAN CLKN [26] SCL0 SCL0 CONN_TOP_CLK CONN_TOP_CLK [56]
Y24 SPI4_PA_CLK [23] [26] SDA0 AC5 J5 CONN_TOP_DATA [56]
CSI2_CLK_P_F [27] A4 B2 R417 0;1A;0402 AC2 DPI_D7 SDA0 CONN_TOP_DATA H3
DA1P D1P RCP_B [6] [27] CAM_CLK1 CAM_CLK1 CONN_HRST_B CONN_HRST_B [56]
CSI2_CLK_N_F [27] B4 B1 RCN_B [6] W24 R403 NF_2.2K;5%;0201
DA1N D1N DPI_D6 [4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63]
SPI4_PA_MOSI [23] VIO18_PMU
AA2 R404 NF_2.2K;5%;0201
CSI2_LANE0_P_F [27] A5 C2 C422 CAM_RST1 AB23 AE4 H4
DA2P D2P RDP0_B [6] DPI_D5 SPI4_PA_CSN [23] [30] SCL1 SCL1 CONN_BT_CLK CONN_BT_CLK [56]
CSI2_LANE0_N_F [27] A6 C1 RDN0_B [6] Y5 AF4 H5
DA2N D2N CAM_PDN1 [30] SDA1 SDA1 CONN_BT_DATA CONN_BT_DATA [56]
NF_18pF;5%;50V;0201 AB26 SPI4_PA_MISO [23]
CSI2_LANE1_P_F [27] B5 D2 DPI_D4 R405 NF_2.2K;5%;0201
DA3P D3P RDP1_B [6] [6,10,27] VCAMIO_PMU
C CSI2_LANE1_N_F [27] B6 D1 RDN1_B [6] [6] RDP2_B U2 W26 R406 NF_2.2K;5%;0201 C
DA3N D3N U1 CSI2A_L0P DPI_D3 CODEC_GPIO14 [21] AB2 K6
[6] RDN2_B CSI2A_L0N [27] SCL2 SCL2 CONN_WB_PTA CONN_WB_PTA [56]
CSI2_LANE2_P_F [27] C5 E2 RDP2_B [6] W25 AB1 H6
DA4P D4P DPI_D2 TOF_XSHUT [28] [27] SDA2 SDA2 CONN_WF_CTRL2 CONN_WF_CTRL2 [56]
CSI2_LANE2_N_F [27] C6 E1 RDN2_B [6] J7
DA4N D4N CONN_WF_CTRL1 CONN_WF_CTRL1 [56]
[6] RDP0_B T5 AA25 [4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63] VIO18_PMU R407 NF_2.2K;5%;0201 J6 CONN_WF_CTRL0 [56]
R5 CSI2A_L1P DPI_D1 R408 NF_2.2K;5%;0201 CONN_WF_CTRL0
[6] RDN0_B CSI2A_L1N W23 TOF_INT [28] [23,63] SCL3 AF22 R22 CAM_SWITCH_SEL [6]
1 DPI_D0 AG22 SCL3 ANT_SEL2 T23
TP402 [23,63] SDA3 SDA3 ANT_SEL1 CODEC_VDD_EN [21]
CSI2_LANE3_P_R [27] D6 U4 P22
CLKBP [6] RCP_B CSI2A_L2P ANT_SEL0 GPIO_GPS_LNA_EN [58]
CSI2_LANE3_N_R [27] D5 U3 R410 NF_2.2K;5%;0201
CLKBN [6] RCN_B CSI2A_L2N [6,10,27] VCAMIO_PMU
R409 NF_2.2K;5%;0201
CSI2_CLK_P_R [27] E6 F1 Y2 H8
DB1P /OE [27] SCL4 SCL4 XIN_WBG XIN_WBG [56]
CSI2_CLK_N_R [27] E5 F2 CAM_SWITCH_SEL [6] V2 W2
DB1N SEL [6] RDP1_B CSI2B_L0P [27] SDA4 SDA4
C3 V1
NC [6] RDN1_B CSI2B_L0N
AUD_IF
CSI2_LANE0_P_R [27] F6 C4 R415 0;0.5A;0201 VCAMA_PMU [10,27] R411 NF_2.2K;5%;0201
DP2P VCC [4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63] VIO18_PMU
CSI2_LANE0_N_R [27] F5 D3 R412 NF_2.2K;5%;0201
DB2N GND
PWM
D4 V4 AG23 AH24
NC1 [6] RDP3_B CSI2B_L1P I2S1_BCK I2S3_CODEC_BCLK [21] [15,26,28,34] SCL5 SCL5
CSI2_LANE1_P_R [27] E4 R416 NF_0;0.5A;0201 RCAM_AVDD [27] V3 AH25
DB3P [6] RDN3_B CSI2B_L1N [15,26,28,34] SDA5 SDA5
CSI2_LANE1_N_R [27] F4 C420 AD21 AA6
DB3N C419 I2S1_LRCK I2S3_CODEC_LRCLK [21] PWM_A
CSI2_LANE2_P_R [27] E3 R418 0;1A;0402 K4 AG21
DB4P 1.0UF;20%;6.3V;0201 33pf;30%;50V;0201 [27] CAM_CLK2 CAM_CLK2 I2S1_DO I2S3_CODEC_SDO [21]
CSI2_LANE2_N_R [27] F3 N26
DB4N [29] EINT_FP_N SCL6
[21] CLKM0 L5 AG19 I2S0_CODEC_SDI [21] P26
C423 CAM_PDN2 I2S2_DI [34] CC_INT SDA6
BCT644EWX-TR
PERI. EN GPIO
[27] CAM_RST2 K5
CAM_RST2 AD20
NF_18pF;5%;50V;0201 I2S1_MCK CODEC_RST_N [21]
[28] FLASH_EN AA7 Y4
AD19 PERIPHERAL_EN14 EINT10 CODEC_GPIO11 [21]
[26] GPIO_LCM_LED_EN PERIPHERAL_EN13
AD22 W4 SAR_INT [63]
[33] HW_ID2 PERIPHERAL_EN12 EINT9
SPI [29] FP_3V3_EN Y6
Y7 PERIPHERAL_EN11 AD4
[29] GPIO_FP_RST_N PERIPHERAL_EN10 EINT8 JTRST [33]
[27] CAM_CLK3 R419 0;1A;0402 L4 AG3 SPI0_CSB [29]
CAM_CLK3 SPI_CSB V22 AE1
[27] REAR_CAM_AVDD_EN PERIPHERAL_EN9 EINT7 CODEC_GPIO12 [21]
[27] CAM_PDN3 L3 AF3 SPI0_CLK [29]
C424 CAM_PDN3 SPI_CLK K22 AE2
[25] EAR_EINT PERIPHERAL_EN8 EINT6 EINT_CTP [26]
[27] CAM_RST3 K3 AH2 SPI0_MO [29]
CAM_RST3 SPI_MO T22 AF2
NF_18pF;5%;50V;0201 [28] LED_EN PERIPHERAL_EN7 EINT5 EINT_ALPS [30]
AJ2 SPI0_MI [29]
SPI_MI N22 AC3
[27] CAM_DVDD_1P2_EN PERIPHERAL_EN6 EINT4 ACC_GYRO_INT1 [30]
AD25 AG1 CODEC_GPIO13 [21]
[30] PSENSOR_3V3_EN PERIPHERAL_EN5 EINT3
AB25 SCP_SPI_CSB [30]
SPI1_CSB Y25 AG2
[23] VIB_RST_N PERIPHERAL_EN4 EINT2 SPI2_CK [26]
AA22 SCP_SPI_CLK [30]
SPI1_CLK L22 AB4
[23] SPK_AMP1_RST_N PERIPHERAL_EN3 EINT1 SPI2_MO [26]
Y22 SCP_SPI_MO [30]
SPI1_MO M22 AB5
[15] EINT_CHG_CE PERIPHERAL_EN2 EINT0 SPI2_CS [26]
W22 SCP_SPI_MI [30]
SPI1_MI L25
[26] ENN PERIPHERAL_EN1
B
[26] ENP R25 B
PERIPHERAL_EN0

Schematic design notice of "13_BB_2" page.

Note 13-1: CSI ports which are no use could be connected to GND or set in NC.
For detail information, please refer to MT6771 Design Notice

A A

Title REV: V10

04_BB_2_MIPI&GPIO
DOCUMENT NO.: Design Name Size D

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 6 of 65

5 4 3 2 1
 5 4 3 2 1

U101G
MT6771-DDR4

MT6771-SBS
EMI_IF EMI_IF
EMI1_DQ15 D14 C16 EMI1_CS1
[20] EMI1_DQ15 EMI1_DQ15 EMI1_CS1 EMI1_CS1 [20]
D EMI1_DQ14 B14 E17 EMI1_CS0 D
[20] EMI1_DQ14 EMI1_DQ14 EMI1_CS0 EMI1_CS0 [20]
EMI1_DQ13 A15
[20] EMI1_DQ13 EMI1_DQ13 A7 EMI0_CS1
EMI0_CS1 EMI0_CS1 [20]
EMI1_DQ12 C12
[20] EMI1_DQ12 EMI1_DQ12 D8 EMI0_CS0
EMI0_CS0 EMI0_CS0 [20]
EMI1_DQ11 D15
[20] EMI1_DQ11 EMI1_DQ11
EMI1_DQ10 A13
[20] EMI1_DQ10 EMI1_DQ10
EMI1_DQ9 C14 E18 EMI1_CKE1
[20] EMI1_DQ9 EMI1_DQ9 EMI1_CKE1 EMI1_CKE1 [20]
EMI1_DQ8 C13 D18 EMI1_CKE0
[20] EMI1_DQ8 EMI1_DQ8 EMI1_CKE0 EMI1_CKE0 [20]
EMI1_DQ7 C21
[20] EMI1_DQ7 EMI1_DQ7 D7 EMI0_CKE1
EMI0_CKE1 EMI0_CKE1 [20]
EMI1_DQ6 A19
[20] EMI1_DQ6 EMI1_DQ6 E8 EMI0_CKE0
EMI0_CKE0 EMI0_CKE0 [20]
EMI1_DQ5 B19
[20] EMI1_DQ5 EMI1_DQ5
EMI1_DQ4 C20
[20] EMI1_DQ4 EMI1_DQ4
EMI1_DQ3 E19 B15 EMI1_DMI1
[20] EMI1_DQ3 EMI1_DQ3 EMI1_DMI1 EMI1_DMI1 [20]
EMI1_DQ2 D20 B18 EMI1_DMI0
[20] EMI1_DQ2 EMI1_DQ2 EMI1_DMI0 EMI1_DMI0 [20]
EMI1_DQ1 E20
[20] EMI1_DQ1 EMI1_DQ1 C8 EMI0_DMI1
EMI0_DMI1 EMI0_DMI1 [20]
EMI1_DQ0 F20
[20] EMI1_DQ0 EMI1_DQ0 B4 EMI0_DMI0
EMI0_DMI0 EMI0_DMI0 [20]

EMI1_CA5 D19 F13 EMI1_DQS1_C

[20] EMI1_CA5 EMI1_CA5 EMI1_DQS1_C EMI1_DQS1_C [20]
EMI1_CA4 C17 E13 EMI1_DQS1_T
[20] EMI1_CA4 EMI1_CA4 EMI1_DQS1_T EMI1_DQS1_T [20]
EMI1_CA3 A17 E21 EMI1_DQS0_C
[20] EMI1_CA3 EMI1_CA3 EMI1_DQS0_C EMI1_DQS0_C [20]
C EMI1_CA2 EMI1_DQS0_T C
B17 F21 EMI1_DQS0_T [20]
[20] EMI1_CA2 EMI1_CA2 EMI1_DQS0_T
EMI1_CA1 C15
[20] EMI1_CA1 EMI1_CA1
EMI1_CA0 D17 E12 EMI0_DQS1_C
[20] EMI1_CA0 EMI1_CA0 EMI0_DQS1_C EMI0_DQS1_C [20]
F12 EMI0_DQS1_T
EMI0_DQS1_T EMI0_DQS1_T [20]
EMI0_DQ15 D11
[20] EMI0_DQ15 EMI0_DQ15 C4 EMI0_DQS0_C
EMI0_DQS0_C EMI0_DQS0_C [20]
EMI0_DQ14 C9
[20] EMI0_DQ14 EMI0_DQ14 D4 EMI0_DQS0_T
EMI0_DQS0_T EMI0_DQS0_T [20]
EMI0_DQ13 D9
[20] EMI0_DQ13 EMI0_DQ13
EMI0_DQ12 A11
[20] EMI0_DQ12 EMI0_DQ12
EMI0_DQ11 A9 F16 EMI1_CK_C
[20] EMI0_DQ11 EMI0_DQ11 EMI1_CK_C EMI1_CK_C [20]
EMI0_DQ10 B10 E16 EMI1_CK_T
[20] EMI0_DQ10 EMI0_DQ10 EMI1_CK_T EMI1_CK_T [20]
EMI0_DQ9 E11
[20] EMI0_DQ9 EMI0_DQ9 E10 EMI0_CK_C
EMI0_CK_C EMI0_CK_C [20]
EMI0_DQ8 B11
[20] EMI0_DQ8 EMI0_DQ8 D10 EMI0_CK_T
EMI0_CK_T EMI0_CK_T [20]
EMI0_DQ7 A3
[20] EMI0_DQ7 EMI0_DQ7
EMI0_DQ6 A5
[20] EMI0_DQ6 EMI0_DQ6
EMI0_DQ5 C5
[20] EMI0_DQ5 EMI0_DQ5 D22 EMI_RESET_N
EMI_RESET_N EMI_RESET_N [20]
EMI0_DQ4 B3
[20] EMI0_DQ4 EMI0_DQ4
EMI0_DQ3 D6
[20] EMI0_DQ3 EMI0_DQ3
EMI0_DQ2 E6
[20] EMI0_DQ2 EMI0_DQ2
EMI0_DQ1 D5
[20] EMI0_DQ1 EMI0_DQ1
B EMI0_DQ0 E5 B
[20] EMI0_DQ0 EMI0_DQ0

EMI0_CA5 E7 UFS_IF
[20] EMI0_CA5 EMI0_CA5 F23
EMI0_CA4 B7 UFS_CKIN_26M
[20] EMI0_CA4 EMI0_CA4
EMI0_CA3 B6
[20] EMI0_CA3 EMI0_CA3 B24
EMI0_CA2 B5 UFS_TX0_P A24
[20] EMI0_CA2 EMI0_CA2 UFS_TX0_N
EMI0_CA1 C7
[20] EMI0_CA1 EMI0_CA1 A22
EMI0_CA0 E9 UFS_RX0_RXP B22
[20] EMI0_CA0 EMI0_CA0 UFS_RX0_RXN

E22
UFS_RST_N

R501 EMI_EXTR
2 1 EMI_EXTR A2
EMI_EXTR
60.4;1%;0201

Note: 14-1

A A

Title REV: V10

10_BB_ POWER_PDN
Schematic design notice of "14_BB_3" page.
DOCUMENT NO.: Design Name Size C

The resistor of EMI_EXTR for DRAM has to be placed near to BB as close as possible DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI
Note 14-1: R501, please select 60.4 ohm 1% resistor

Date: Friday, June 14, 2019 Sheet 7 of 65

5 4 3 2 1
 5 4 3 2 1

D D

[4,5,6,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63] VIO18_PMU
FOR BOADR ID 2
R601 R602 R605
390K;1%;0201 390K;1%;0201 NF_390K;1%;0201
R603
NF_10K;5%;0201
BAT_ID [5,22]

2
[5] HW_ID RT602 R604
RT601 100K;1%;0402 0;0.5A;0201
100K;1%;0402
RT603

1
BOADR ID 1 0;0.5A;0201

1. IF used for battery ID,R604 NC,R605=390K

Thermistor to sense charger Thermistor to sense AP
2. IF unused ,R604=0 R,R605 NC
C temperature temperature C

1. RT602must keep a distance about 6~8 mm away from AP and far from
other heat sources 10 mm at least.
AUX_IN2_NTC 2. The distance is the shortest distance from package edge to edge.
[5] AUX_IN2_NTC

AUX_IN0_NTC
[5] AUX_IN0_NTC

B B

A A

Title 06_BB_AUXADC_Thermal REV: V10

DOCUMENT NO.: Design Name Size C

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 8 of 65

5 4 3 2 1
 5 4 3 2 1

U701A
U / MT6358W / A_1

MT6358
R701 VBUCK CTRL
VSYS_SMPS E2
[10,11,15,17,21,23,26,27,28,29,30,34] VSYS VSYS_SMPS

1;5%;0201 C702
SG701
1.0UF;20%;6.3V;0201
L701：
D
1 2 GND_SMPS E1
GND_SMPS
MT6771L 饱和电流5.3A D
MT6771T 饱和电流5.7A
SINGLE-GND-L4
L701
VPROC11 IN VPROC11 L close to chip 0.8V 5000mA
A6 A7 VPROC11 DVDD_PROC_B [3]
B6 VSYS_VPROC11_1 VPROC11_1 B7
VSYS_VPROC11_2 VPROC11_2 0.47uH;20%;2016
C701 differential and shielding
SG702
10uF;20%;6.3V;0402 A8 D6 4mil
GND_VPROC11-1 VPROC11_FB DVDD_PROC_B_PMIC_FB [3] C712
1 2 GND_VPROC11 B8
GND_VPROC11_2 D7 4mil NF_10uF;20%;6.3V;0402
GND_VPROC11_FB DVDD_PROC_B_PMIC_GND [3]
SINGLE-GND-L4

L702 803401000931
VPROC12 IN VPROC12 L close to chip
A10 B9 VPROC12 0.8V 5000mA DVDD_PROC_L [3]
B10 VSYS_VPROC12_1 VPROC12_1 A9
VSYS_VPROC12_2 VPROC12_2 0.47UH;20%;2016
C703 differential and shielding
SG703
10uF;20%;6.3V;0402 D8 E9 4mil
DVDD_PROC_L_PMIC_FB [3]
1 2 GND_VPROC12 D9 GND_VPROC12_1 VPROC12_FB
GND_VPROC12_2 D10 4mil
GND_VPROC12_FB DVDD_PROC_L_PMIC_GND [3]
SINGLE-GND-L4

VCORE IN VCORE L703

A15 A14 VCORE
B15 VSYS_VCORE_1 VCORE_1 B14
L close to chip 0.8V 5000mA DVDD_CORE [3,4]
VSYS_VCORE_2 VCORE_2
C704 0.47uH;20%;2016
SG704
10uF;20%;6.3V;0402 B13
1 2 GND_VCORE A13 GND_VCORE_1 differential and shielding
GND_VCORE_2 C16 4mil
VCORE_FB DVDD_CORE_PMIC_FB [3]
SINGLE-GND-L4
B16 4mil
DVDD_CORE_PMIC_GND [3]
GND_VCORE_FB
C C

L704
VMODEM IN VMODEM L close to chip 0.8V 3250mA
F14 F15 VMODEM DVDD_MODEM [3]
VSYS_VMODEM VMODEM_1 F16 1.0UH;20%;2016
VMODEM_2
C705 differential and shielding
SG705
4.7uF;20%;6.3V;0402 D15 4mil
DVDD_MODEM_PMIC_FB [3]
1 2 GND_VMODEM G15 VMODEM_FB
G16 GND_VMODEM_1 E14 4mil
GND_VMODEM_2 GND_VMODEM_FB DVDD_MODEM_PMIC_GND [3]
SINGLE-GND-L4

L705
VPA IN VPA L close to chip
A5 A4 VPA 0.5V 1000mA VPA_PMU [46]
VSYS_VPA VPA 1.0UH;20%;2016

C706 D5 C707
SG706 VPA_FB
10uF;20%;6.3V;0402 B4 2.2uF;20%;6.3V;0402
1 2 GND_VPA GND_VPA
Note: 20-1
SINGLE-GND-L4
close to VPA Inductor
VS1 IN VS1 PMIC feedback cap.
L706 Total cap. = 1uF+6.2uF
B1 A2 VS1
C1 VSYS_VS1_1 VS1_1 B2
L close to chip 2V 2000mA VS1_PMU [9,10,17]
VSYS_VS1_2 VS1_2
C708 1.0uH;20%;2016
SG707
4.7uF;20%;6.3V;0402 A3
1 2 GND_VS1 B3 GND_VS1_1
GND_VS1_2 E7
B VS1_FB VS1_PMU VS1
[9,10,17] sense to Cap B
SINGLE-GND-L4

VS2 IN VS2
L707
L15 VS2
K15 VS2_1 L16
L close to chip 1.35V 2000mA VS2_PMU [9,10,21,27]
K16 VSYS_VS2_1 VS2_2
VSYS_VS2_2 1.0uH;20%;2016
C709
SG708
4.7uF;20%;6.3V;0402 L14
1 2 GND_VS2 GND_VS2 D16
VS2_FB VS2_PMU VS2 sense
[9,10,21,27] to Cap
SINGLE-GND-L4
VGPU IN VGPU L708
B12 VGPU L close to chip
VGPU_1 A12 0.8V 5000mA DVDD_GPU [3]
A11 VGPU_2
B11 VSYS_VGPU_1 0.47UH;20%;2016
VSYS_VGPU_2
C710 differential and shielding
SG709
10uF;20%;6.3V;0402 D12 D14 4mil
DVDD_GPU_PMIC_FB [3]
1 2 GND_VGPU D13 GND_VGPU_1 VGPU_FB
GND_VGPU_2 C15 4mil
GND_VGPU_FB DVDD_GPU_PMIC_GND [3]
SINGLE-GND-L4
L709
VDRAM1 VDRAM1 L close to chip 1.125V/1.225V 2000mA
J15 VDRAM1 EMI_VDD2 [3,10,19,20]
J16 VDRAM1
VSYS_VDRAM1 1.0uH;20%;2016

C713
C711 H15 differential and shielding
SG710 GND_VDRAM1 NF_10uF;20%;6.3V;0402
A 4.7uF;20%;6.3V;0402 D11 4mil
EMI_VDD2_FB [19] A
1 2 GND_VDRAM1 VDRAM1_FB
E12 4mil
EMI_VDD2_GND [19]
GND_VDRAM1_FB
SINGLE-GND-L4
All Buck Input Cap close to chip Title
07_POWER_MT6358-Buck REV: V10

DOCUMENT NO.: Design Name Size C

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Schematic design notice of "20_POWER_MT6358-Buck" page.

Date: Friday, June 14, 2019 Sheet 9 of 65
Note 20-1: Please select C707 with 0402 size
5 4 3 2 1
 5 4 3 2 1

1. "Typical Cap" defined in design notice is the minimum cap. to LDO Cout.
U701B
2. NC cap can move to application, if (PCB L<20nH, PCB R<0.2 ohm)
U / MT6358W / A_1 => value and placement of Cap, please refer design notice

MT6358 Close to PMIC

LDO IN LDO
R7 2.8V 50mA
VFE28 VFE28_PMU [34,46]
P6 2.24V 50mA
VXO22 VXO22_PMU
P7
,11,15,17,21,23,26,27,28,29,30,34] VSYS VSYS_LDO1 2.8V 50mA
R6
D VCN28 VCN28_PMU [56,58] D
,11,15,17,21,23,26,27,28,29,30,34] VSYS P9

NF_1.0UF;20%;6.3V;0201
VSYS_LDO2

NF_1.0UF;20%;6.3V;0201
M10 1.8/2.5/2.7/2.8/2.9/3.0V 200mA
VCAMA1 VCAMA_PMU [6,27]
,11,15,17,21,23,26,27,28,29,30,34] VSYS N11
VSYS_LDO3 M6 1.8V 50mA
VAUX18 VAUX18_PMU [13]
R5 2.8V 50mA
VAUD28 VAUD28_PMU [12]
C801 C802 C803
M9 2.8V 50mA
2.2uF;20%;6.3V;0201 2.2uF;20%;6.3V;0201 2.2uF;20%;6.3V;0201 ALDO VBIF28 VBIF28_PMU [11]
N10 1.8/2.5/2.7/2.8/2.9/3.0V 200mA
VCAMA2 VCAMA2_PMU [27]
C837 C838
C804 C805 C806 C807 C808 C809
1.0UF;20%;6.3V;0201 2.2uF;20%;6.3V;0402 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
[9,17] VS1_PMU E4 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
VS1_LDO1 N12 3.3/3.4/3.5/3.6V 800mA
VCN33 VCN33_PMU [56]
C846
P8 2.8/3.0V 400mA
10uF;20%;6.3V;0402 VLDO28 VLDO28_PMU [27]
C810 C845 C812
22uF;20%;6.3V;0603 10uF;20%;6.3V;0402 4.7uF;20%;6.3V;0402 N9 2.8V 200mA
VIO28 VIO28_PMU [28,30,63]
R9 1.86/2.9/3.0/3.3V 200mA
VMC VMC_PMU [4]
R10 2.9/3.0/3.3V 800mA
VMCH VMCH_PMU [31]
[3,9,19,20] EMI_VDD2 R15
VS2_LDO1 R11 2.9/3.0/3.3V 800mA

NF_1.0UF;20%;6.3V;0201

NF_1.0UF;20%;6.3V;0201

NF_1.0UF;20%;6.3V;0201
VEMC VEMC_PMU [19]
C813 N7 1.7/1.8/1.86/2.76/3.0/3.1V 200mA
VSIM1 VSIM1_PMU [4,31]
2.2uF;20%;6.3V;0402
P10 1.7/1.8/1.86/2.76/3.0/3.1V 200mA
VSIM2 VSIM2_PMU [4,31]
P11 1.2/1.3/1.5/1.8/2.0/2.8/3.0/3.3V 200mA
VIBR
N8 3.07V 200mA
VUSB VUSB_PMU [4]
N14
[9,21,27] VS2_PMU VS2_LDO2 DLDO
P13 C844 C815 C816 C817 C818 C819 C820 C839 C840 C841
VS2_LDO3 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
C C
C821 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
22uF;20%;6.3V;0603

F5 1.81V 450mA
VRF18 VRF18_PMU [37]
E3 1.71/1.8V/1.84V 300mA
VEFUSE VEFUSE_PMU [4]
All LDO Input Cap close to chip M14
VS2_LDO4 F6 1.8V 300mA
VCN18 VCN18_PMU [56]

NF_1.0UF;20%;6.3V;0201
VS2_LDO4
Connect to VS2 If VCAMD < 1.2V, VCAMD = 1.2V E6 1.8V 300mA
Connect to VS1 If VCAMD > 1.2V VCAMIO VCAMIO_PMU [6,27]
F3 1.8V 700mA
VIO18 VIO18_PMU [4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,4
SH801 SINGLE-GND-L8
F7 C822 C823 C824 C825 C842 1 2
D_GND1 AVDD18_SOC [4]
F8 4.7uF;20%;6.3V;0402 1.0UF;20%;6.3V;0201
F9 D_GND2 1.0UF;20%;6.3V;0201 4.7uF;20%;6.3V;0402
G7 D_GND3 SLDO1
G8 D_GND4
G9 D_GND5 P16
Note: 21-1
H7 D_GND6 VRF12_S
H8 D_GND7 N15 1.2V 800mA
D_GND8 VRF12 VRF12_PMU [37]
H9
D_GND9 N16 1.2V 300mA
VA12 VA12_PMU [4]
P12 0.6~1.2(0.9)V 600mA
VSRAM_PROC11 DVDD_SRAM_PROC_B [3]
P14 0.55~1.2(0.9)V 600mA
VSRAM_OTHERS DVDD_SRAM_CORE [3]
R14 0.65~1.2(0.9)V 600mA
VREF
VREF VSRAM_GPU DVDD_VSRAM_GPU_PMU [3]
Close to IC
M12
C826 VREF R13 0.6~1.2(0.9)V 600mA
B SG801 VSRAM_PROC12 DVDD_SRAM_PROC_L [3] B
0.1uF;20%;6.3V;0201
1 2 GND_VREF N13 P15 0.6/1.8V 600/100mA
GND_VREF VDRAM2 EMI_VDDQ [3,19,20]
M15 0.9/1.0/1.05/1.1/1.2/1.3/1.5/1.8V 600mA
SINGLE-GND-L4 VCAMD VCAMD_PMU [27]

DIG Power SLDO2

33,34,37,40,41,46,49,63 VIO18_PMU L9
DVDD18_IO C827 C843 C828 C829 C830 C831 C832 C833
1.8V 10mA DVDD18_DIG J8 1.0UF;20%;6.3V;0201 2.2uF;20%;6.3V;0402 2.2uF;20%;6.3V;0402 2.2uF;20%;6.3V;0402
DVDD18_DIG DVDD18_DIG 22uF;20%;6.3V;0603 2.2uF;20%;6.3V;0402 2.2uF;20%;6.3V;0402 4.7uF;20%;6.3V;0402

L8
DVSS18_IO
C834 C835 C836 Note: 21-2
1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 0.1uF;20%;6.3V;0201

SG802
1 2 DVSS18_IO

SINGLE-GND-L4

A A
Schematic design notice of "21_POWER_MT6358-LDO" page.

Note 21-1: Please set SH801 close to C825, making star connection between VIO18_PMU and AVDD18_SOC near to LDO cap. C825 Title
08_POWER_MT6358-LDO REV: V10

Please also refer to MT6358 design notice for further detail design information DOCUMENT NO.: Design Name Size C

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Note 21-2: If these power trace can meet LDO layout constraint, these CAP can be NC or removed.
Please refer to MT6358 design notice.
Date: Friday, June 14, 2019 Sheet 10 of 65

5 4 3 2 1
 5 4 3 2 1

D U701C D

MT6358
Control I/F Control I/F
[5] SYSRSTB D4 D2 PWRKEY D901 2 1 LRB521CS-30T5G PWRKEY_SW [15,32]
RESETB PWRKEY short to GND
[5] WATCHDOG F12 G13 if disable
WDTRSTB_IN HOMEKEY
J13 HOMEKEY
SD_CARD_DET_N_PMU
SD_CARD_DET_N SD_CARD_DET_N_PMU [31]

PMIC SPI TEST SD Detect pin for VMCH power off

[5] PWRAP_SPI0_CSN F13 L6

SPI_CSN FSOURCE

[5] PWRAP_SPI0_CK F11

SPI_CLK E8
G11 PMU_TESTMODE
[5] PWRAP_SPI0_MO SPI_MOSI
G10
[5] PWRAP_SPI0_MI SPI_MISO

Note: 22-1
PMIC CFG EXT PMIC EN
R901
UVLO_VTH M13 D3
UVLO_VTH EXT_PMIC_EN1
A1
200K;1%;0201 A16 NC1 E5
R1 NC2 EXT_PMIC_EN2
R16 NC3
NC4
C C
U / MT6358W / A_1

U701E

Cap close to chip

MT6358
Charger I/F Gauge
differential
[9,10,15,17,21,23,26,27,28,29,30,34] VSYS M11 N6
VSYSSNS CS_P CS_P [22]
M5 Fuel Gauge
CS_N CS_N [22]
C901
1.0UF;20%;6.3V;0201 L13 BATADC Battery Voltage BATADC [22]
BATADC
BATON L12
[10] VBIF28_PMU R902 24K;1%;0201 BATON
VCDT K12
R906 VCDT
1K;5%;0201
[22,33] BATON_CONN
Width =4mils, total Length<3000mils CHRLDO K13
CHRLDO C902
1.0UF;20%;6.3V;0201
[11,15,34] VBUS R903 330K;1%;0201

[11,15,34] VBUS R905 7.5K;1%;0201

R904 U / MT6358W / A_1
39K;1%;0201 Cap close to chip
C903
B B
1.0UF;20%;6.3V;0201
VCDT rating: 1.268V

A A

Schematic design notice of "22_POWER_MT6358-General"

Title
09_POWER_MT6358-GeneralREV: V10

Note 22-1: EXT_PMIC_EN1 : For UFS_1V8, and keep floating if it is not used DOCUMENT NO.: Design Name Size C
EXT_PMIC_EN2 : For VA09 of SSUSB/UFS, and keep floating if it is not used
DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 11 of 65

5 4 3 2 1
 5 4 3 2 1

MT6358 HW trapping for DRAM U701D R1099 0;0.5A;0201

[12] AU_MICBIAS0 MICBIAS1A [21,34]

MT6358 R1098 0;0.5A;0201

MICBIAS1B [21,24]
AUD_CLK_MISO
AUDIO IF UL POWER
R1001 20mil
VAUD28_PMU [10]
12K;5%;0201
[5] AUD_CLK_MISO H10 J3
AUD_CLK_MISO AVDD28_AUD C1001 AVSS28_AUD [25] SH1001
J11 1.0UF;20%;6.3V;0201
[5] AUD_DAT_MISO0 AUD_DAT_MISO0 20mil
H11 J5
D [5] AUD_DAT_MISO1 AUD_DAT_MISO1 AVSS28_AUD D

[5] AUD_SYNC_MISO J10 C1002 C1003

AUD_SYNC_MISO
1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
K5
AU_MICBIAS0 AU_MICBIAS0 [12]
R1002 [5] AUD_CLK_MOSI L11
AUD_CLK_MOSI L5
12K;5%;0201 AU_MICBIAS1 AU_MICBIAS1 [25]
[5] AUD_DAT_MOSI0 J9
AUD_DAT_MOSI0

[5] AUD_DAT_MOSI1 L10

AUD_DAT_MOSI1

[5] AUD_SYNC_MOSI K10

AUD_SYNC_MOSI
Close to Chip

AUDIO INPUT
For P-N pair: differential pair & GND shielding!
K1
[24] AU_VIN0_P AU_VIN0_P CHARGE PUMP
[24] AU_VIN0_N L1 VIO18_PMU [4,5,6,8,10,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63]
AU_VIN0_N 20mil
For P-N pair: differential pair & GND shielding!
H2 C1004
AVDD18_AUD SH1002
[25] AU_VIN1_P L4 2.2uF;20%;6.3V;0402
AU_VIN1_P 1 L1 2
L3 H1
[25] AU_VIN1_N AU_VIN1_N AVSS18_AUD
For P-N pair: differential pair & GND shielding! C1005
F1 4.7uF;20%;6.3V;0402
K4 AU_V18N
[24] AU_VIN2_P AU_VIN2_P
K3 1. AVSS18_AUD is connected to GND with
[24] AU_VIN2_N AU_VIN2_N
very short trace
G2
FLYP
C C
R1003 R0201_NC
R1004 R0201_NC
F2
C1006 2. AVSS18_AUD is connected to de-couple
G1001 4.7uF;20%;6.3V;0402
G1002
ACCDET
FLYN cap of AVDD18_AUD and AU_V18N with 6mil
trace respectively
[25] ACCDET K6
ACCDET
Close to Chip
[25] HP_EINT J4
HP_EINT

-AU_HPL and AU_HPR should be routed as single end signal

and be guarded by GND, up and down, left and right respectively
-The suggested layout pattern of AU_HPL/ AU_HPR/ AU_REFN AUDIO OUTPUT
is " GND AU_HPL AU_REFN AU_HPR GND"
H4
[25] AU_HPL AU_HPL
H5
[25] AU_REFN AU_REFN
G4
[25] AU_HPR AU_HPR

G5
AU_LOLP
C1007 G6
AU_LOLN
1000pF;20%;50V;0201
For P-N pair: differential pair & GND shielding!
J6
[23] AU_HSP AU_HSP

[23] AU_HSN H6
AU_HSN

B
Close to Chip B
U / MT6358W / A_1

Schematic design notice of "23_POWER_MT6358-Audio"

Note 23-1: VDRAM 2 / VDRAM1 output voltage vs. trap pin.

HW GPIO configuration Trapping Option VDRAM2 Power source

DRAM type
AUD_SYNC_MISO AUD_CLK_MISO VDRAM1 VDRAM2 (VS2_LDO1_ball)

0 0 1.125V 0.6V LP4X VDRAM1

0 1 OFF 1.8V LP4X (Ext x 2 EN) VS1
A A

1 0 1.225V OFF LP3 VDRAM1 Title REV: V10

10_POWER_MT6358-Audio
1 1 1.125V 1.8V LP4X (Ext x 1 EN) VS1 DOCUMENT NO.: Design Name Size C

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 12 of 65

5 4 3 2 1
 5 4 3 2 1

U701G
R1107
1 2
MT6358 0;1A;0402
VAUX18_PMU [10]

AUXADC
Cap close to chip
M3
AVDD18_AUXADC

C1101
1.0UF;20%;6.3V;0201
M4
AVSS18_AUXADC SG1101
D D
1 2
differential Route AVDD18_AUXADC/AUXADC_VIN with 3mil trace
C1102 width and with well GND shielding.
0.1uF;20%;6.3V;0201
AVDD18_AUXADC/AUXADC_VIN need to be shielded with
M2
AUXADC_VIN GND or AVSS18_AUXADC.
AVSS18_AUXADC 15mil trace width
AUXADC_VIN 3mil trace width
AVDD18_AUXADC 3mil trace width
differential

differential
Y1101
R1101 100K;5%;0201
4 3
SENSOR HOT2 XTAL2 3mil trace width

DCXO XTAL1 1 2
HOT1 GND

N1 XTAL1 3mil trace width AVSS18_AUXADC

XTAL1 26MHz

P1 XTAL2 3mil trace width

XTAL2

C C
R2
AVSS22_XOBUF
Please connect DCXO GND to main
P2
GND by independent L1-2 GND via.
AVSS22_XO DON'T connect it through L1 GND
N2
AVSS22_XO_ISO

U / MT6358W / A_1

U701F

MT6358
CLK CTRL DCXO CLKOUT

L7 P4 XO_SOC R1102 0;0.5A;0201

[5] SRCLKENA0 SRCLKEN_IN0 XO_SOC PMIC_CLK_BB [5]
J7
[5,37] SRCLKENA1 SRCLKEN_IN1 R3 XO_CEL R1103 0;0.5A;0201
XO_CEL PMIC_CLK_RF [37]

P3 XO_WCN R1104 0;0.5A;0201

XO_WCN PMIC_CLK_WCN [56]

N4
Sensor Hub XO_NFC

P5
H13 XO_EXT
B [5] SCP_VREQ_VAO SCP_VREQ_VAO B
C1103 C1104 C1105
C0201_NC C0201_NC C0201_NC

U / MT6358W / A_1

VRTC28 2.8V 2mA U701H

R1106
1.5K;5%;0201 C1107
MT6358
0.1uF;20%;6.3V;0201 RTC
M8
C1108 VRTC28
2.2uF;20%;6.3V;0402

TP1101
1
RTC CLKOUT
12x15MIL

F10
[5] RTC32K_CK RTC32K_1V8_0
G12
RTC32K_1V8_1
M7
RTC32K_2V8

U / MT6358W / A_1
A A

Title 11_POWER_MT6358_Clock REV: V10

DOCUMENT NO.: Design Name Size C

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 13 of 65

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Title REV: V10

12_POWER_MT6370-General
DOCUMENT NO.: Design Name Size C

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 14 of 65

5 4 3 2 1
 5 4 3 2 1

D D

C1301
L1301
2.2uF;20%;16V;0402 U1301 1.0uH;20%;2520

1 19
VAC SW1 VSYS [9,10,11,17,21,23,26,27,28,29,30,34]
24 20
[11,34] VBUS VBUS SW2 C1306 C1307 C1308
0.047uF;20%;16V;0201 10uF;20%;6.3V;0402 10uF;20%;6.3V;0402
C1302 10uF;20%;16V;0603
23 21
PMID BTST
10 22 REGN
NC1 REGN
C1305 4.7uF;20%;6.3V;0402
[5] CHD_DM 3 17
4 PG GND1 18
[28] WHITE_LED STAT GND2
R1301 10K;5%;0201
[6,26,28,34] SDA5 6 15
[4,5,6,8,10,12,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63] VIO18_PMU 5 SDA SYS1 16
[6,26,28,34] SCL5 SCL SYS2
C [5] EINT_CHG_0 7 C
8 INT 13
NC BAT1 VBAT [22,33,46]
[6] EINT_CHG_CE 9 14
CE BAT2
C1304
R1303 51K;5%;0201
11 REGN 10uF;20%;6.3V;0402
TS

gnd-pad4
gnd-pad3
gnd-pad2
gnd-pad1
12 R1304 0;0.5A;0201
QON PWRKEY_SW [11,32]
[5] CHD_DP 2
PSEL
BQ25601
R1302

28
27
26
25
51K;5%;0201

B B

A A

Title 13_POWER_MT6370-Charger + PP REV: V10

DOCUMENT NO.: Design Name Size C

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 15 of 65

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Schematic design notice of "27_POWER_SubPMIC-HV powers" page. Title 14_POWER_MT6370-HV powers REV: V10

Note 27-1: It is recommended to reserve 0-ohm and cap. for BOM fine tune to minimize RF de-sense. DOCUMENT NO.: Design Name Size C

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Note 27-2: It is recommended to reserve 0-ohm for BOM fine tune to minimize RF de-sense.

Date: Friday, June 14, 2019 Sheet 16 of 65

5 4 3 2 1
 5 4 3 2 1

D D

LDO for EMI_VDD1 of LPDDR4 VDD1

R1502
[9,10,11,15,21,23,26,27,28,29,30,34] VSYS
NF_0;0.5A;0201

R1501
[9,10] VS1_PMU 20 mil U1502 R1505
0;0.5A;0201 VIO18_PMU [4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63]
4 1 NF_0;0.5A;0201
C C1507 VIN VOUT C
1.0UF;20%;6.3V;0201 2 20 mil
3 GND1 5 1.8V 20 mil EMI_VDD1 [4,19]
EN NC

[4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63] VIO18_PMU ETA5053V180DF1E

C1509
1.0UF;20%;6.3V;0201

B B

A A

Title REV: V10

15_POWER_ThirdParty_Powers
DOCUMENT NO.: Design Name Size C

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 17 of 65

5 4 3 2 1
 5 4 3 2 1

D D

BATTERY
CONNECTOR [6,22,33,34]

[6,22,33,34]
USB_DM

USB_DP

TVS3604 TVS3605
USB_DM

USB_DP
[6,22,33,34]

[6,22,33,34]

1
N1

N1
SH3605 1 2 BATADC [11]

N2

N2
SINGLE-GND-L4

2
NF_PSED5V0H1BSF NF_PSED5V0H1BSF
Close to battery connector
C C
VBAT [15,33,46]

C3632

1
AZ3105-01F.R7G
C3629 C3630
10uF;20%;6.3V;0402
TVS3602 1.0UF;20%;6.3V;0201 33pf;30%;50V;0201

2
J3601

1 P+ P+ 8
R3601
[22] BATON_CONN_THERM 2 TH+ ID 7 2 1 BAT_ID [5,8]
SG3611 HT-COPPER GND
NF_0;0.5A;0201
1 2 3 TH- 6
ID
R3699
4 5 VBAT_GND [33]
P- P-
0.01;1%;0805

SG3601 SG3602 5050060810

R3602
[34] BATON_SUB 1 2
NF_0;0.5A;0201

R3603
[22] BATON_CONN_THERM 1 2 BATON_CONN [11,33]
CS_N [11]
0;0.5A;0201

2
CS_P [11]
TVS3603

N2
PESD3V3V1BCSF

N1
1
Battery pack is considered not present if BAT_ON is above 0.944*TREF

B B

A A

Title REV: V10

36_Battery/USB IF
DOCUMENT NO.: Design Name Size D

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 22 of 65

5 4 3 2 1
 5 4 3 2 1

D D

MAIN MIC

main GND

[21,34] MIC_IN1_P_CON C3821 1.0UF;20%;6.3V;0201AU_VIN0_P [12]

C3813
33pf;30%;50V;0201

[21,34] MIC_IN1_M_CON C3812 1.0UF;20%;6.3V;0201AU_VIN0_N [12]

Close to PMIC
68pF;30%;50V;0201
C3818 C3802
68pF;30%;50V;0201 TO CODEC
2

SG3803
SINGLE-GND-L4
C C
1

main GND

TOP MIC
R3829
1 2
MICBIAS1B [12,21]
0;1A;0402

C3801 0.1uF;20%;6.3V;0201

C3822 33pf;30%;50V;0201 AU_VIN2_P_CS [21]

B B
AU_VIN2_N_CS [21]
1

U3801
VDD

3 Close to BB C3809 1.0UF;20%;6.3V;0201[12] AU_VIN2_P

GND
OUT

SPV0842LR5H-1
C3808
2

100pF;30%;50V;0201

C3810 1.0UF;20%;6.3V;0201
[12] AU_VIN2_N
1

C3803 C3804
D3801
N1

C0201_NC C0201_NC
NF_PESD3V3V1BCSF
1

N2

R3828
0;0.5A;0201
2
2

main GND
2

SG3804
2

SINGLE-GND-L4
SG3801
1

SINGLE-GND-L4
1

A A

Title REV: V10

38_MIC
DOCUMENT NO.: Design Name Size D

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 24 of 65

5 4 3 2 1
 5 4 3 2 1

Main Camera 13M [6,27]

[6,27] SDA4
CAM_RST2
[6,27] SCL4
L4103
SCL4 [6,27]
SDA4
CAM_RST2
[6,27]
[6,27]
TP4124 CAM_MCLK2_CON [27]
[6] CAM_CLK2

NF_18pF;5%;50V;0201C4103

NF_33pF;5%;50V;0201C4104

NF_33pF;5%;50V;0201C4164

NF_33pF;5%;50V;0201C4165
J4101
68ohm;600mA;0402

Depth Camera 2M

1
24 1 VCAMA1_R_CON [27]
GND_MCAMAVDD
[27] CAM_MCLK0_CON 23 2
CAM_PDN0 [6,27]
22 3 J4102
21 4 SFYNC [27]
[6] RCN RDN0 [6] [27] DCAMA_CON 1 24 CAM1_AGND
20 5 RDP0 [6]
[6] RCP [6,27] CAM_RST2 2 23 CAM_MCLK2_CON [27]
19 6 RDN1 [6] [27] SFYNC 3 22
[6] RDN2 18 7 RDP1 [6] [6] RDN0_A 4 21 RCN_A [6]
[6] RDP2 17 8
RDN3 [6] [6] RDP0_A 5 20 RCP_A [6]
16 9
RDP3 [6] 6 19
[6,10,27] VCAMIO_PMU 15 10 SDA2 [6,27] DOVDD 1P8 7 18
14 11 SCL2 [6,27] [6,10,27] VCAMIO_PMU VCAMIO_PMU [6,10,27]
[10,27] VCAMD_PMU 8 17
13 12
[10,27] VLDO28_PMU R4144 0;1A;0402 AVDD 28 9 16
[6,10,27] VCAMA_PMU DCAMA_CON [27]
[6,27] SDA4 10 15 VCAMIO_PMU [6,10,27]
28 25
D 11 14 D
27 GND-4PIN 26 C4111 [6,27] SCL4 12 13

2
C4110 C4109
SG4111 CONN-24P-2ROW-GND4P SG4113
25 28

100pF;30%;50V;0201

4.7uF;20%;6.3V;0402
SINGLE-GND-L4 26 GND-4PIN 27 SINGLE-GND-L4

1.0UF;20%;6.3V;0201
1

1
CONN-24P-2ROW-GND4P

SG41011 2

SINGLE-GND-L4

[10,27] VLDO28_PMU VLDO28_PMU [10,27]

[27] DEPTH_WIDE_DVDD DEPTH_WIDE_DVDD [27]
Wide Camera 8M
SCL2 [6,27] CONN-24P-2ROW-GND4P
SCL2 [6,27] [10,27] VCAMD_PMU VCAMD_PMU [10,27] [6,10,27] VCAMIO_PMU VCAMIO_PMU [6,10,27]
26 27
SDA2 [6,27] L4101 SDA2 [6,27] [6,10,27] VCAMIO_PMU 25
GND-4PIN
28
VCAMIO_PMU [6,10,27] R4147 0;1A;0402
[6,10,27] VCAMA_PMU VCAMA1_W_CON [27]
CAM_CLK0 [6] R4162 0;1A;0402 R4148 1 12 13
CAM_MCLK0_CON [27] [10] VCAMA2_PMU VCAMA1_R_CON [27] [6,27] RCAM_AVDD [27] VCAMA1_W_CON
11 14
24 WCAM_AGND
CAM_PDN0 [6,27] CAM_PDN0 [6,27] NF_0;1A;0402 [6,27] WCAM_RESET3 2 23 CAM_MCLK3_WCAM [27]
68ohm;600mA;0402 R4143 NF_0;1A;0402 C4160 C4159 C4161 C4162 10 15
[6,27] RCAM_AVDD
C4114C4199 C4198 C4158
3 9 16
22
C4115 C4117 [6] CSI2_LANE0_N_R 4 21 CSI2_CLK_N_R [6]
C4107

C4116 C4118 C4119 I2C_WIDE_SCL

[6,27] 8 17
C4108

C4166

C4167

100pF;30%;50V;0201

100pF;30%;50V;0201
5 20

4.7uF;20%;6.3V;0402
1.0UF;20%;6.3V;0201
I2C_WIDE_SCL
[6,27] [6] CSI2_LANE0_P_R CSI2_CLK_P_R [6]
I2C_WIDE_SDA
[6,27] L4104 [6] CSI2_LANE1_N_R 6 7 18 19
2.2uF;20%;6.3V;0201

100pF;30%;50V;0201
2.2uF;20%;6.3V;0201 I2C_WIDE_SDA
[6,27]

4.7uF;20%;6.3V;0402

100pF;30%;50V;0201
7 6 19 18 CSI2_LANE2_N_R [6]

4.7uF;10%;10V;0603
1.0UF;20%;6.3V;0201
[6] CSI2_LANE1_P_R

1.0UF;20%;6.3V;0201
CAM_CLK3 [6] 5 20
CAM_MCLK3_WCAM [27] 8 17
NF_18pF;5%;50V;0201

NF_2.2uF;20%;6.3V;0201 [6] CSI2_LANE3_N_R CSI2_LANE2_P_R [6]

NF_33pF;5%;50V;0201

NF_18pF;5%;50V;0201

NF_33pF;5%;50V;0201

68ohm;600mA;0402 4 21
CAM_RST3 [6] WCAM_RESET3 [6,27] [6] CSI2_LANE3_P_R 9 3 22
16 VCAMIO_PMU [6,10,27]
10 15

NF_18pF;5%;50V;0201C4156

NF_18pF;5%;50V;0201 C4102
NF_33pF;5%;50V;0201C4157

NF_33pF;5%;50V;0201C4101
I2C_WIDE_SDA 2 23
11 1 24
14 DEPTH_WIDE_DVDD [27]
R4157 12 13

2
[4,41] SDA4
I2C_WIDE_SCL J4103
0;0.5A;0201 SG4114

2
R4159 SINGLE-GND-L4
C SG4102 [4,41] SDA2 C
SINGLE-GND-L4 SG41101 2 NF_0;0.5A;0201

1
[4,41] SCL4
SINGLE-GND-L4

1
R4158
0;0.5A;0201
R4160
[4,41] SCL2
NF_0;0.5A;0201 R4155 R4156
0;0.5A;0201
If use 8M WIDE R4157=0;R4158=0; R4159=NC;R4160=NC; NF_0;0.5A;0201
If use 2M Micro R4157=NC;R4158=NC; R4159=0;R4160=0;
[10,27] VLDO28_PMU
If use 8M WIDE R4156=0;R4155=NC;
If use 2M Micro R4156=NC;R4155=0;

Rear CAM and other Camera AVDD 2P8

VSYS [9,10,11,15,17,21,23,26,27,28,29,30,34]

Front Camera 8M C4147

1.0UF;20%;6.3V;0201
U4104
4 1 RCAM_AVDD [6,27]
IN OUT
CONN-24P-2ROW-GND4P 2
GND1 C4148 C4149
REAR_CAM_AVDD_EN [6] 3 5
26 27 EN GND2

33pf;30%;50V;0201
1.0UF;20%;6.3V;0201
25
GND-4PIN
28
ETA5053V280DF1E
12 13
[6,27] SCL2 11 14 FCAM_DVDD [27] 1
TP4104
[6,27] SDA2 10 15
VCAMIO_PMU [6,10,27]
[6] CSI2_LANE3_P_F 9 16
[6] CSI2_LANE3_N_F 8 17 CSI2_LANE2_P_F [6]
B [6] CSI2_LANE1_P_F 7 18 CSI2_LANE2_N_F [6] B
6 19
[6] CSI2_LANE1_N_F
[6] CSI2_LANE0_P_F 5 20 CSI2_CLK_P_F [6]
4 21
[6] CSI2_LANE0_N_F CSI2_CLK_N_F [6]
3 22
[6,27] CAM_PDN3 2 23 CAM_CLK1_CON [27]
1 24 FCAM_AGND
[27] VCAMA1_F_CON
2

J4104
SG4112
SINGLE-GND-L4
1

5M 8M CAM DVDD

[9,10,21] VS2_PMU
[9,10,11,15,17,21,23,26,27,28,29,30,34] VSYS
C4152 U4102
0;0.5A;0201 R4163 C4131
VCAMD_PMU [10,27]
NF_1.0UF;20%;6.3V;0201 U4103 1.0UF;20%;6.3V;02014 1
DEPTH_WIDE_DVDD [27]
VIN VOUT
VSYS [9,10,11,15,17,21,23,26,27,28,29,30,34] 2
SCL2 [6,27] SCL2 [6,27] 4 CAM_DVDD_1P2_EN [6] 3 GND1 5
IN EN GND2
REAR_CAM_DVDD_EN [5] 3 1 FCAM_DVDD [27]
SDA2 [6,27] EN OUT AP7343D-12FS4-7B C4132
SDA2 [6,27] [27] FCAM_DVDD FCAM_DVDD [27] 1
L4102 2 TP4119

GND
BIAS 1.0UF;20%;6.3V;0201
[6,10,27] VCAMIO_PMU VCAMIO_PMU [6,10,27] C4151 C4153
CAM_CLK1 [6] CAM_CLK1_CON [27] C4150
NF_SGM2038-1.2XUDY4G/TR

5
R4140 0;1A;0402 NF_0.1uF;20%;6.3V;0201

NF_33pf;30%;50V;0201
NF_1.0UF;20%;6.3V;0201
68ohm;600mA;0402 [6,10,27] VCAMA_PMU VCAMA1_F_CON [27] 1
TP4103
CAM_PDN3 [6,27] CAM_PDN3 [6,27]
R4142 NF_0;1A;0402
[6,27] RCAM_AVDD C4143 C4144 C4140 C4141 C4142
NF_18pF;5%;50V;0201C4136
NF_33pF;5%;50V;0201C4137

NF_33pF;5%;50V;0201C4138

NF_33pF;5%;50V;0201C4139

A A
100pF;30%;50V;0201

4.7uF;20%;6.3V;0402
1.0UF;20%;6.3V;0201

100pF;30%;50V;0201
4.7uF;10%;10V;0603

Title REV: V10

41.Camera IF
2

SG4108 DOCUMENT NO.: Size D

98870_1_11_201906141113
SINGLE-GND-L4

DEPARTMENT: DEPARTMENT DESIGNER: DESIGNER

1

Date: Friday, June 14, 2019 Sheet 27 of 65

5 4 3 2 1
 5 4 3 2 1

J4501

MSDC1_DAT2_CON [31] P1 G1
P2 DAT2 GND G2
MSDC1_DAT3_CON [31]
P3 CT/DAT3 GND G3
MSDC1_CMD_CON [31]
VMCH_PMU [10,31] P4 CMD GND G4
VDD GND

T-F
MSDC1_CLK_CON [31] P5 G5
P6 CLK GND G6
P7 VSS GND G7
MSDC1_DAT0_CON [31]
P8 DAT0 GND G8
MSDC1_DAT1_CON [31]
DAT1 GND G9
GND G10
GND G11
TF CARD EINT_SIM_SD_CON [31]
A1

A2
DET_LEVER
GND
GND
G12

DET_SW
D D

R4509 VSIM1_PMU_CON [31] AC11 AC51

[6] MSDC1_DAT2 22;5%;0201 VCC-SIMA GND
MSDC1_DAT2_CON [31] AC12 AC52
AC13 VCC1-SIMA SIM-A GND AC53
VCC2-SIMA GND
[6] MSDC1_DAT3 R4510 22;5%;0201
MSDC1_DAT3_CON [31] AC21 AC61
SIM1_SRST_CON [31] AC22 RST-SIMA VPP-SIMA AC62
AC23 RST1-SIMA VPP1-SIMA AC63
[6] MSDC1_CMD R4511 22;5%;0201 RST2-SIMA VPP2-SIMA
MSDC1_CMD_CON [31]
AC31 AC71
SIM1_SCLK_CON [31] AC32 CLK-SIMA I/O-SIMA AC72 [31] SIM1_SIO_CON
[10,31] VMCH_PMU AC33 CLK1-SIMA I/O1-SIMA AC73
CLK2-SIMA I/O2-SIMA

[6] MSDC1_CLK R4512 22;5%;0201

MSDC1_CLK_CON [31]
BC11 BC51
VSIM2_PMU_CON [31] BC12 VCC-SIMB GND BC52
BC13 VCC1-SIMB GND BC53
VCC2-SIMB GND
BC21
SIM-B BC61
[6] MSDC1_DAT0 R4513 22;5%;0201 RST-SIMB VPP-SIMB
MSDC1_DAT0_CON [31] SIM2_SRST_CON [31] BC22 BC62
BC23 RST1-SIMB VPP1-SIMB BC63
RST2-SIMB VPP2-SIMB
[6] MSDC1_DAT1 R4514 22;5%;0201
MSDC1_DAT1_CON [31] BC31 BC71
SIM2_SCLK_CON [31] BC32 CLK-SIMB I/O-SIMB BC72 [31] SIM2_SIO_CON
BC33 CLK1-SIMB I/O1-SIMB BC73
CLK2-SIMB I/O2-SIMB

2
TVS4514 TVS4513 TVS4512

2
2

2
TVS4517 TVS4516 TVS4502 TVS4515
C4570

N2

N2

N2
N2
N2

N2

N2
SIM-T-CAF00-20137-1029
C0201_NC
C4511
Note:

N1

N1

N1
N1
HIGH when Tray inserted

N1

N1

N1
2.2uF;20%;6.3V;0402
NF_PSED5V0H1BSF
NF_PSED5V0H1BSF

1
NF_PSED5V0H1BSF

1
NF_PSED5V0H1BSF NF_PSED5V0H1BSF

1
NF_PSED5V0H1BSF PESD5V0S1BL

SIM&SD Connector
C C

SIM1 [10,31] VMCH_PMU

[5] SIM1_SCLK R4503 22;5%;0201

SIM1_SCLK_CON [31]

[5] SIM1_SRST R4504 22;5%;0201

SIM1_SRST_CON [31]
R4501 22;5%;0201
[4,10] VSIM1_PMU VSIM1_PMU_CON [31]
R4525
100K;5%;0201
C4530
0.1uF;20%;6.3V;0201
[5] SIM1_SIO 22;5%;0201 R4505 SIM1_SIO_CON [31]
2

2
2

TVS4511 TVS4503 TVS4504

2

TVS4505
N2

N2
N2

B B
N2

N1

N1
N1

C4501
N1

1
1

1.0UF;20%;6.3V;0201
1

NF_PSED5V0H1BSF PESD5V0S1BL
NF_PSED5V0H1BSF NF_PSED5V0H1BSF

SIM2 [4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,33,34,37,40,41,46,49,63] VIO18_PMU

[5] SIM2_SCLK R4516 22;5%;0201 R4529

SIM2_SCLK_CON [31]
[11] SD_CARD_DET_N_PMU R4521
R4517 22;5%;0201 0;0.5A;0201
[5] SIM2_SRST SIM2_SRST_CON [31] 100K;1%;0201
R4518 22;5%;0201
[4,10] VSIM2_PMU VSIM2_PMU_CON [31]
SH4511

[6] EINT_SD L1
EINT_SIM_SD_CON [31]
SH4512
22;5%;0201 R4520

2
[5] SIM2_SIO SIM2_SIO_CON [31] L1 TVS4501
[5] INT_SIM1

N2
SH4513
2

L1
2

TVS4507 TVS4508 TVS4509 [5] INT_SIM2

2

N1
TVS4518
N2

N2
N2
N2

NF_PSED5V0H1BSF

1
N1

N1
N1

C4502
N1

1
1

1.0UF;20%;6.3V;0201
1

NF_PSED5V0H1BSF PESD5V0S1BL
NF_PSED5V0H1BSF NF_PSED5V0H1BSF

A A

Title REV: V10

45_SIM/TF IF
DOCUMENT NO.: Design Name Size D

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

5 4 3 2 Date: 1 Friday, June 14, 2019 Sheet 31 of 65

 5 4 3 2 1

CT BT USB
Grounding
TP4712 TP4780 TP4765 TP4714 TP4716 TP4717
DEVICE MODE CONF J4709
1 TP4713
[15,22,46] VBAT TP-1.5MM TP-1MM TP-1MM TP-1.5MM TP-1MM TP-1MM
TP-1.5MM
[4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63] VIO18_PMU AT12-110001-04

D D

1
1
TP4721
[6,22,34] USB_DM 1
[11,22] BATON_CONN 1 TP-1.5MM R4723
R4724
[6,22,34] USB_DP J4708 2

1
TP4731 [34] VBUS_USB_CON AT12-110001-04
1 TP-1.5MM
USB_CC1_CON [34] 10K;5%;0201 10K;5%;0201 BOARD_ID

2
TP4730
1 TP-1.5MM USB_CC2_CON [34] R4706 0;0.5A;0201[6] 1
HW_ID2
J4706 2
R4707 0;0.5A;0201 [6]
BAT GND place near the connect
HW_ID1
AT12-110001-04

KEYS R709 R710

1

1
TP4781
1 [32] PWRKEY_CONN_TP
POWER_ON 1
TP4703
TP-1MM C4721 C4722 J4707
2
[22] VBAT_GND TP-1.5MM
[32] KPCOL2_TP
FASTBOOT VOL_DOWN 1 TP-1MM
0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201
TP4705 10K;5%;0201 10K;5%;0201 AT12-110001-04

2
HOLE4700 HOLE4702 HOLE4703 HOLE4704 HOLE4710

FORCE DOWNLOAD VOL_UP 1 1

PTH-1.6MM PTH-1.6MM PTH-1.6MM PTH-1.6MM PTH-1.6MM
[32] KPCOL0_TP TP4766 TP-1MM
J4701
2
AT12-110001-04

1
1
HOLE4707 HOLE4708 HOLE4709
2 HOLE4705 HOLE4706
PTH-1.6MM PTH-1.6MM PTH-1.6MM
PTH-1.6MM PTH-1.6MM

SPR4702
AT05-110001-01
PTH

1
1

1
C C

JTAG CONNECTOR

1
J4703

UART
J4705 AT12-110001-04
1 2 TDO
SPI0_MI_JTAG [29]
3 4 TCK SPI0_CLK_JTAG [29]
TMS 5 6 TDI
[29] SPI0_CSB_JTAG SPI0_MO_JTAG [29]
7 8
1
9 10
VIO18_PMU [4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63] R4716 1K;5%;0201 1
[6,33] UTXD0 11 12 [6,33] UTXD0 TP4761 2
[6,33] URXD0 13 14
15 16 [6,33] URXD0 R4717 1K;5%;0201
JTRST [6] TP-0.8MM
J4704
1 TP4762
17 18 AT12-110001-04
C4723
NF_0.01uF;20%;25V;0201 TP-0.8MM
CONN-16P-2ROW-GND2P-A

TOP BOSS Grounding

B B

SHIELDING

SH4701
BOT SH4702
MARK Waterproof
SH4706

FM4701 FM4703
FM4702 FM4704
屏蔽罩 屏蔽罩 屏蔽罩 1mm 1mm 1mm 1mm
J4712

1
PMU WCN
1

RF
1

1
1

1
ICO-WATERPROOF-D3

A
TOP BAD MARK J4713 A
BM4705 BM4706
SH4704 SH4705 SH4703 BAD Mark BAD Mark 1

屏蔽罩 屏蔽罩 屏蔽罩 SC10-210001-01

1

RF PA BB
1

Smart PA
Title
47_Testpoint/Shielding/GNDREV: V10

DOCUMENT NO.: Design Name Size D

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 33 of 65

5 4 3 2 1
 5 4 3 2 1

OVP
D D

SUB CONN.
R4801 0;1A;0603

U4801
J4801 R4802 0;1A;0603 6.8V
[33,34] VBUS_USB_CON
42 41 B3 A2

1
POWER VBUS_USB_CON [33,34] IN1 OUT1 VBUS [11,15,34]
R4804 R4805 C2 A3
C3 IN2 OUT2 B2
C4804 IN3 OUT3
1 40 C4805 NF_51K;5%;0201
[23] SPK1_P_FB 2 39 SPK1_N_FB [23] 1.0uF;10%;25V;0402

2
150pF;10%;50V;0201 C4806

2
3 38

3
4 37 C1 B1

N2
GND
47K;5%;0201 OVLO ACOK
[23] SPK_OUT_P1 5 36 0.01uF;20%;25V;0201
SPK_OUT_N1 [23] D4802 D4801
6 35

1
7 34 MIC_IN1_M_CON [21,24] NF_PTVS18VU1UPA NF_WE07DF-B

N1
[5,49] MIPI2_SCLK AW33905

A1
8 33 MIC_IN1_P_CON [21,24] R4806
[5,49] MIPI2_SDATA 0;0.5A;0201
9 32

1
10 31 MICBIAS1A [12,21]
[33,34] USB_CC2_CON 11 30

2
[33,34] USB_CC1_CON 12 29 USB_DM [6,22,33]
[22] BATON_SUB 13 28
USB_DP [6,22,33]
14 27
15 26 VSW_HAP_P [23]
[4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63] VIO18_PMU 16 25
VSW_HAP_M [23]
17 24
18 23 VFE28_PMU [10,46]
[63] HB_ANT_SAR_PRI
[63] LMB_ANT_SAR_REF 19 22
20 21
[63] LMB_ANT_SAR_PRI

43 POWER 44

WP27D-SX40VA3

C C
MAIN MIC CS7331P.
R4857
1 2

NF_0;0.5A;0201

U4802

[34] VDD_CCLOGIC 1 4 VSYS [9,10,11,15,17,21,23,26,27,28,29,30]

VOUT VIN
2
5 GND1 3 VIO18_PMU [4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63]
C4816
GND2 EN

AP7343D-33FS4-7B C4817
1.0UF;20%;6.3V;0201

VIO18_PMU [4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63] NF_1.0UF;20%;6.3V;0201

1
R4856
NF_200K;1%;0201
[33,34] VBUS_USB_CON

2
[6] USB_ID

R4812
CC LOGIC R4859NF_0;0.5A;0201
1 2

NF_51K;5%;0201 1 2
[4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63] VIO18_PMU
R4858NF_0;0.5A;0201
R4810 33;5%;0201
[34] VDD_CCLOGIC
[33,34] USB_CC1_CON USB_TYPEC_CC1 [34]

C4815
USB_TYPEC_CC2 [34]

12

11

10
[33,34] USB_CC2_CON

9
U4804
R4811 33;5%;0201 NF_0.1uF;20%;6.3V;0201
2

ID
GND
VDD

EN_N
D4825 D4826
N2

N2

WE07DF-B WE07DF-B SCL5 [6,15,26,28,34]

1 8
CC1 SCL/OUT2
N1

N1

2 7

INT_N/OUT3
CC2 SDA/OUT1 SDA5 [6,15,26,28,34]

VBUS_DET
B B
1

PORT

ADDR
3

6
NF_TUSB320LI

VIO18_PMU [4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63]

U4803
R4853
USB_TYPEC_CC1 [34] C1 B1 1 2 VDD_CCLOGIC [34]
CC1 VCONN

1
USB_TYPEC_CC2 [34] A1 A3
CC2 VDD 0;0.5A;0201
R4851 4.7K;5%;0201 R4817
1 2 A2 B3 SCL5 [6,15,26,28,34] 2.2K;5%;0201
[11,15,34] VBUS VBUS SCL
150K C3

2
C2 SDA SDA5 [6,15,26,28,34]
GND B2
INT_N CC_INT [6]

C4810 RT1711H C4811 C4812

C4813 C4814 0.1uF;20%;25V;0201
0.1uF;20%;25V;0201
0.1uF;20%;25V;0201
220pF;20%;50V;0201220pF;20%;50V;0201

Change 330pF

A A

Title REV: V10

48_Sub PCB IF
DOCUMENT NO.: Design Name Size D

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 34 of 65

5 4 3 2 1
 5 4 3 2 1

D D

J6101
ECT818000500
J6102

C6101 C6123 C6107

2 RF_AntMLB_TRX_ANT RF_AntMLB_TRX_RFSWITCH_OUT 2 1 RF_AntMLB_TRX_RFSWITCH_IN
I/O OUT IN RF_AntMLB_TRX_RFSWITCH [41]

GND1
GND2
GND3

GND2
GND1
33pF;5%;50V;0201 33pF;5%;50V;0201 33pF;5%;50V;0201
L6125

3
4
1
L0201_NC 818004112

4
3
Note2:
L6130
68nH;5%;0201

R6103
10K;5%;0201

ANT_DET_LMB
U6101
C6108

5
RF-MXD8546C
RF_AntMLB_TRX_DPDT_IN1 R6104
4 6

GND3
[48] RF_Ant_DRX_DPDT_OUT2 RFI1 RFI2 BPI_BUS3 [5]
3 7 0;0.5A;0201
C6124 GND2 GND4 33pF;5%;50V;0201
RF_AntMLB_TRX_DPDT_OUT1 2 8
RFO1 RFO2 RF_AntMLB_TRX_DPDT_OUT2 [48]

VDD
R6105
1 9 100K;5%;0201
C
33pF;5%;50V;0201 GND1 VCTL C
C6102

VIO_1P8_ANT_DET_LMB
10
47pF;10%;50V;0201

L6131
VIO18_PMU [4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63]
[5] BPI_BUS10 68nH;5%;0201

[41,46,48,49,51,52] LTE_VFE28

100pF;5%;50V;0201 C6122 100pF;5%;50V;0201

C6103

C6121 100pF;5%;50V;0201

J6103
ECT818000500 Note1: J6104

C6104
2 RF_AntHB_TRX_ANT RF_AntHB_TRX_RFSWITCH_OUT 2 1
I/O OUT IN RF_AntHB_TRX_RFSWITCH [41]
GND1
GND2
GND3

GND2
GND1
33pF;5%;50V;0201

B L6101 B
3
4
1

818004112
L0201_NC

4
3
R6106
10K;5%;0201

ANT_DET_HB
R6107
BPI_BUS2 [5]
0;0.5A;0201

C6105 Note1:
R6108
100K;5%;0201
47pF;10%;50V;0201
Note2:
VIO_1P8_ANT_DET_HB

L6102
VIO18_PMU [4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49,63]
68nH;5%;0201

C6106

100pF;5%;50V;0201

A A

Title REV: V10

DOCUMENT NO.:Design Name = 98870_1_11_201906141113 Size D

DEPARTMENT: DEPARTMENT = WINGTECH-SZ

DESIGNER: DESIGNER = LIUFENGLEI

Date: Page Modify Date = Friday, June 14, 2019 Sheet 40 of 65

5 4 3 2 1
 5 4 3 2 1

D D

J6901

AT12-110001-04
Note1: J6905

C6905 R6906 L6907 C6910 C6911

1 RF_Ant_DRX_ANT RF_Ant_DRX_ANT_MATCH1 RF_Ant_DRX_ANT_MATCH2 RF_Ant_DRX_RFSWITCH_OUT 2 1
OUT IN RF_Ant_DRX_RFSWITCH [49]

GND2
GND1
2
33pF;5%;50V;0201 33pF;5%;50V;0201 0;0.5A;0201 33pF;5%;50V;0201 33pF;5%;50V;0201
Note2:
C6909 C6096
L6905 R6907 818004112

4
3
82nH;5%;0201 L0201_NC L6903
J6902 L6901
L0201_NC
100nH;5%;0201 33pF;5%;50V;0201 33pF;5%;50V;0201
AT14-110001-04

1 C6907

2 ANT_SAR_DIV [63]
U6902
100pF;5%;50V;0201

9
RF-MXD8546C

RFI2

GND4

RFO2

VCTL
C6908
5 10
GND3 VDD

100pF;5%;50V;0201

GND2

GND1
RFO1
C C

RFI1
4

1
[5] BPI_BUS8
LTE_VFE28 [40,41,46,48,49,51,52]

[40] RF_Ant_DRX_DPDT_OUT2

[40] RF_AntMLB_TRX_DPDT_OUT2

C6902
L6923
[63] DIV_ANT_SAR_REF
100nH;5%;0201
33pF;5%;50V;0201

J6903

B AT14-110001-04 B

Note1:

RF_Ant_DRX_SP4T R6908 RF_Ant_DRX_SP4T_RFC

1

2
J6904
33pF;5%;50V;0201
1

Note2:
AT12-110001-04 NF_PESDUC2XD18VB L6902
N1

TVS6901 82nH;5%;0201
N2

1
2

J6911
10

U6901
AT12-110001-04
[40,41,46,48,49,51,52] LTE_VFE28 4
RFC

VDD

[5] BPI_ANT2 5
CTRL1 RF_Ant_DRX_SP4T_RF1 R6903
1 0;0.5A;0201
1 RF1
[5] BPI_ANT0 6
CTRL2 2 RF_Ant_DRX_SP4T_RF2 R6904 0;0.5A;0201
2 RF2
R6901
RF_Ant_DRX_GND

C6901 C6904 9 RF_Ant_DRX_SP4T_RF3_L L6904 82nH;5%;0201 RF_Ant_DRX_SP4T_RF3 0;0.5A;0201

C6903 RF3
100pF;5%;50V;0201 7
100pF;5%;50V;0201 GND2 RF_Ant_DRX_SP4T_RF4 R6902
100pF;5%;50V;0201 8 0;0.5A;0201
3 RF4
GND1
BGSA14GN10

Note1:
L6922
33pF;5%;50V;0201

Note1:

A Note2: A

Note3:

Note4:

Title REV: V10

Page Name = 69_Diversity_ANT
DOCUMENT NO.: Size
Design Name = 98870_1_11_201906141113 D

DEPARTMENT: DESIGNER:
DEPARTMENT = WINGTECH-SZ DESIGNER = LIUFENGLEI

Date: Page Modify Date = Friday, June 14, 2019 Sheet 48 of 65

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Title Reserved REV: V10

DOCUMENT NO.: Design Name Size A1

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 50 of 65

 5 4 3 2 1

D D

B1/4/66 DRX L7207 L7208

B2 DRX
L7209 RF_B1B3_DRX_LNA_COMM
RF_B1_DRX_SAW_IN U7205
[49] RF_B1_DRX_ASM 1.5NH;0.1nH;0201 U7206 SAFFB1G96AB0F0A
1.2NH;0.1nH;0201 SFWG42CBB02 22pF;5%;50V;0201 C7223 L7220 C7203
RF_B2_DRX_SAW_IN 1 4 RF_B2_DRX_SAW_OUT RF_B2_DRX_RFIC_MATCH
Note1: [49] RF_B2_DRX_ASM UNBL1 UNBL2 RF_B2_DRX_RFIC [37]
L7210 U7208
1.0NH;0.1nH;0201

GND1

GND2

GND3
7.5NH;3%;0201 1.8pF;0.05pF;50V;0201 18pF;5%;50V;0201
6 1 Note1:
L7218 VEN GND1 L7222 L7229
C7224
RF_B1B3_DRX_SAW_OUT RF_B1B3_DRX_LNA_IN L0201_NC 1.5NH;0.1nH;0201
6 1 5 2

5
B1 B1 / B3 RFIN VDD C7207 C7206 2.7NH;0.1nH;0201
L7230 L0201_NC RF_B1B3_DRX_LNA_OUT RF_B1B3_DRX_RFIC_MATCH
?MHZ 4 3
RF_B3_DRX_SAW_IN GND2 RF OUT RF_B1B3_DRX_RFIC [37]
9
[49] RF_B3_DRX_ASM B3
2.0NH;0.1nH;0201 [5] BPI_BUS7 C0201_NC 10PF;5%;50V;0201
2 RTC8606M
GND1 100pF;5%;50V;0201 L7226
L7211
L7270 C7232 L0201_NC 1.5NH;0.1nH;0201
7 3

B3 DRX 10NH;3%;0201

8
GND5

GND6
GND2

GND3
4
L7219
2.7NH;0.1nH;0201

10 5 LTE_VFE28 [40,41,46,48,49,51,52]
GND7 GND4
1000pF;20%;50V;0201

L7212

C C

B5 DRX
L7201 L7202
U7203 MS11U881M-RX05S
RF_B8_DRX_LNA_COMM L7214 C7208
L7213
7.5NH;3%;0201 RF_B5_DRX_ASM RF_B5_DRX_SAW_IN 1 4 RF_B5_DRX_SAW_OUT RF_B5_DRX_RFIC_MATCH

B8 DRX 22pF;5%;50V;0201
[49] RF_B5_DRX_ASM
4.3NH;3%;0201
UNBL1 UNBL2
8.2NH;3%;0201
RF_B5_DRX_RFIC [37]

GND1

GND2

GND3
15pF;5%;50V;0201
Note1: U7202 L7216
MS11U942M-RX08S Note1: 15NH;3%;0201
C7209 C7225

5
U7201 6 1
C7201 L7204 VEN GND1 1.0pF;0.05pF;50V;0201 15NH;3%;0201
RF_B8_DRX_SAW_IN 1 4 RF_B8_DRX_SAW_OUT RF_B8_DRX_LNA_IN
5 2
[49] RF_B8_DRX_ASM UNBL1 UNBL2 RFIN VDD C7210 C7215
L0201_NC
GND1

GND2

GND3

4 3 RF_B8_DRX_LNA_OUT RF_B8_DRX_RFIC_MATCH
33pF;5%;50V;0201 GND2 RF OUT RF_B8_DRX_RFIC [37]
L7205 C0201_NC
L7203 12NH;3%;0201 27pF;5%;50V;0201
L0201_NC [5] BPI_BUS0
RTC8606L L7227
2

330pF;5%;25V;0201 L7206
C7211 L0201_NC
12NH;3%;0201

LTE_VFE28 [40,41,46,48,49,51,52]

1000pF;20%;50V;0201

B C7214 B

B28 DRX
RF_B20_DRX_LPF_COMM1

Note1:

B20 DRX R7294

0;0.5A;0201
RF_B20_DRX_LPF_COMM
C7229

C7230
RF_B28_DRX_SAW_IN 1
U7207 SAFFB780MAA0F0A

4 RF_B28_DRX_SAW_OUT
L7224 C7231
RF_B28_DRX_RFIC_MATCH
22pF;5%;50V;0201 [49] RF_B28_DRX_ASM UNBL1 UNBL2 RF_B28_DRX_RFIC [37]
Note1: FL7209 4.3NH;3%;0201

GND1

GND2

GND3
RFLPF10050G9DM1T76 U7220 SFH806BA002 33pF;5%;50V;0201 22pF;5%;50V;0201
R7262 C7221 C7222 C7216 C7217
L7223 L7225
RF_B20_DRX_ASM RF_B20_DRX_LPF_IN6 4 RF_B20_DRX_LPF_OUT RF_B20_DRX_SAW_IN 4 1 RF_B20_DRX_SAW_OUT RF_B20_DRX_RFIC_MATCH 15NH;3%;0201 15NH;3%;0201
[49] RF_B20_DRX_ASM RF_B20_DRX_RFIC [37]

5
INPUT OUTPUT UNBL2 UNBL1 L7217
10NH;3%;0201
GND1
GND2

GND3

GND2

GND1

C0201_NC 1.0pF;0.05pF;50V;0201
39pF;5%;50V;0201
NC1
NC2

0;0.5A;0201 C0201_NC C7218

L7215
C7204 15NH;3%;0201
C7205
1
3

2
5

27nH;3%;0201 C0201_NC
C0201_NC

A A
Note1:

Title REV: V10

Page Name = 72_DRX_LMB
DOCUMENT NO.: Size
Design Name = 98870_1_11_201906141113 D

DEPARTMENT: DEPARTMENT = WINGTECH-SZ

DESIGNER: DESIGNER = LIUFENGLEI

Date: Page Modify Date = Friday, June 14, 2019 Sheet 51 of 65

5 4 3 2 1
 5 4 3 2 1

D D

Note1:
L7302 L7303
Note1:
RF_B7_DRX_LNA_COMM

0;0.5A;0201 U7301 0;0.5A;0201

U7302 MS11U2G65-RX07S 6 1
C7304 L7301 VEN GND1
RF_B7_DRX_ASM RF_B7_DRX_SAW_IN 1 4 RF_B7_DRX_SAW_OUT RF_B7_DRX_LNA_IN 5 2
[49] RF_B7_DRX_ASM UNBL1 UNBL2 RFIN VDD L7305 C7305
L0201_NC

GND1

GND2

GND3
4 3 RF_B7_DRX_LNA_OUT RF_B7_DRX_RFIC_MATCH
33pF;5%;50V;0201 GND2 RF OUT RF_B7_DRX_RFIC [37]
L0201_NC
L7909 [5] BPI_ANT1 C7302 8.2pF;0.25pF;50V;0201
L7307 RTC8606M

5
5.1NH;3%;0201
5.1NH;3%;0201
C7312
100pF;5%;50V;0201 2.2pF;0.25pF;50V;0201
L7316
L0201_NC

B7 DRX C7301
LTE_VFE28 [40,41,46,48,49,51]

100pF;5%;50V;0201

C C

U7307 SFHG96AA402 C7310

C7320 L7318
5.6pF;0.25pF;50V;0201
RF_B41_DRX_ASM RF_B41_DRX_SAW_IN 1 4 RF_B41_DRX_SAW_OUT RF_B41_DRX_RFIC_MATCH
[49] RF_B41_DRX_ASM UNBL1 UNBL2 RF_B41_DRX_RFIC [37]
1.5NH;0.1nH;0201

GND1

GND2

GND3
33pF;5%;50V;0201
L7322
3.9NH;0.1nH;0201 C7311
2.2pF;0.25pF;50V;0201 L7319

5
L0201_NC

B38/41 DRX

B B

U7303 SAFFB2G35AA0F0A
L7309 C7321 C7322
RF_B40_DRX_ASM RF_B40_DRX_SAW_IN 1 4 RF_B40_DRX_SAW_OUT RF_B40_DRX_RFIC_MATCH
[49] RF_B40_DRX_ASM UNBL1 UNBL2 RF_B40_DRX_RFIC [37]

GND1

GND2

GND3
6.8pF;0.25pF;50V;0201
27pF;5%;50V;0201 6.8pF;0.25pF;50V;0201
C7314 L7314
L7312
9.1NH;3%;0201 3.9NH;0.1nH;0201 1.5NH;0.1nH;0201
2

B40 DRX

A A

Note1:

Title REV: V10

Page Name = 73_DRX_HB
DOCUMENT NO.: Size
Design Name = 98870_1_11_201906141113 D

DEPARTMENT: DEPARTMENT = WINGTECH-SZ DESIGNER: DESIGNER = LIUFENGLEI

Date: Page Modify Date = Friday, June 14, 2019 Sheet 52 of 65

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Title
<Title>

Size Document Number Rev

A1 <Doc> 1.0

Date: Friday, June 14, 2019 Sheet 53 of 65

 5 4 3 2 1

D D

C C

B B

A A

Title Reserved REV: V10

DOCUMENT NO.: Design Name Size A1

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 54 of 65

 5 4 3 2 1

D D

C C

B B

A A

Title Reserved REV: V10

DOCUMENT NO.: Design Name Size A1

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 55 of 65

 5 4 3 2 1

D D

[56] AVDD18_WBT

C7701 0.1uF;20%;6.3V;0201
CONN_BT_DATA
CONN_BT_DATA [6]
C7702 100pF;5%;50V;0201 CONN_BT_CLK
CONN_BT_CLK [6]
CONN_WF_CTRL0
CONN_WF_CTRL0 [6]
CONN_WF_CTRL1
U7702 CONN_WF_CTRL1 [6] L7712
CONN_WF_CTRL2

30

29

28

27

26

25

24

23

22

21
CONN_WF_CTRL2 [6]
[56] FM_AVDD28 VCN28_PMU [10,58]

AVDD18_WBT2

AVDD18_WBT1

WF_CTRL0

WF_CTRL1

WF_CTRL2
WIFI_AUX_2G

WB_VDET_2G

WIFI_VDET_5G

BT_DATA

BT_CLK
120ohm;200mA;0201
C7718
1.0UF;20%;6.3V;0201

31 20 WF_IP
[57] RF_WB_TRX_ANT WB_RF_2G WF_IP WF_IP [6]
R7711 0;0.5A;0201
[56] AVDD18_GPS VCN18_PMU [10]
[56] AVDD33_WBT
Note4: 32 19 WF_IN
C NC1 WF_IN WF_IN [6] C
C7719
C7703 4.7uF;10%;10V;0603 1.0UF;20%;6.3V;0201
R7712 0;0.5A;0201
WF_QP [56] AVDD18_WBT
C7704 100pF;5%;50V;0201 33 18
AVDD33_WBT WF_QP WF_QP [6]

34 17 WF_QN
WF_RF_5G WF_QN WF_QN [6]

R7768 0;1A;0402
BT_IP [56] AVDD33_WBT VCN33_PMU [10]
35 16
WF_AUX_5G Note2: BT_IP BT_IP [6]
[56] FM_AVDD28

C7707 0.01uF;20%;25V;0201 36
AVDD28_FM
MT6631N/A BT_IN
15 BT_IN
BT_IN [6]
Note1:

L7705 L0201_NC

37 Note3: 14 BT_QP
[25] FM_ANT_N FM_LANT_N BT_QP BT_QP [6]

L7709

[25] RF_FM_ANT_WCN
82nH;5%;0201
FM_LANT_P 38
FM_LANT_P MT6631N BT_QN
13 BT_QN
BT_QN [6]

L7704 GPS_I
[58] RF_GPS_RX_RFIN 39 12
L0201_NC GPS_RFIN GPS_IP GPS_I [6]

40 11
[56] AVDD18_GPS AVDD18_GPS GPS_IN

AVDD28_FSOURCE

CONN_TOP_DATA
C7711

CONN_TOP_CLK
CONN_HRST_B
4700pF;20%;6.3V;0201 41
DVSS

GPS_QN
WB_PTA

GPS_QP
XO_IN
CEXT

NC2
1

10
MT6631

MT6631_CEXT
C7714

[6] CONN_HRST_B GPS_Q

100pF;5%;50V;0201 GPS_Q [6]
[6] CONN_TOP_DATA
B [6] CONN_TOP_CLK RF_MT6631_XO_IN B

[6] CONN_WB_PTA C7713

R7701 0;0.5A;0201
1.0UF;20%;6.3V;0201 PMIC_CLK_WCN [13]

R7702 0;0.5A;0201
XIN_WBG [6]

A Note1: A

Note2:

Note3:

Title REV: V10

Note4:
Page Name = 77_WCN_MT6631
DOCUMENT NO.: Size
Design Name = 98870_1_11_201906141113 D

DEPARTMENT: DEPARTMENT = WINGTECH-SZDESIGNER: DESIGNER = LIUFENGLEI

Date: Page Modify Date = Friday, June 14, 2019 Sheet 56 of 65

5 4 3 2 1
 5 4 3 2 1

D D

WIFI GPS ANT

R7801 Note1:
J7801

AT12-110001-04
C0201_NC

J7802
FL7810 DP1608-V1524CAT F6HG2G441EG65 U7801
1
L7801 C7801 L7802 R7803 R7804
2 RF_WBG_TRX_ANT RF_WBG_TRX_ANT_MATCH RF_WBG_TRX_RFSWITCH_OUT
2 1 RF_WBG_TRX_RFSWITCH_IN RF_WBG_TRX_DIP_OUT
5 1 RF_WB_TRX_DIP_IN RF_WB_TRX_SAW_OUT
4 1 RF_WB_TRX_SAW_IN
OUT IN COMMON H_PORT UNBL2 UNBL1 RF_WB_TRX_ANT [56]
1.0NH;0.1nH;0201 1.0NH;0.1nH;0201

GND2
GND1

GND3

GND2

GND1
33pF;5%;50V;0201 3.9pF;0.05pF;50V;0201 33pF;5%;50V;0201
L7804 L7809 L7805 L7806

GND1
GND2
GND3
C7802 C7803 3 RF_GPS_RX_DIP_OUT [58]
C7804 L_PORT L7807
L7808
C0201_NC C0201_NC 818004112 6.8NH;3%;0201
J7805 C0201_NC L0201_NC

4
3

2
2
4
6
AT12-110001-04
L0201_NC L0201_NC L0201_NC 6.8NH;3%;0201

C C

B B

A Note1:
A

Title REV: V10

Reserved
DOCUMENT NO.: Design Name Size D

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 57 of 65

5 4 3 2 1
 5 4 3 2 1

D D

R7903 R0201_NC RF_GPS_RX_POST_SAW_COMM R7904 R0201_NC

Note1: Note1:
U7901 U7903 SAFFB1G56KB0F0A RF_GPS_ATT

RF_GPS_RX_LNA_OUTR7902 0;0.5A;0201 RF_GPS_RX_POST_SAW_IN RF_GPS_RX_POST_SAW_OUT

1 6 1 4 R7905 0;0.5A;0201 R7901 0;0.5A;0201 RF_GPS_RX_RFIN [56]
GND1 RFOUT UNBL1 UNBL2
U7902 SAFFB1G56KB0F0A

GND1

GND2

GND3
2 5
C7902 L7902 GND2 EN C7903 C7904
C7909 C7910 R0201_NC R0201_NC
[57] RF_GPS_RX_DIP_OUT C7901 18pF;5%;50V;0201 RF_GPS_RX_SAW_IN 4 1 RF_GPS_RX_SAW_OUT RF_GPS_RX_SAW_MATCH RF_GPS_RX_LNA_IN 3 4
UNBL2 UNBL1 RFIN VCC R0201_NC R0201_NC

5
GPS_LNA_EN
9.1NH;3%;0201

GND3

GND2

GND1
18pF;5%;50V;0201
AW5005DNRZ

GPS_LNA_VCC
C7906
L7903 C7905

2
C0201_NC L7904
L0201_NC L0201_NC [10,56] VCN28_PMU L7901
GPIO_GPS_LNA_EN [6]
RF_GPS_NOTCH 100nH;5%;0201
100nH;5%;0201

C7911 C7907 C7908

C C0201_NC
0.01uF;20%;25V;0201 0.01uF;20%;25V;0201
C

B B

A Note1:
A

Title REV: V10

Reserved
DOCUMENT NO.: Design Name Size D

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 58 of 65

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Title Reserved REV: V10

DOCUMENT NO.: Design Name Size A1

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 59 of 65

 5 4 3 2 1

D D

C C

B B

A A

Title Reserved REV: V10

DOCUMENT NO.: Design Name Size A1

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 60 of 65

 5 4 3 2 1

4 4

3 3

2 2

1 1

Title REV: V10

10_BB_ POWER_PDN
DOCUMENT NO.: Design Name Size D

DEPARTMENT: WINGTECH-SZ DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 61 of 65

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Title Reserved REV: V10

DOCUMENT NO.: Design Name Size A1

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 62 of 65

 5 4 3 2 1

D [48] ANT_SAR_DIV
1K;5%;0201 D
R8492
C8443
C0201_NC

R8457 560;5%;0201
[63] ANT_SAR_DIV_SEM

[34] LMB_ANT_SAR_PRI

C8444
C0201_NC

R8491 560;5%;0201
[63] LMB_ANT_SAR_PRI_SEM SAR_NIRQ_ABO [63]
R8478
[34] LMB_ANT_SAR_REF C8439
1K;5%;0201
C8445 C0201_NC
R8459
C0201_NC
U8401
1K;5%;0201
R8488 SAR_IC_PIN10 10 1 SAR_IC_PIN1
CS3/DSDA/P10 CS4/DSCL/P11
[63] LMB_ANT_SAR_REF_SEM SAR_IC_PIN9 9 2 R8486 R0201_NC
560;5%;0201 CS1/P03 INT0/P12 [63] SAR_NIRQ_SEM SAR_INT [6]
SAR_IC_PIN8 8 [63] SAR_NIRQ_ABO R8487 0;0.5A;0201
R8479 1K;5%;0201 3
[34] HB_ANT_SAR_PRI CS0/P02 VSS R8431 2.2K;5%;0201 VIO18_PMU [4,5,6,8,10,12,15,17,19,21,23,25,26,28,29,30,31,33,34,37,40,41,46,49]
C8446 SAR_IC_PIN7 7 4
C0201_NC CS7/P01 VDDEXT
SAR_IC_PIN4 R8477 0;0.5A;0201
6 5 VIO28_PMU [10,28,30,63]
R8489 SCL/P14 SDA/P13
[63] HB_ANT_SAR_PRI_SEM RF-A96T346DFP
560;5%;0201 C8403 C8404
1.0uF;10%;6.3V;0402
R8480 1K;5%;0201
[48] DIV_ANT_SAR_REF 0.1uF;20%;6.3V;0201
C8447
C0201_NC

R8490
[63] DIV_ANT_SAR_REF_SEM
560;5%;0201

SAR_I2C_SDA_ABOV R8495
R8494 SDA3 [6,23,63]
[6,23,63] SCL3 SAR_I2C_SCL_ABOV
0;0.5A;0201
0;0.5A;0201
C8436 C8438
C0201_NC C0201_NC

C C

R0201_NC
SAR_I2C_SCL_SEM SCL3 [6,23,63]
R8493

C8437
C0201_NC

[63] SAR_NIRQ_SEM
R8433
C8440 SDA3 [6,23,63]

B C0201_NC
U8402
C8430
0;0.5A;0201
B
10 1
NIRQ SCL C0201_NC
9 2 SAR_I2C_SDA_SEM
[63] DIV_ANT_SAR_REF_SEM CSIO4 SDA
8 3
[63] HB_ANT_SAR_PRI_SEM CSIO3 CSIO2 ANT_SAR_DIV_SEM [63]
7 4 R8496 0;0.5A;0201
[63] LMB_ANT_SAR_REF_SEM CSIO0 VDD VIO28_PMU [10,28,30,63]
6 5
[63] LMB_ANT_SAR_PRI_SEM CSIO1 GND C8442
C8441
RF-SX9331_1 0.1uF;20%;6.3V;0201 1.0uF;10%;6.3V;0402

A A

Title Reserved REV: V10

DOCUMENT NO.: Design Name Size A1

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 63 of 65

 5 4 3 2 1

D D

C C

B B

A A

Title Reserved REV: V10

DOCUMENT NO.: Design Name Size A1

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 64 of 65

 5 4 3 2 1

D D

C C

B B

A A

Title Reserved REV: V10

DOCUMENT NO.: Design Name Size A1

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Friday, June 14, 2019 Sheet 65 of 65