Module III

TIMERS,SERIAL COMMUNICATION
• 3.1.0 To understand the working of timers
• 3.1.1 To explain the timers in 8051
• 3.1.2 To distinguish between timer function and counter function in
8051
• 3.1.3 To explain TMOD and TCON special function registers
• 3.1.4 To explain different modes of operation of timers
• 3.1.5 To write simple delay programs using timer
3.1.1 To explain the timers in 8051

• The 8051 has two timers, Timer 0 and Timer 1. They can be used as
timers or as event counters. Both Timer 0 and Timer 1 are 16-bit
wide. Since the 8051 follows an 8-bit architecture, each 16 bit is
accessed as two separate registers of low-byte and high-byte.
• It can create a delay or an interval of time, then we call it an interval
timer
• It can count the frequency of external signal- called as event counter
• The timer uses clock frequency of the chip and counter uses external
frequency for its operation
Timer 0 Register
• The 16-bit register of Timer 0 is accessed as low- and high-byte. The
low-byte register is called TL0 (Timer 0 low byte) and the high-byte
register is called TH0 (Timer 0 high byte). These registers can be
accessed like any other register. For example, the instruction MOV
TL0, #4H moves the value into the low-byte of Timer #0.
Timer 1 Register

• The 16-bit register of Timer 1 is accessed as low- and high-byte. The

low-byte register is called TL1 (Timer 1 low byte) and the high-byte
register is called TH1 (Timer 1 high byte). These registers can be
accessed like any other register. For example, the instruction MOV
TL1, #4H moves the value into the low-byte of Timer 1.
TMOD (Timer Mode) Register
• TMOD(Timer Mode) is an SFR. The address of this register is 89H. This is not bit-
addressable.
• Both Timer 0 and Timer 1 use the same register to set the various timer
operation modes. It is an 8-bit register in which the lower 4 bits are set aside for
Timer 0 and the upper four bits for Timer 1.

Gate − When set, the timer only runs while INT(0,1) is high.
C/T − Counter/Timer select bit. Cleared for timer operation
M1 − Mode bit 1.
M0 − Mode bit 0.
• GATE:
1 = Enable Timer/Counter only when the INT0/INT1 pin is high and TR0/TR1 is set.
0 = Enable Timer/Counter when TR0/TR1 is set.
• C/T (CLOCK / TIMER):Timer or counter selected
1 = Use as Counter (input from Tx input pin)
0 = Use as Timer( input from internal system clock)
• M1/M0 :Timer/Counter mode select bit
M1 M0 Mode Operation
13-bit timer/counter, 8-bit of THx & 5-bit of
0 0 0 (13-bit timer mode)
TLx
16-bit timer/counter, THx cascaded with
0 1 1 (16-bit timer mode)
TLx
8-bit timer/counter (auto-reload mode),
1 0 2 (8-bit auto-reload mode) TLx reload with the value held by THx
each time TLx overflow
Split the 16-bit timer into two 8-bit timers
1 1 3 (split timer mode)
i.e. THx and TLx like two 8-bit timer
TCON REGISTER
• TCON is a bit addressable SFR. Out of the 8 bits, the lower 4 bits are concerned
with external interrupts. The upper 4 bits deals with Timers.
• TF1 and TF0 are timer flags that indicate overflow condition in timers 1 and timer
0 respectively. When an overflow condition is reached, the value is changed to 1
from 0. TR0 and TR1 are used to start timers 0 and 1. When a value 1 loads into
these registers, the timers start counting from the values which are inside them.

Bit 7 - TF1: Timer1 Overflow Flag

1 = Timer1 overflow occurred (i.e. Timer1 goes to its max and roll over back to zero).
0 = Timer1 overflow not occurred.
It is cleared through software. In the Timer1 overflow interrupt service routine, this bit will get cleared
automatically while exiting from ISR.
Bit 6 - TR1: Timer1 Run Control Bit
1 = Timer1 start. 0 = Timer1 stop.
It is set and cleared by software.
Bit 5 – TF0: Timer0 Overflow Flag Bit 4 – TR0: Timer0 Run Control Bit
• Bit 3 - IE1: External Interrupt1 Edge Flag
• 1 = External interrupt1 occurred.
• 0 = External interrupt1 Processed. It is set and cleared by
hardware.
• Bit 2 - IT1: External Interrupt1 Trigger Type Select Bit
• 1 = Interrupt occurs on falling edge at INT1 pin.
• 0 = Interrupt occur on a low level at the INT1 pin.
• Bit 1 – IE0: External Interrupt0 Edge Flag
• Bit 0 – IT0: External Interrupt0 Trigger Type Select Bit
Timer/Counter control logic
Different modes of operation of timers
• The timer may operate in any one of four modes that are
determined by the mode bits M1 and M0 in the TMOD register
• Mode 0 of Timer/Counter

• The Mode 0 operation is the 8-bit timer or counter with a 5-bit pre-
scaler. So it is a 13-bit timer/counter. It uses 5 bits of TL0 or TL1 and
all of the 8-bits of TH0 or TH1.It can count up from 0000 to 1FFFH.
Mode 1
In this mode, both the timers act as 16-bit timers, enabling them to
count from 0000 to FFFFH.Most programmers use this mode due to
its high counting capacity. One issue of this mode is that the start
value has to be put in the timer registers after each cycle increasing
software overhead.
Mode 2:
• This mode comes with an auto-reload function, which helps deal
with the software overhead issue in mode 2. In this configuration, the
timer acts like an 8 bit counter and uses the lower bit (TL0/TL1) as the
actual counter. As it is an 8 bit counter, it counts from 00 to FFH. The
higher bit (TH1/TH0) acts as a storage element that stores and inputs
the value to the lower bits when they reset.
Mode 3
• Mode 3 is different for Timer0 and Timer1. When the Timer0 is
working in mode 3, the TL0 will be used as an 8-bit timer/counter. It
will be controlled by the standard Timer0 control bits, T0
and INT0 inputs. The TH0 is used as an 8-bit timer but not the
counter. This is controlled by Timer1 Control bit TR1. When the TH0
overflows from FFH to 00H, then TF1 is set to 1. In the following
diagram, we can Timer0 in Mode 3.
Step in programming an interval timer
• 1.write the mod control word in the TMOD register
• 2.Write the count in the timer register
• 3.Start the timer
• 4.Wait for overflow and check the status of the timer flag
• 5.Stop the timer
• 6.If this sequence is to be repeated ,reload the timer register,clear the
timer flag and go to step 3
Write simple delay programs using timer
• Write the mode control words for the following cases :
• 1.Timer 1 in mode 1
• 2.Timer 0 in mode 2
• 3.Timer 1 in mode 2 and timer 0 in mode 1
• Solution : For all these cases, the GATE and C/T bits are to be made 0.
• (i) Timer 1 in mode 1 : Timer 1 uses the upper nibble of the TMOD register,
the lower nibble bits may be made 0. The TMOD value is to be : 0001 0000,
i.e., 10H
• (ii) Timer 0 in mode 2 : Timer 0 uses only the lower nibble. The TMOD value
1s 0000 0010, i.e., 02
• (iii) Timer 1 in mode 2 and timer 0 in mode 1 : Both the upper and lower
nibbles of TMOD must be configured. TMOD is 0010 0001, i.e., 21H.
Use timer 1 in mode 1 to create a delay .Load the number 8942H in the
corresponding timer register .Write a program for this, and also calculate the
amount of delay obtained.
solution ¢
ORG 0
MOV TMOD, #10H ;load TMOD word
MOV TL1. #42H ;load lower byte of count
MOV TH1, #89H ;load upper byte of count
SETB TRI ;start the timer
CHECK : JNB TF1, CHECK ;check if TF1 is set
CLR TR1 ;stop the timer
END
This program loads the mode word, and the count value in the respective
registers, i.e., TH1 and TL1. Then the timer is started. Next, the processor is
in put in a loop waiting for the timer flag to be set. When TF1 flag is set, the
timer is stopped by clearing TR1.
• Delay Calculation :
• Let's calculate the amount of this delay. The clock we use has the
frequency of 12 MHz, and thus the period of one machine cycle is 1
usec. The timer register has the initial value of 8042H. When the
timer starts, this number increases every machine cycle to 8043, 8044
.... FFFFH. The number of machine cycles expended in reaching the
maximum count is FFFFH - 8042H = 7FBDH = 32,701 (in decimal). To
roll to 0 from the maximum count, takes one more machine cycle,
and hence the total number of machine cycles = 32,702 which
corresponds to a delay of 32,702 usecs = 32.702 msecs.
Using delay in program 1Generate a square wave at pin 2.4
• ORG 0
• MOV TMOD, #10H ;mode 1 timer 1
BACK : MOV TL1, #42H ;load low byte of count
MOV TH1, #80H ;load high byte of count
SETB TR1 ;start the timer
CPL P2.4 ;complement P2.4
ACALL DELAY ;call delay procedure
SJMP BACK ;jump to BACK
DELAY : JNB TF1, DELAY ;jump to delay if TF1! = 1
CLR TR1 ;stop the timer
CLR TF1 ;clear the timer flag
RET :return to main program
END
This program generates a square wave on pin P2.4. The pin is complemented for every
delay of 32MS