30-10-2018

MEL G611 :
IC FABRICATION TECHNOLOGY
Section X: Annealing
25 Oct (Thu) & 30 Oct (Tue) 2018
BITS Pilani
Hyderabad Campus
Sanket Goel, EEE

Sec IX, L 27 - 29: Ion Implantation

• 18 (Thu), 20 (Sat) & 23 (Tue) Oct 2018

• Learning Objectives
o To learn ion implantation technology for precise
doping into the silicon.

• Topics covered –
o Implant in Si
o High-Energy Implant
o Ultralow Energy Implant
o Ion beam Heating
o Measurement methods

MEL G611 : IC FABRICATION TECHNOLOGY 2 BITS Pilani, Hyderabad Campus

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Sec X, L 30 & 31: Annealing

• 25 Oct (Thu) & 30 Oct (Tue) 2018

• Learning Objectives
o To understand Annealing of damages and masking
during implantation

• Topics to be covered
o How annealing helps to recover damages and
thickness of the masking layer improves the masking
efficiency

MEL G611 : IC FABRICATION TECHNOLOGY 3 BITS Pilani, Hyderabad Campus

Basic VLSI Fabrication Steps

MEL G611 : IC FABRICATION TECHNOLOGY 4 BITS Pilani, Hyderabad Campus

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Impact of Implantation
• A lot of damage in the implanted region
• Parameters that get most affected
o Conductivity  very low (impurity not on the proper sites)
o Mobility  very low (highly disordered damaged region)
o Lifetime
• Aim  to get back the required levels these , µ & 
• How  wafer must be subjected to high temperature
treatment
• How much temperature and for how long?
• From the ion implantation profile, from RP we know where
most of the ions are coming to a rest. That is where the peak
concentration lies.

MEL G611 : IC FABRICATION TECHNOLOGY 5 BITS Pilani, Hyderabad Campus

Annealing of Si
• Process of repairing implant damage (“healing” the surface)
• Putting dopant atoms in substitutional sites where they will
be electrically active
• Annealing objectives
o Healing, recrystallization (500 - 600 oC)
o Renew electrical activity (600 - 900 oC)
• Region of maximum damage?
o By nuclear stopping mechanism  ion is imparting its energy to the
lattice atoms.
o Lattice atoms get displaced, and cause secondary displacement of
other lattice atoms.
• Annealing time and temperature  depend upon the dose;
lower the dose, simpler will be the annealing
• Orientation  (100) will anneal 10 times faster than (111)
MEL G611 : IC FABRICATION TECHNOLOGY 6 BITS Pilani, Hyderabad Campus

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Annealing Classes
• Divided into two classes (based on type of material) they are
o Pre-amorphised & No pre-amorphised
• Pre-amorphised

 400oC 600oC

Recovery Partial (clusters Recrystallization

disappear) takes place

Activation 20% to 30% 50% to 90%

Recovery life time extreme low low

• T  950oC  Fast recovery

MEL G611 : IC FABRICATION TECHNOLOGY 7 BITS Pilani, Hyderabad Campus

Annealing Classes
No Pre-amorphised
• Low dose, light ion implantation: all the parameters
(conductivity, mobility, as well as life time) can be fully
recovered between 800oC - 950oC
• Heavy ion implantation, low dose: all the parameters can
be recovered by 1000oC
• It is difficult to get full activation for high dose heavy ion
implantation.
• If the life time recovery is not very important than pre
amorphisation is better than not pre amorphisation
material.
• @ 600oC we get 90% activation

MEL G611 : IC FABRICATION TECHNOLOGY 8 BITS Pilani, Hyderabad Campus

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Practical case: P, & As in Si

• Phosphorus  relatively heavy ion, so it loses its
energy primarily by the nuclear stopping mechanism
o Projected range proportional to incident energy
o lot of energy to put phosphorus deep into the silicon
o Rp=1.1 μm/Mev
o As the temperature increases (5250C) the carrier
activation increases till a point it >80% of activation

• Arsenic  behaves very similar to that of phosphorus.

o Rp=0.58 μm/M ev.

MEL G611 : IC FABRICATION TECHNOLOGY 9 BITS Pilani, Hyderabad Campus

Practical case: B in Si
• Light ion, Rp=3.1 μm/M ev.
• Incident energy range in 10 to 100
keV
• Exhibits anomalous annealing
characteristics
• Region I: Point defect disorder is
annealed out with rapid increase in
activation
• Region II: Extended dislocation
structure due to relative strain.
Reverse annealing
• Region III: Boron precipitates
dissolve into Si and become active

MEL G611 : IC FABRICATION TECHNOLOGY 10 BITS Pilani, Hyderabad Campus

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Masking in ion implantation

• Ion implantation is a room temperature process
• Larger choice of mask material
• No need to use SiO2 always (like diffusion)
• Ion implantation can use photoresist as the mask
• Silicon and mask layer generate energetic ions when ion
beam is incident on semiconductor and these energy ions
will have Gaussian principle.

o d  masking layer thickness.

o If d is large  less impurity is put inside silicon
o If d is less  large amount of impurity is put inside silicon

MEL G611 : IC FABRICATION TECHNOLOGY 11 BITS Pilani, Hyderabad Campus

Evaluation of doped layer

• Junction depth
o Measured by lapping and straining
o Cylindrical groove technique
o Interference fringe method
 Lapped sample  Provide optical flat and subject to
monochromatic radiation by sodium vapour lamp.
 Dull fringes appear in p region and we can count it.
 Junction depth= # of dull fringes * light wavelength

• Doping distribution
o SIMS (Secondary Ion Mass Spectroscopy)
o Won’t tell us whether this impurity is electronically active
or not, whether it is sitting in the substitutional site or it is
just sitting anywhere inside the semiconductor
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Shallow Junction Challenge

• Need for shallow junction (20-50 nm) means
o Diffusion lengths
 Small
 Well controlled
• Annealing at high temperature required for dopant activation
and low defect density
• To achieve short diffusion length, we need
o Fast ramp to temperature
o Well controlled temperature (time)
o Short bake time

• Cant do it in furnace, then how?

MEL G611 : IC FABRICATION TECHNOLOGY 13 BITS Pilani, Hyderabad Campus

Rapid Thermal Processing

• Bank of lamps rapidly heats a single wafer suspended on low
thermal mass pins

• Heat the wafer optically

o Front-side and/or
backside
• 150oC – 1300oC
• Ramp rates 200oC/s
possible
• Sub-seconds anneals possible
o Wide range of time / temperature options available
• Fast cooling required
• Non-equilibrium process

MEL G611 : IC FABRICATION TECHNOLOGY 14 BITS Pilani, Hyderabad Campus

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Thermal Transfer Mechanisms

• Temperature uniformity difficult to achieve
• Optical pyrometry used to measure wafer temperature
• Radiative: Stefan-Boltzman equation

• Conduction • k  thermal conductivity of material

• Convection • h effective heat transfer coefficient
• T  temperature of the gas far from
the wafer

• Radiative dominates at high

temperatures

MEL G611 : IC FABRICATION TECHNOLOGY 15 BITS Pilani, Hyderabad Campus

Heating options

The emissivity of silicon as a

function of wavelength with
temperature as a parameter

Backside heating Front-side heating

MEL G611 : IC FABRICATION TECHNOLOGY 16 BITS Pilani, Hyderabad Campus

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RTP Use and Process

• Rapid Thermal Annealing (RTA) : Shallow Junctions
• Rapid Thermal Oxidation (RTO): Dry O2 for thin oxides
• Rapid thermal Nitridation (RTN)
• Silicide / Salicide (self-aligned silicide): TiS2 / NiSi / CoSi2 etc
• High-k gate dielectric densification

(Dt)

MEL G611 : IC FABRICATION TECHNOLOGY 17 BITS Pilani, Hyderabad Campus

Problem

MEL G611 : IC FABRICATION TECHNOLOGY 18 BITS Pilani, Hyderabad Campus

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Problem
Planck’s radiation law: For a black radiator the intensity of
radiation Rλ at a particular wavelength λ is given by
C1 = 2hc2
C2 = hc/k

What is the maximum wavelength at which the maximum energy

is emitted by a blackbody at temperature T K?

MEL G611 : IC FABRICATION TECHNOLOGY 19 BITS Pilani, Hyderabad Campus

Problem
Consider the sun to act as a blackbody. The surface temperature
is 6000oC, and it has a radius of 6.95x108 m. Find the peak
wavelength and the total power radiated.

MEL G611 : IC FABRICATION TECHNOLOGY 20 BITS Pilani, Hyderabad Campus

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Problem
The major source of uncertainty in pyrometry is an uncertainty in
the emissivity. If the wafer temperature is 10000C, what
wavelength is most desirable to minimize the effect of this
uncertainty?

• If the pyrometer is operating at 5 µm, a 5% uncertainty in the emissivity produces a

220C error in the temperature.
• If a pyrometer operating in the 0.94–0.96 µm range produces only a 40C temperature
error for the same 5% error in emissivity.

MEL G611 : IC FABRICATION TECHNOLOGY 21 BITS Pilani, Hyderabad Campus

Sec X, L 29 & 30: Annealing

• 27 (Thu), 29 (Sat) Sept; 4 (Thu), 6 (Sat) Oct 2018

• Learning Objectives
o To explore the basic process of dopant diffusion
o Methods to accurately predict dopant profiles.

• Topics to be covered –
o Diffusion time dependent process
o Diffusion independent process

MEL G611 : IC FABRICATION TECHNOLOGY 22 BITS Pilani, Hyderabad Campus

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Sec IX, L 31 & 32: Epitaxy

• 1 Nov (Thu) & 3 Nov (Sat) 2018

• Learning Objectives
o To understand epitaxy and its use in IC fabrication
process

• Topics to be covered –
o Vapor phase epitaxy
o Molecular Beam Epitaxy
o SoI
o Epitaxial evaluation

MEL G611 : IC FABRICATION TECHNOLOGY 23 BITS Pilani, Hyderabad Campus

Rapid Thermal Annealing (RTA)

• Wafers quickly heated to >1000°C
• Colling is done slowly to prevent
dislocations and wafer breakage
due to thermal shock.
• Attained by high intensity lamps

• Transparent walls remain relatively cool during this short time

• Wafer temperature is determined with an optical pyrometer
• Heats a single wafer at a time using either lamp based heating,
a hot chuck, or a hot plate that a wafer is brought near.
• Unlike furnace anneals they are short in duration, processing
each wafer in several minutes.

MEL G611 : IC FABRICATION TECHNOLOGY 24 BITS Pilani, Hyderabad Campus

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