LOGIC DESIGN AND SWITCHING THEORY(CE-204) 2020-CE-096

Roll No. 2020-CE-096 Section C Name ABDUL HASEEB

Department: Computer Engineering Program: Bachelor of Science

Assignment 2
CE-204 T Logic Design and Switching Theory

Announced date: 26th April 2021 Due Date: 2nd May 2021 Total Marks = 2

Marks Obtained =
Teacher Name: Mohsin Vohra

(CLO_2: Cognitive Level C3 e.g. Applying) (PLO_2: Problem Analysis)

Q1. Constructs the logic symbol for the 74151 eight, line multiplexer.
Logic Symbol of 74151 eight, line multiplexer:

LOGIC SYMBOL OF 74151 Multiplexer:

Vcc = Pin 16
GND = Pin 8

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LOGIC DESIGN AND SWITCHING THEORY(CE-204) 2020-CE-096

Q2. Shows the working of 7-segment Common Cathode and Common Anode with the
help of neat and clean diagrams.
7-segment Display Common Cathode:
In the common cathode , all the cathode connections of the LED segments are joined
together to logic “0” or ground. The individual segments are illuminated by application of
a “HIGH”, or logic “1” signal via a current limiting resistor to forward bias the individual
Anode terminals.

Common Cathode display when B & C is set to HIGH:

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LOGIC DESIGN AND SWITCHING THEORY(CE-204) 2020-CE-096

7-segment Display Common Anode:

In the common anode display, all the anode connections of the LED segments are joined
together to logic “1”. The individual segments are illuminated by applying a ground, logic
“0” or “LOW” signal via a suitable current limiting resistor to the Cathode of the
particular segment (A-G).
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Common Anode display when B & C is set to LOW:

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LOGIC DESIGN AND SWITCHING THEORY(CE-204) 2020-CE-096

Q3. Relate how a decoder can be used as a Demultiplexer? Explain with the help of
suitable diagram.
Decoder Use as a Demultiplexer:
A decoder with an enable input can function as a Demultiplexer. A demultiplexer is a circuit
that receives information on a single line and transmits this information on one of 2n
possible output lines. Demultiplexer circuits can be connected together to form a large
decoder circuit.
Diagram:

When w=0, the top decoder is enabled and the other is disabled. Bottom decoder outputs are
all 0’s & top outputs generate minterms 0000 to 0111, When w=1 bottom decoder outputs
generate minterms
1000 to 1111,
Enable lines are a convenient feature for connecting two or more IC packages for the purpose
of expanding the digital function into a similar function with more inputs and outputs.

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