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Bus Arbiter
Bus Arbiter
Bus Arbiter
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Entity: Generic arbiter
--
-- Description:
-- -------------------------------------
-- This module implements a generic arbiter. It currently supports the
-- following arbitration strategies:
--
-- * Round Robin (RR)
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design,
Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity bus_Arbiter is
generic (
STRATEGY : string
:= "RR"; -- RR,
LOT
PORTS :
positive := 1;
WEIGHTS :
T_INTVEC := (0 => 1);
OUTPUT_REG : boolean
:= TRUE
);
port (
Clock : in
std_logic;
Reset : in
std_logic;
Arbitrate : in
std_logic;
Request_Vector : in
std_logic_vector(PORTS - 1 downto 0);
begin
begin
-- Lottery Arbiter
--
===================================================================================
=======================================================================
-- genLOT : if (STRATEGY = "RR") generate
-- begin
--
-- end generate;
end architecture;