Digital Electronics LAB MANUAL

INSTITUTE OF TECHNOLOGY & MANAGEMENT, VADODARA
PRACTICAL NO. 1
AIM:
Getting familiar with various digital integrated circuits of different logic families. Study of data sheet of
these circuits and see how to test these circuits using Digital IC Tester.
REQUIREMENT:
 Digital IC Tester
THEORY:
A logic family may refer to one of two related concepts. A logic family of monolithic digital integrated
circuit devices is a group of electronic logic gates constructed using one of several different designs, usually
with compatible logic levels and power supply characteristics within a family. Many logic families were
produced as individual components, each containing one or a few related basic logical functions, which could
be used as "building-blocks" to create systems or as so-called "glue" to interconnect more complex integrated
circuits. A "logic family" may also refer to a set of techniques used to implement logic
within VLSI integrated circuits such as central processors, memories, or other complex functions. Some such
logic families use static techniques to minimize design complexity. Other such logic families, such
as domino logic, use clocked dynamic techniques to minimize size, power consumption, and delay.
The list of packaged building-block logic families can be divided into categories, listed here in roughly
chronological order of introduction, along with their usual abbreviations:
 Resistor–transistor logic (RTL)
 Direct-coupled transistor logic (DCTL)
 Resistor–capacitor–transistor logic (RCTL)
 Diode–transistor logic (DTL)
 Complemented transistor diode logic (CTDL)
 High-threshold logic (HTL)
 Emitter-coupled logic (ECL)
 Positive emitter-coupled logic (PECL)
 Low-voltage positive emitter-coupled logic (LVPECL)
 Gunning transceiver logic (GTL)
 Transistor–transistor logic (TTL)
 P-type metal–oxide–semiconductor logic (PMOS)
BASIC-ELECTRONICS LAB MANUAL Page 1

 N-type metal–oxide–semiconductor logic (NMOS)

 Depletion-load NMOS logic
 High-density nMOS (HMOS)
 Complementary metal–oxide–semiconductor logic (CMOS)
 Bipolar complementary metal–oxide–semiconductor logic (BiCMOS)
 Integrated injection logic (I2L)
Procedure:
1. Mount any digital IC on slots given on kit.
2. Turn on the digital IC tester.
3. Enter IC number using keypad that you want to check.
4. Press Search button if you don’t know IC no. and then check for Pass / Fail.
5. Press search again to find similar ICs of that family.
CONCLUSION:

PRACTICAL NO. 2
AIM:
Digital IC Testers and Logic State Analyzer as well as digital pattern generators should be demonstrated to
the students.
REQUIREMENT:
 Digital IC Tester
THEORY:
VPL-DICT Digital IC Tester
VPL-DICT is a Hand-Held version, designed as a powerful tool for manufacturers, servicing engineers, R&D
personals to test a wide range of Digital IC's.

FEATURES
 Tests most of the 6 to 40 pin ICs in DIP package. The list includes 74/54, 40/45, 93/96 series ICs,
EPROMs, RAMs, peripheral ICs, microprocessor (8088/8085/Z80/6502), miscellaneous digital ICs.
 Automatic testing of variety of ICs.
 Potential free 40 pin universal ZIF socket.
 Digital Display to show IC number, PASS & FAIL Status, Operations display.
 It has 16/12 keys for its operation.
 Battery & Mains operation
 Handheld size
 Audio alarm to user whenever it is required.
TEST LIBRARY
CMOS ICs (40 Series): 00 01 02 06 07 08 09 10 11 12 13 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

32 33 34 35 38 40 41 42 473 44 47 48 49 50 51 52 53 54 55 56 60 61 63 66 67 68 69 70 71 72 73 75 76 77
78 81 82 85 86 89 93 94 95 96 97 98 99 101 102 103 106 107 109 110 147 160 161 162 163 174 175 192
193 194 195

CMOS ICs (MC140) : MC140
CMOS ICs (45 Series) : 01 02 03 06 08 10 11 12 13 14 15 16 18 19 20 29 30 31 32 37 38 39 41 43 44 47 51

55 56 58 59 60 61 72 81 82 84 85 99
CMOS MC : MC145
TTL 74/54 Series : 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

30 31 32 33 34 35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 53 54 55 58 60 63 64 65 68 69 70 72 73 74
75 76 77 78 80 82 83 85 86 89 90 91 92 93 94 95 96 100 104 105 107 109 110 111 112 113 114 116 121 122
123 125 126 128 131 132 133 134 135 136 137 138 139 140 141 142 145 147 148 150 151 152 153 154 155
156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 173 174 175 176 177 178 179 180 181 182
183 184 185 189 190 191 192 193 194 195 196 197 198 199 211 213 219 226 230 231 237 238 239 240 241
242 243 244 245 246 247 248 249 251 253 255 256 257 258 259 260 261 265 266 273 274 276 278 279 280
283 284 285 289 290 293 295 298 299 319 322 323 347 348 350 351 352 353 354 356 363 364 365 366 367
368 373 374 375 376 377 378 379 381 382 386 388 390 393 395 396 398 399 425 426 440 441 442 443 444
445 447 465 466 467 468 490 502 503 518 519 520 521 522 533 534 537 538 539 540 541 542 543 544 545
563 564 568 569 573 574 575 576 577 580 588 589 590 594 597 604 605 620 621 622 623 638 639 640 641
642 643 644 645 646 647 648 651 652 653 654 655 656 657 658 659 664 665 668 669 670 674 675 676 677
678 679 680 682 683 684 685 686 687 688 689 700 730 731 734 795 796 797 798 804 805 808 821 822 823
824 825 826 832 841 842 843 844 845 846 990 991 992 993 994 995 996
75/55 Series :
107 108 113 121 122 123 124 125 127 128 129 136 138 151 153 159 158 160 172 173 174 175 176 177 178
183 189 401 402 403 404 411 412 413 414 416 417 418 419 430 431 432 433 434 437 446 447 448 449 450
451 452 453 454 455 470 471 472 473 474 491 492 496 497 498
Microprocessor, EPROM, RAM and other digital ICs :

8255 8155 8156 8253 8254 8226 8031 8051 8052 8032 8035 8039 8048 8049 8259 8279 8751 8752 8749
2716 2732 2764 27128 27256 27512 2864 2817 2816 62256 2114 6116 6264.
CONCLUSION:

PRACTICAL NO. 3
AIM:
Configuring NAND and NOR logic gates as universal gates.
REQUIREMENT:
 Universal NAND and NOR Kit
 Cords
THEORY:
Universal Gates:
A universal gate is a gate which can implement any Boolean function without need to use any other gate
type. The NAND and NOR gates are universal gates. In practice, this is advantageous since NAND and NOR
gates are economical and easier to fabricate and are the basic gates used in all IC digital logic families. In
fact, an AND gate is typically implemented as a NAND gate followed by an Inverter. An OR gate is typically
implemented as a NOR gate followed by an inverter.
 Implementing an Inverter Using only NAND Gate

All NAND input pins connect to the input signal A gives an output A’.
 Implementing AND Using only NAND Gates

An AND gate can be replaced by NAND gates as shown in the figure (The AND is replaced by a NAND
gate with its output complemented by a NAND gate inverter).
 Implementing OR Using only NAND Gates

An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is replaced by a NAND
gate with all its inputs complemented by NAND gate inverters)
 Implementing an Inverter Using only NOR Gate

All NOR input pins connect to the input signal A gives an output A’.

 Implementing OR Using only NOR Gates

An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by a NOR gate with
its output complemented by a NOR gate inverter)
 Implementing AND Using only NOR Gates

An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is replaced by a NOR
gate with all its inputs complemented by NOR gate inverters)
Procedure:
1. Connect the trainer kit to ac power supply.

2. Connect the NAND & NOR gates for any of the logic functions to be realized.
3. Connect the inputs of first stage to logic sources and output of the last gate to logic indicator.
4. Apply various input combinations and observe output for each one.
5. Verify the truth table for each input/ output combination.
6. Repeat the process for all logic functions.
7. Switch off the ac power supply.
CONCLUSION:

PRACTICAL NO. 4
AIM:
Study and Configure of various digital circuits such as adder, subtractor, decoder,
encoder and code converters
REQUIREMENT:
 Trainer Kit
 D.C. Power Supply
 Patch-cords, etc.
THEORY:
A half adder adds two one-bit binary numbers A and B. It has two outputs, S and C (the value theoretically
carried on to the next addition); the final sum is 2C + S. The simplest half adder design, pictured on the right,
incorporates an XOR gate for S and an AND gate for C. Half adders cannot be used compositely, given their
incapacity for a carry-in bit

A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds
three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in
(in theory from a past addition). The circuit produces a two-bit output sum typically represented by the
signals Cout and S.

The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two
inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).
The full-subtractor is a combinational circuit which is used to perform subtraction of three bits. It has three
inputs, X (minuend) and Y (subtrahend) and Z (subtrahend) and two outputs D (difference) and B (borrow).

A Decoder is a combinational circuit that converts binary information from n input lines to a
maximum of 2n unique output lines.


An encoder is a digital circuit that performs the inverse of a decoder, the encoder has 2 n
(or less) input lines and n output lines ,the output lines generate the binary code corresponding
to the input value .
A D/A Converter is used when the binary output from a digital system is to be converted into its
equivalent analog voltage or current.
The binary output will be a sequence of 1′s and 0′s. Thus they ma be difficult to follow. But, a D/A
converter help the user to interpret easily.
Basically, a D/A converter have an op-amp. It can be classified into 2 types.

Digital to Analog Converter using Binary-Weighted Resistors

A D/A converter using binary-weighted resistors is shown in the figure below. In the circuit, the op-
amp is connected in the inverting mode. The op-amp can also be connected in the non-inverting mode. The
circuit diagram represents a 4-digit converter. Thus, the number of binary inputs is four.
We know that, a 4-bit converter will have 24 = 16 combinations of output. Thus, a corresponding 16
outputs of analog will also be present for the binary inputs.
Four switches from b0 to b3 are available to simulate the binary inputs: in practice, a 4-bit binary
counter such as a 7493 can also be used.
Working
The circuit is basically working as a current to voltage converter.
 b0 is closed
It will be connected directly to the +5V.
Thus, voltage across R = 5V
Current through R = 5V/10kohm = 0.5mA
Current through feedback resistor, Rf = 0.5mA (Since, Input bias current, IB is negligible)
Thus, output voltage = -(1kohm)*(0.5mA) = -0.5V
 b1 is closed, b0 is open
R/2 will be connected to the positive supply of the +5V.
Current through R will become twice the value of current (1mA) to flow through Rf.
hus, output voltage also doubles.
 b0 and b1 are closed
Current through Rf = 1.5mA
Output voltage = -(1kohm)*(1.5mA) = -1.5V
Thus, according to the position (ON/OFF) of the switches (bo-b3), the corresponding “binary-
weighted” currents will be obtained in the input resistor. The current through Rf will be the sum of these

currents. This overall current is then converted to its proportional output voltage. Naturally, the output will
be maximum if the switches (b0-b3) are closed
V0 = -Rf *([b0/R][b1/(R/2)][b2/(R/4)][b3/(R/8)]) – where each of the inputs b3, b2, b1, and b0 may
either be HIGH (+5V) or LOW (0V).
The graph with the analog outputs versus possible combinations of inputs is shown below.
Digital-to-Analog Converter Circuit - Binary-Weighted Resistors Method Graph

The output is a negative going staircase waveform with 15 steps of -).5V each. In practice, due to the
variations in the logic HIGH voltage levels, all the steps will not have the same size. The value of the
feedback resistor Rf changes the size of the steps. Thus, a desired size for a step can be obtained by
connecting the appropriate feedback resistor. The only condition to look out for is that the maximum output
voltage should not exceed the saturation levels of the op-amp. Metal-film resistors are more preferred for
obtaining accurate outputs.
Disadvantages
If the number of inputs (>4) or combinations (>16) is more, the binary-weighted resistors may not be
readily available. This is why; R and 2R method is more preferred as it requires only two sets of precision
resistance values.
Digital to Analog Converter with R and 2R Resistors

A D/A converter with R and 2R resistors is shown in the figure below. As in the binary-weighted
resistors method, the binary inputs are simulated by the switches (b0-b3), and the output is proportional to
the binary inputs. Binary inputs can be either in the HIGH (+5V) or LOW (0V) state. Let b3 be the most
significant bit and thus is connected to the +5V and all the other switchs are connected to the ground.

Digital to Analog Converter with R and 2R Resistors
Thus, according to Thevenin’s equivalent resistance, RTH,

RTH = [{[(2RII2R + R)} II2R] + R}II2R] + R = 2R = 20kOhms.
The resultant circuit is shown below.

Digital to Analog Converter with R and 2R Resistors - Resultant Circuit

Graph is given below.
Digital to Analog Converter with R and 2R Resistors - Graph
In the figure shown above, the negative input is at virtual ground, therefore the current through
RTH=0.
Current through 2R connected to +5V = 5V/20kohm = 0.25 mA
The current will be the same as that in Rf.

Vo = -(20kohm)*(0.25mA) = -5V
Output voltage equation is given below.

V0 = -Rf (b3/2R+b2/4R+b1/8R+b0/16R)

PRACTICAL NO. 5
AIM:
Verify Thevenin’s And Norton’s Theorems.
REQUIREMENT:
 Thevenin/Norton Application Trainer Kit
 AC/DC Voltage/Current Source
 Multimeters
 Patch-cords, etc.
THEORY:
Two powerful circuit analysis techniques are Thevenin's theorem and Norton's theorem. Both theories
convert a complex circuit to a simpler series or parallel equivalent circuit for easier analysis. Analysis
involves removing part of the circuit across two terminals to aid calculation, later combining the circuit with
the Thevenin or Norton equivalent circuit.
Thevenin's Theorem
The top left diagram represents the circuit for analysis at terminals A and B. The top right hand
circuit is the Thevenin equivalent circuit, a voltage source Vth with a series resistance, Rth. The bottom left
diagram is the same circuit driving a load. The load is NOT included in the thevenin equivalent circuit and
must be separated, this is why the terminals are marked A and B.

Value of VTH and RTH
To find the equivalent Thevenin resistance of the circuit. RTH the load is first removed and any circuit
voltages are short circuited. The resistance is then calculated. The Thevenin voltage is found by first
removing the circuit load and then working out the voltage across point A and B in the circuit.
An Example :
A demonstration of the thevenin technique to find current I1 in the diagram below:
First, the circuit to the right of points A and B is converted to a

Thevenin source and resistance. The components to the left, the 30v
battery and 10 ohm resistor are removed. The Thevenin voltage is then
the equivalent voltage across terminals A and B becomes:
40 * 10
VTH = = 13.3333
30

The circuit is now converted to find the Thevenin Resistance (seen looking into the circuit to the right
of points A and B). All voltage sources are short circuited and the equivalent Thevenin Resistance will be the
value of the 10 ohm resistor in parallel with the 20 ohm resistor.
20 * 10
RTH = 10||20= = 6.6667
(20+10)
Knowing both the equivalent Thevenin Voltage and
Thevenin Resistance, the value of current I1 can now be solved. I1
flows in series and from ohm's law will be the voltage difference
( 30 V source - VTH) divided by total resistance:
30 - VTH 30 - 13.3333
I1 = = = 1 Amp
(10 + RTH) (10 + 6.6667)
The example above is messy numerically, and it is important to use

sufficient decimal places to be accurate. Instead of decimals,
improper fractions can be used, which are sometimes easier to
calculate.
Norton's Theorem
The Norton theorem converts an ordinary circuit to an equivalent parallel circuit which is a current source in
parallel with a resistor. The technique is similar to the thevenin theorem and two points in a circuit must be
defined, this is where the analysis will take place.

As with Thevenin, the equivalent circuit is a current generator In and norton equivalent resistance,
Rn. These must be worked out to use the Norton theorem. The analysis points using Norton are short
circuited, whereas using the Thevenin Method they are open circuit.
Value of VTH and RTH
The value of Vth is found by either measuring (if you don't know what's in the circuit) or be using circuit
analysis. To find Rth ( with load removed) short circuit voltage supplies, open current sources and calculate
the equivalent resistance.
An Example :
Norton's theorem is demonstrated to find the current flowing through the 50 ohm resistor, I1 in the diagram
below :
The points A and B is where the Norton conversion takes place, the rightmost 50 ohm (load) resistor
is first removed, and diagram redrawn with terminals A and B are short circuited, see below:
First the Norton Resistance RN is calculated. Any current sources

are short circuited and any voltage sources are drawn open circuit as

shown in the left diagram. The resistance in the circuit is now a 50 ohm resistor in series with a 100 ohm
resistor and another 50 ohm in parallel. The Norton Resistance is:
50 * 100
RN = 50 + = 83.3333 Ohm
( 50 + 100 )
First the total current It is calculated using ohm's law, this

is the battery voltage divided by total resistance. The resistance in
the circuit is now a 50 ohm resistor in series with a 100 ohm
resistor and another 50 ohm in parallel. (100 ohm in parallel with
50 ohm is 33.3333.) The Norton Resistance RN is:
100
It = 1.2
( 50 +
= Amp
33.3333)
Now that It is
known the circuit can be redrawn as shown left to find
the value of the equivalent Norton Current. Using the
current division rule, IN is worked out:
1.2 * 100
IN = = 0.8 Amp
( 50 + 100)
The Norton equivalent circuit can now be completed
with the right hand 50 ohm resistor included:
The current through the load, I, can now be found using the current division rule :
0.8 * 83.333
I= = 0.5 Amp
( 50 + 83.3333)
The results can be verified using the Thevenin method or a circuit simulation.

PRACTICAL NO. 6
AIM:
To build RLC circuits and to observe the transient response to a step input.
REQUIREMENT:
 Multisim Software
THEORY:
RLC circuits are widely used in a variety of applications such as filters in communications systems,
ignition systems in automobiles, defibrillator circuits in biomedical applications, etc. The analysis of RLC
circuits is more complex than of the RC circuits we have seen in the previous lab. RLC circuits have a much
richer and interesting response than the previously studied RC or RL circuits. A summary of the response is
given below.

Let’s assume a series RLC circuit as is shown in Figure 1. The discussion is also applicable to other
RLC circuits such as the parallel circuit.
Figure 1: Series RLC circuit
By writing KVL one gets a second order differential equation. The solution consists of two parts:
x(t) = xn(t) + xp(t),
in which xn(t) is the complementary solution (=solution of the homogeneous differential equation also
called the natural response) and a xp(t) is the particular solution (also called forced response). Lets focus on
the complementary solution. The form of this solution depends on the roots of the characteristic equation,
(1)
In which is the damping ratio and is the undamped resonant frequency. The roots of the quadratic
equation are equal to,
(1b)
For the example of the series RLC circuit one has the following characteristic equation for the current
iL(t) or vC(t),
s2 + R/L.s + 1/LC =0. (2)
Depending on the value of the damping ratio one has three possible cases:
Case 1: Critically damped response: two equal roots s= s1= s2
(3)
The total response consists of the sum of the complementary and the particular solution. The case of a
critically damped response to a unit input step function is shown in Figure 2.
Case 2: Overdamped response: two real and unequal roots s1 and s2
(4)
Figure 2 shows an overdamped response to a unit input step function.

Figure 2: Critically and overdamped response to a unit input step function.
Case 3: Underdamped response: two complex roots
(5)
Figure 3 shows an underdamped response to a unit input step function.
Figure 3: Underdamped response to a unit input step function.
In-lab assignments
A. Equipment:
 1. Agilent Signal Generator

 2. Agilent Scope
 3. Protoboard
 4. Resistor: 5Kohm potentiometer
 5. Capacitors: 100nF
 6. Inductor 100mH
 7. box with cables and connectors
 8. Scope Probe
 9. DMM

 10. RLC Meter

 10. Multisim software
B. Procedure
1. Simulate the three RLC circuits using Multisim software for the cases of damping ratio equal to 1,
2 and 0.2 (use the values of R, L and C found from the pre-laboratory). Use a square wave with 1Vpp (i.e.
amplitude of 0.5V with offset of 0.5V - use the function generator in EWB) and frequency of 200 Hz as input
voltage. Compare the waveforms with the one you calculated in the pre-lab. Make a print out.
2. Get the components L and C you will need to build the RLC circuit. A real inductor consists of a
parasitic resistor (due to the windings) in series with an ideal inductor as shown in Figure 4. Measure the
value of the inductor and the parasitic resistance RL using an RLC meter and record these in your notebook.
Measure also the value of the capacitor. For the resistors use a 5 kOhm potentiometer.
Figure 4: Model of an inductor
3. Build the series RLC circuit of Figure 5, using the values for L and C found in the pre-lab
corresponding to the damping ratio of 1, 2 and 0.2.
Figure 5: RLC circuit: (a) RTOT includes all resistors in the circuit; (b) showing the different resistors
in the circuit.
The total resistor RTOT of the circuit consists of three components: RT which is the output resistance of
the function generator (50 Ohm), the parasitic resistor RL and the actual resistor R. First calculate the
required resistor R such that the total resistor corresponds to the one found in the pre-lab for each case. Fill
out a table similar to the one shown below.
Damping ratio
1 2 0.2
RT (Ohm) . . .
RL (Ohm) . . .

Rtot (Ohm) . . .
R (Ohm) . . .
4. Measure the response of each case.
Case 1: critically damped response.
a. Set the potentiometer to the value R calculated above corresponding to a damping ratio of 1.
b. Set the function generator to 1Vpp with an offset voltage of 0.5V and a frequency of 200
Hz. Display this waveform on the oscilloscope. Measure the voltage over the capacitor and display
the waveform vC(t)on the scope. Measure its characteristics: risetime, Vmin, Vmax, and Vpp. Make also
a print out of the display. Compare the measured results with the one from the pre-lab and the
simulations.
Case 2: overdamped response.

a. Set the potentiometer to the value R calculated above corresponding to a damping ratio of 2.
Measure and display the response over the capacitor and make a print out. Determine the rise time,
min and max value of the voltage vC.
b. Calculate one of the time constants of the expression (4). Usually one of the time constants
is considerably larger than the other one which implies that the exponential with the smallest time
constant dies out quickly. You can make use of this to find the largest time constant. Measure two
points on the graph (v1,t1) and (v2,t2) as shown in Figure 6. Choose t1 sufficiently away from the
origin so that one of the exponentials has decayed to zero. You can than make use of the following
relationship to find the time constant:
(7)
In which Vf is the final value of the exponential (value at the time t=infinite). The expression
you derived in the last lab: =trise/2.2 is a special case of the above expressions (i.e. v1=0.1Vmax;
v2=0.9Vmax).

Figure 6: method to measure the time constant.
Case 3: underdamped response
a. Set the potentiometer corresponding to the value R calculated above corresponding to a

damping ratio of 0.2. Measure and display the response over the capacitor and make a print out.
Determine its characteristics: voltage and time of the first peak, voltage and time of the second peak.
Make a print out.
b. Determine the value of and dfrom the measured waveform (See Figure 3). Use the
expression (7) to determine the value of the time constant (=1/).
5. Vary the potentiometer and observe the behavior of the response (display the voltage over the
capacitor). Notice when the output goes from underdamped to critically damped and overdamped. In general,
a critically damped response is preferred because it does not give overshoot or "ringing" and has a fast rise
time. An overdamped response has a slower rise time than the other responses, while the underdamped
response rises the fastest, but also give a lot of overshoot which is not desired. Record your observations in
you lab notebook.

PRACTICAL NO. 7
AIM:
To Study the Behavior of a Given Feed-Back Control System.
REQUIREMENT:
THEORY:
Op-Amp Inverting Amplifier.
An inverting amplifier using opamp is a type of amplifier using opamp where the output waveform
will be phase opposite to the input waveform. The input waveform will be amplifier by the factor Av
(voltage gain of the amplifier) in magnitude and its phase will be inverted. In the inverting amplifier circuit
the signal to be amplified is applied to the inverting input of the opamp through the input resistance R1. Rf is
the feedback resistor. Rf and Rin together determines the gain of the amplifier. Inverting operational

amplifier gain can be expressed using the equation Av = – Rf/R1. Negative sign implies that the output signal
is negated. The circuit diagram of a basic inverting amplifier using opamp is shown below.
Inverting amplifier using opamp
The input and output waveforms of an inverting amplifier using opamp is shown below. The graph is
drawn assuming that the gain (Av) of the amplifier is 2 and the input signal is a sine wave. It is clear from the
graph that the output is twice in magnitude when compared to the input (Vout = Av x Vin) and phase
opposite to the input.
Inverting operatinal amplifier waveform

Practical inverting amplifier using 741
A simple practical inverting amplifier using 741 IC is shown below. uA 741 is a high performance
and of course the most popular operational amplifier. It can be used in a verity of applications like integrator,
differentiator, voltage follower, amplifier etc. uA 741 has a wide supply voltage range (+/-22V DC) and has
a high open loop gain. The IC has an integrated compensation network for improving stability and has short
circuit protection.
Signal to be amplified is applied to the inverting pi (pin2) of the IC. Non inverting pin (pin3) is
connected to ground. R1 is the input resistor and Rf is the feedback resistor. Rf and R1 together sets the gain
of the amplifier. With the used values of R1 and Rf the gain will be 10 (Av = -Rf/R1 = 10K/1K = 10). RL is
the load resistor and the amplified signal will be available across it. POT R2 can be used for nullifying the
output offset voltage. If you are planning to assemble the circuit, the power supply must be well regulated
and filtered. Noise from the power supply can adversely affect the performance of the circuit. When
assembling on PCB it is recommended to mount the IC on the board using an IC base.

PRACTICAL NO. 8
AIM:
To Study the Function of Op-Amp Integrator Circuit Through Simulation Using Multisim.
REQUIREMENT:
THEORY:
An integrator circuit is a circuit in which the input waveform. An integrator circuit based on opamp is
shown in fig1. Such a circuit is also termed as an integrating amplifier. The circuit is somewhat similar to an
opamp inverting amplifier but the feedback resistor Rf is replaced by a capacitor Cf. The circuit diagram of
an opamp as an integrator is shown below.
Op-Amp Integrator Circuit Diagram

Equation for the instantaneous output voltage of the opamp integrator can be derived as follows.
Applying Kirchoff’s current (KCL) at node V2 we get
i1= iF + iB
Since the input resistance of an opamp is very high (in the range of Mega ohms) iB will be very small
at it can be neglected.
Therefore i1 = iF
The relation between the current through a capacitor and voltage across it is iC = C dv/dt.
Therefore iF = Cf X d (V2 – Vo ) / dt
Also i1 = (Vin – V2) / R1.
Therefore the equation i1 = iF can be rewritten as (Vin – V2) / R1 = Cf X d(V2 – Vo) / dt……….(1)
Since the non-inverting input is connected to ground, V1 can be taken as 0. Since the open loop gain
of the present circuit is near infinity V2 can be assumed to be zero.
So the equation (1) becomes; Vin / R1 = Cf X d (-Vo) / dt
Integrating the both sides of the above equation with respect to time, we get

Rearranging the equation we get :
C is the integration constant and it has a proportional relationship with the output voltage at time t =
0.From equation (2) it is clear that the output voltage has an inverse relation with the R1 Cf (time constant)
and a directly proportional relation with the negative integral of the input voltage.
In the DC condition Cf offers infinite resistance and so the integrator circuit will be like an inverting
opamp amplifier with infinite feedback resistance (Rf = ∞). The equation for the voltage gain (A) of an
opamp amplifier in inverting mode is A = -(Rf/R1). Substituting Rf=∞ in the present scenario we get A=∞.
Therefore the small input offset voltage will get amplified by this factor and there will be an error voltage at
the output. This problem can be solved by adding a feedback resistor Rf parallel to Cf as shown in fig 4
shown below.
Practical
Op-Amp Integrator Circuit
The addition of Rf will fix the low frequency gain (A) of the circuit to a fixed small value and so the
input offset voltage will have practically no effect on the output offset voltage and variations in the output
voltage is prevented.
Integrating a square wave will result in a triangle waveform and integrating a sine wave will result in
a Cosine waveform. It is shown in the figures shown below.

Integrating square wave
Integrating sine wave waveform
PRACTICAL NO. 9
AIM:
To Study the Function of Op-Amp Differentiator Circuit Through Simulation Using Multisim.
REQUIREMENT:
THEORY:
Op-Amp Differentiator Circuit
The input signal to the differentiator is applied to the capacitor. The capacitor blocks any DC content
so there is no current flow to the amplifier summing point, X resulting in zero output voltage. The capacitor
only allows AC type input voltage changes to pass through and whose frequency is dependant on the rate of
change of the input signal.

At low frequencies the reactance of the capacitor is “High” resulting in a low gain ( Rƒ/Xc ) and low
output voltage from the op-amp. At higher frequencies the reactance of the capacitor is much lower resulting
in a higher gain and higher output voltage from the differentiator amplifier.
However, at high frequencies an op-amp differentiator circuit becomes unstable and will start to
oscillate. This is due mainly to the first-order effect, which determines the frequency response of the op-amp
circuit causing a second-order response which, at high frequencies gives an output voltage far higher than
what would be expected. To avoid this the high frequency gain of the circuit needs to be reduced by adding
an additional small value capacitor across the feedback resistor Rƒ.
Ok, some math’s to explain what’s going on!. Since the node voltage of the operational amplifier at
its inverting input terminal is zero, the current, i flowing through the capacitor will be given as:
The charge on the capacitor equals Capacitance x Voltage across the capacitor
The rate of change of this charge is
But dQ/dt is the capacitor current i
From which we have an ideal voltage output for the op-amp differentiator is given as:
Therefore, the output voltage Vout is a constant -Rƒ.C times the derivative of the input voltage Vin
with respect to time. The minus sign indicates a 180o phase shift because the input signal is connected to the
inverting input terminal of the operational amplifier.
One final point to mention, the Op-amp Differentiator circuit in its basic form has two main disadvantages
compared to the previous integrator circuit. One is that it suffers from instability at high frequencies as
mentioned above, and the other is that the capacitive input makes it very susceptible to random noise signals
and any noise or harmonics present in the source circuit will be amplified more than the input signal itself.
This is because the output is proportional to the slope of the input voltage so some means of limiting the
bandwidth in order to achieve closed-loop stability is required.

Op-amp Differentiator Waveforms:
If we apply a constantly changing signal such as a Square-wave, Triangular or Sine-wave type signal
to the input of a differentiator amplifier circuit the resultant output signal will be changed and whose final
shape is dependant upon the RC time constant of the Resistor/Capacitor combination.

Improved Op-amp Differentiator Amplifier
The basic single resistor and single capacitor op-amp differentiator circuit is not widely used to
reform the mathematical function of Differentiation because of the two inherent faults mentioned above,
“Instability” and “Noise”. So in order to reduce the overall closed-loop gain of the circuit at high frequencies,
an extra resistor, Rin is added to the input as shown below.

PRACTICAL NO. 10
AIM:
Simulate Simple Filtering Signal Processing Function Using Multisim.
REQUIREMENT:
THEORY:
There are many different types of filters, including low pass, high pass and band pass. We will
discuss each of the following filters in turn and how they are used and constructed using Op Amps. When a
filter contains a device like an Op Amp they are called active filters. These active filters differ from passive
filters (simple RC circuits) by the fact that there is the ability for gain depending on the configuration of the
elements in the circuit. There are some problems encountered in active filters that need to be overcome. The
first is that there is still a gain bandwidth limitation that arises. The second is the bandwidth in general. In a
high pass filter there is going to be high frequency roll off due to the limitations of the Op Amp used. This is
very hard to overcome with conventional op amps. The mathematical operations discussed in the previous
lab (the integrator and differentiator) are both types of active filters. As for now, the discussion will focus
mainly on the low pass (LP), high pass (HP) and band pass (BP) filters. There is also a band stop filter that
can be created from the band pass filter with a simple change of components.
Low Pass Filters

The low pass filter is one that allows low frequencies and stops (attenuates) higher frequencies, hence
the name. The design of a low pass filter needs to take into consideration the maximum frequency that would
need to be allowed through. This is called the cut off frequency (or the 3 dB down frequency). Based on the
type of filter that is used (e.g. Butterworth, Bessel, Tschebyscheff) the attenuation of the higher frequencies
can be greater. This attenuation is also based on the order (e.g. 1st, 2nd, 3rd…) of the filter that is used. Based
on the order of the filter the rolloff of the filter can be calculated using the formula –n*20 dB/decade. This
means that a first order low pass filter has an attenuation of -20 dB/decade, while a second order filter should

have -40 dB/decade rolloff and on down the list for higher orders. Shown in Figure 1 is the basic active 1st
order low pass filter (in the non-inverting configuration) with unity gain.
Figure 1: Basic 1st Order Bessel LP Filter in the Non-Inverting Configuration with Unity Gain
The equation in (1) is used to calculate the value of the capacitor needed based on a chosen value for
cutoff frequency and R1 (or vice versa if a value for C1 and a cutoff frequency are chosen then the value of R1
can be found). There is unity gain in this configuration because of the non-inverting properties of the Op
Amp. To change the gain, the feedback network must be changed to include two other resistors (R2 and R3).
The gain is then found to be 1 + R3/R2 because of the non-inverting configuration. The circuit with a non-
unity gain is shown in Figure 2.
fc = 1/(2piR1C1)…..(1)
Figure 2: Basic 1st Order Bessel LP Filter in the Non-Inverting Configuration with Non-unity Gain

High Pass Filters

If creating a low pass filter was easy, then creating a high pass filter is even easier. In the case of the
st
1 order Bessel LP filter the capacitor and resistor only need to be interchanged with each other and the result
is a high pass filter. The same equation holds for finding the cutoff frequency and is shown in (1). The circuit
shown in Figure 4 is that of a 1st order Bessel HP filter with unity gain. The gain can be adjusted to the non-
unity case by adding the feedback network resistors in the same location as the LP circuit of Figure 2.
Figure 3: 1st Order Bessel HP Filter with unity gain

Digital Electronics LAB MANUAL

Uploaded by

Copyright:

Available Formats

You might also like

Digital Electronics LAB MANUAL

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Digital Electronics LAB MANUAL

Uploaded by

Copyright:

Available Formats

INSTITUTE OF TECHNOLOGY & MANAGEMENT, VADODARA

BASIC-ELECTRONICS LAB MANUAL Page 1

 N-type metal–oxide–semiconductor logic (NMOS)

BASIC-ELECTRONICS LAB MANUAL Page 2

VPL-DICT Digital IC Tester

BASIC-ELECTRONICS LAB MANUAL Page 3

CMOS ICs (40 Series): 00 01 02 06 07 08 09 10 11 12 13 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

BASIC-ELECTRONICS LAB MANUAL Page 4

CMOS ICs (MC140) : MC140

CMOS ICs (45 Series) : 01 02 03 06 08 10 11 12 13 14 15 16 18 19 20 29 30 31 32 37 38 39 41 43 44 47 51

TTL 74/54 Series : 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Microprocessor, EPROM, RAM and other digital ICs :

BASIC-ELECTRONICS LAB MANUAL Page 5

 Implementing an Inverter Using only NAND Gate

BASIC-ELECTRONICS LAB MANUAL Page 6

 Implementing AND Using only NAND Gates

 Implementing OR Using only NAND Gates

 Implementing an Inverter Using only NOR Gate

BASIC-ELECTRONICS LAB MANUAL Page 7

 Implementing OR Using only NOR Gates

 Implementing AND Using only NOR Gates

1. Connect the trainer kit to ac power supply.

BASIC-ELECTRONICS LAB MANUAL Page 8

BASIC-ELECTRONICS LAB MANUAL Page 9

BASIC-ELECTRONICS LAB MANUAL Page 10

BASIC-ELECTRONICS LAB MANUAL Page 11

BASIC-ELECTRONICS LAB MANUAL Page 12

BASIC-ELECTRONICS LAB MANUAL Page 13

Basically, a D/A converter have an op-amp. It can be classified into 2 types.

BASIC-ELECTRONICS LAB MANUAL Page 14

Digital to Analog Converter using Binary-Weighted Resistors

BASIC-ELECTRONICS LAB MANUAL Page 15

Digital-to-Analog Converter Circuit - Binary-Weighted Resistors Method Graph

Digital to Analog Converter with R and 2R Resistors

BASIC-ELECTRONICS LAB MANUAL Page 16

Digital to Analog Converter with R and 2R Resistors

Thus, according to Thevenin’s equivalent resistance, RTH,

The resultant circuit is shown below.

BASIC-ELECTRONICS LAB MANUAL Page 17

Digital to Analog Converter with R and 2R Resistors - Resultant Circuit

Digital to Analog Converter with R and 2R Resistors - Graph

Current through 2R connected to +5V = 5V/20kohm = 0.25 mA

The current will be the same as that in Rf.

Output voltage equation is given below.

BASIC-ELECTRONICS LAB MANUAL Page 18

BASIC-ELECTRONICS LAB MANUAL Page 19

Value of VTH and RTH

A demonstration of the thevenin technique to find current I1 in the diagram below:

First, the circuit to the right of points A and B is converted to a

BASIC-ELECTRONICS LAB MANUAL Page 20

The example above is messy numerically, and it is important to use

BASIC-ELECTRONICS LAB MANUAL Page 21

First the Norton Resistance RN is calculated. Any current sources

BASIC-ELECTRONICS LAB MANUAL Page 22

First the total current It is calculated using ohm's law, this

BASIC-ELECTRONICS LAB MANUAL Page 23

BASIC-ELECTRONICS LAB MANUAL Page 24