L18 - Multilevel Gate Circuits - 1

EE213M
Digital Circuits
Arun Tej M.
EE213M Digital Circuits
L18: Multi-Level Gate Circuits - 1

Multi-Level Gate Circuits
• The maximum number of gates cascaded in series between a circuit input and the output is referred to
as the number of levels of gates.
• We usually assume that all variables and their complements are available as inputs. Hence, inverters
(i.e., NOT gates) are not counted when determining the number of levels.
• Thus, a function written in SOP or POS form corresponds directly to a two-level gate circuit.
Terminology:
• AND-OR circuit ⇒ Two-level circuit with AND gates at inputs followed by an OR gate at the output
• OR-AND circuit ⇒ Two-level circuit with OR gates at inputs followed by an AND gate at the output
• OR-AND-OR circuit ⇒ Three-level circuit with OR gates at inputs, followed by a level of AND
gates followed by an OR gate at the output
• Circuit of AND and OR gates ⇒ No particular ordering of the gates

Tree Diagram
𝑍 = 𝐴𝐵 + 𝐶 𝐷 + 𝐸 + 𝐹𝐺 + 𝐻
4 levels
6 gates
13 gate inputs
Tree Diagram
(expand by partially
𝑍 = 𝐴𝐵 + 𝐶 𝐷 + 𝐸 + 𝐹𝐺 + 𝐻 = 𝐴𝐵 𝐷 + 𝐸 + 𝐶 𝐷 + 𝐸 + 𝐴𝐵𝐹𝐺 + 𝐶𝐹𝐺 + 𝐻
multiplying out)
3 levels
6 gates
19 gate inputs
Multi-Level Gate Circuits
• Sometimes, increase in the number of levels will reduce the number of gates and inputs, and thus
reduce the cost of the circuit. However, the number of levels that can be increased will also depend on
the circuit delay allowed.
• The number of levels in an AND-OR circuit can usually be increased by factoring the SOP form of
expression from which it is derived.
• The number of levels in an OR-AND circuit can usually be increased by multiplying out some of the
terms in the POS form of expression from which it is derived.
Example
𝑓 𝑎, 𝑏, 𝑐, 𝑑 = σ 𝑚(1, 5, 6, 10, 13, 14). Realize this function with AND and OR gates using 2 level and 3 level
circuits. Also, realize these with AND gate at the output as well as OR gate at the output. Compare all
these circuits and mention which circuit uses less no. of gates and inputs.
𝑎𝑏
𝑐𝑑 00 01 11 10
As we know, SOP form leads directly to 2 level AND-OR circuit.
00 0 0 0 0
01 1 1 1 0
11 0 0 0 0
10 0 1 1 1 2 levels
5 gates
16 gate inputs
𝑓 = 𝑎′ 𝑐 ′ 𝑑 + 𝑏𝑐 ′ 𝑑 + 𝑏𝑐𝑑 ′ + 𝑎𝑐𝑑′
Example
𝑎𝑏
𝑐𝑑 00 01 11 10 No. of levels can be increased by factoring the SOP expression
00 0 0 0 0
01 1 1 1 0
11 0 0 0 0
10 0 1 1 1 3 levels
5 gates
12 gate inputs
𝑓 = 𝑎′ 𝑐 ′ 𝑑 + 𝑏𝑐 ′ 𝑑 + 𝑏𝑐𝑑 ′ + 𝑎𝑐𝑑′
= 𝑐 ′ 𝑑 𝑎′ + 𝑏 + 𝑐𝑑′(𝑎 + 𝑏)
Example
𝑎𝑏
𝑐𝑑 00 01 11 10
As we know, POS form leads directly to 2 level OR-AND circuit.
00 0 0 0 0
01 1 1 1 0
11 0 0 0 0
2 levels
10 0 1 1 1 5 gates
14 gate inputs
𝑓′ = 𝑐 ′ 𝑑′ + 𝑎𝑏′ 𝑐′ + 𝑐𝑑 + 𝑎′ 𝑏′ 𝑐
𝑓 = (𝑐 + 𝑑)(𝑎′ + 𝑏 + 𝑐)(𝑐 ′ + 𝑑 ′ )(𝑎 + 𝑏 + 𝑐 ′ )
Example
No. of levels can be increased by partially multiplying out the POS expression
𝑥 + 𝑦 𝑥 + 𝑧 = 𝑥 + 𝑦𝑧
𝑓 = (𝑐 + 𝑑)(𝑎′ + 𝑏 + 𝑐)(𝑐 ′ + 𝑑 ′ )(𝑎 + 𝑏 + 𝑐 ′ )
= 𝑐 + 𝑑 𝑎′ + 𝑏 [𝑐 ′ + 𝑑′(𝑎 + 𝑏)]
3 levels
Requires 4 levels to implement.
7 gates
We can multiply out 𝑑(𝑎′ + 𝑏) and 𝑑′(𝑎 + 𝑏) to 16 gate inputs
get 3 level circuit.
𝑓 = (𝑐 + 𝑎′ 𝑑 + 𝑏𝑑)(𝑐 ′ + 𝑎𝑑 ′ + 𝑏𝑑′)
Example
Another way to obtain an 𝑛-level circuit with AND-output:
Realize 𝑛-level circuit for 𝑓′ with OR-output and then complement it.
𝑓′ = 𝑐 ′ 𝑑′ + 𝑎𝑏′ 𝑐′ + 𝑐𝑑 + 𝑎′ 𝑏′ 𝑐
= 𝑐 ′ (𝑑 ′ + 𝑎𝑏′ ) + 𝑐(𝑑 + 𝑎′ 𝑏′ )
= 𝑐 ′ (𝑑 ′ + 𝑎)(𝑑 ′ + 𝑏′ ) + 𝑐(𝑑 + 𝑎′ )(𝑑 + 𝑏′ ) 3 – level circuit for 𝑓′ with OR-output

Complementing this expression, we get 3 -
𝑓 = (𝑐 + 𝑎′ 𝑑 + 𝑏𝑑)(𝑐 ′ + 𝑎𝑑 ′ + 𝑏𝑑′)
level circuit for 𝑓 with AND-output
Example
2 level AND-OR: 5 gates, 16 gate inputs

2 level circuit: OR-AND is the best
2 level OR-AND: 5 gates, 14 gate inputs
3 level OR-AND-OR: 5 gates, 12 gate inputs

3 level circuit: OR-AND-OR is the best
3 level AND-OR-AND: 7 gates, 16 gate inputs
In general, to be sure of obtaining a minimum solution, one must find both

the circuit with the AND-gate output and the one with the OR-gate output.
Homework
NAND and NOR
• Logic designers frequently use NAND and NOR gates because they are generally faster and use fewer
components than AND or OR gates.
• Any logic function can be implemented using only NAND gates or only NOR gates.
≡
Functionally Complete Set of Gates
• A set of logic operations is said to be functionally complete if any Boolean function can be expressed in terms of
this set of operations.
• Any function can be expressed in SOP form and an SOP expression uses only the AND, OR, and NOT
operations ⇒ The set AND, OR, and NOT is functionally complete.
• Similarly, a set of logic gates is functionally complete if all switching functions can be realized using this set
of gates.
• Thus, any set of logic gates which can realize AND, OR, and NOT is also functionally complete.
• AND and NOT are a functionally complete set of gates since OR can also be realized using them.
• Similarly, OR and NOT can be used to obtain AND gate since 𝑋𝑌 = (𝑋 ′ + 𝑌 ′ )′.
• If a single gate forms a functionally complete set by itself, then any switching function can be
realized using only gates of that type.
• NAND = AND and NOT ⇒ AND, NOT, and OR ⇒ NAND gate itself is functionally complete
• Hence, any function can be realized using only NAND gates.
• Similarly, any function can be realized using only NOR gates.
{AND – EXOR – 1} is a functionally complete set.
{OR – EXOR – 1} is a functionally complete set.

{2x1 MUX – 0 – 1} is a functionally complete set.
Two-Level NAND and NOR Gate Circuits
• A two-level circuit composed of AND and OR gates is easily converted to a circuit composed of NAND
gates or NOR gates. This conversion is carried out by
i. Using 𝐹 = 𝐹′ ′
ii. Applying DeMorgan’s laws:

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EE213M

L18: Multi-Level Gate Circuits - 1

• Circuit of AND and OR gates ⇒ No particular ordering of the gates

𝑓 = (𝑐 + 𝑑)(𝑎′ + 𝑏 + 𝑐)(𝑐 ′ + 𝑑 ′ )(𝑎 + 𝑏 + 𝑐 ′ )

Another way to obtain an 𝑛-level circuit with AND-output:

= 𝑐 ′ (𝑑 ′ + 𝑎)(𝑑 ′ + 𝑏′ ) + 𝑐(𝑑 + 𝑎′ )(𝑑 + 𝑏′ ) 3 – level circuit for 𝑓′ with OR-output

2 level AND-OR: 5 gates, 16 gate inputs

3 level OR-AND-OR: 5 gates, 12 gate inputs

In general, to be sure of obtaining a minimum solution, one must find both

{OR – EXOR – 1} is a functionally complete set.

ii. Applying DeMorgan’s laws:

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