Assignment for Design and Verification using Verilog Internship Program

NOTE :
1. Assignments to be submitted with codes and simulation snapshots as applicable in a
document form (ms-word template shared).
2. Last date for submission: By 1 week post the completion of Internship.
3. Course certificate shall be provided upon submission of assignments and minimum
scoring of 70% and above.

Session 03 : HDL Modelling and Digital Fundamentals

1. Convert 2DB7 to decimal and binary number system?

2. Perform the following operations using 2’c complement method?
i. -39+92
ii. -19-7
iii. 44+45
iv. -1+1
3. Represent the Boolean expression f(A,B,C)= A’BC’ + A’BC+A’ B’ C’+ABC in SPO and POS forms?
4. Explain how many bits to be added for detecting error in any 3 bits in the data stream of
10 bits?
5. Convert Binary code 0101 to gray code and convert gray code 1010 to binary?

Session 04 : Verilog Constructs – Part I

1. Compile, remove the syntax errors and determine the output for the following Verilog
code?

//casex example
module casex_example();
reg [3:0] opcode;
reg [1:0] a,b c;
reg [1:0] out;
always @ (opcode a or b or c)
casex(opcode)
4'b1zzx : begin // Don't care 2:0 bits
out = a;$display("@%0dns 4'b1zzx is selected, opcode
%b",$time,opcode); end
4'b01?? : begin // bit 1:0 is don't care
out = b; $display("@%0dns 4'b01?? is selected, opcode
%b",$time,opcode); end
4'b001? : begin // bit 0 is don't care
out = c; $display("@%0dns 4'b001? is selected, opcode
%b",$time,opcode); end
default : begin
$display("@%0dns default is selected, opcode %b,$time,opcode); end
endcase

// Testbench code goes here

always #2 a = $random;
always #2 b = $random;
always #2 c = $random;
initial begin
CONFIDENTIAL
Excel VLSI Technologies and/or Entuple Technologies
 opcode = 0;
#2 opcode = 3'b101x;
#2 opcode = 4'b0101;
#2 opcode = 0010;
#2 opcode = 4'b0000; #
#2 $finish;
end
endmodule

Session 05 : Verilog Constructs – Part II

1. Write a Verilog program to demonstrate the behaviour of blocking and non-blocking ?

2. Write a function to compute temperature conversion from centigrade to Fahrenheit and
call this function in a Verilog task? Compile and Simulate the results.
3. Generate a 200 MHz clock and simulate and attach the output waveform?
4. Write a program to demonstrate the differences between casex and casez?
5. Write a simple program to demonstrate differences between $display, $strobe, $write,
$monior?
6. Write a program for the usage of `include, `define and parameter?
7. Declare a simple 2 dimensional array for implementing 64 locations memory, write a
program to load the memory using $readmemh and write the contents of the memory
back to a file using $writememh?
8. Debug, compile and simulate the following Verilog code?

//Passing more than one parameter

module ram_sp_sr_sw (
input clk , // Clock Input
input address , // Address Input
inout data , // Data bi-directional
input cs , // Chip Select
input we , // Write Enable/Read Enable
input oe // Output Enable
);
parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// Actual code for RAM Read/Write here
initial begin
$display ("ADDR_WIDTH=%0d, DATA_WIDTH=0d, RAM_DEPTH=%0d",
ADDR_WIDTH, DATA_WIDTH, RAM_DEPTH);
end
endmodule
// Memory Config 2
module ram_controller2 ();//Some ports
ram_sp_sr_sw #(
.DATA_WIDTH(8),
.ADDR_WIDTH(16),
.RAM_DEPTH(1024)) ram(address,data,cs,we,oe);
initial begin
#1; end
endmodule

CONFIDENTIAL
Excel VLSI Technologies and/or Entuple Technologies
Session 06: Design and verification of Combinational circuits

1. Design and Verify using Verilog test bench -- 1 to 4 Demultiplexer ?

2. Design and Verify 8 to 3 Priority Encoder?
3. Develop a decoder to decode given 16-bit address, equally to 4 memory devices.
generate chip selects for all the four devices? Indicate size of each memory?
4. Design 4 bit adder circuit and verify?
5. Design BCD to 7 segment display and verify?

Session 07: Design and Verification of Sequential circuits

1. Write Verilog codes for latch and a D flip flop and verify?
2. Write Verilog code for T flip flop, JK flip flop?
3. Develop Verilog code for 4 bit synchronous shift register? use clock frequency of 100 Mhz
in test bench?
4. Design mod 24 counter and Verify?
5. Develop Verilog code for divide by 4 clock output?

Session 09 : Microprocessors, Timing

1. Calculate the max frequency of the circuit with 2 flip flops connected back to back with a
combinational circuit between flip flops with following timings given.
a. flip flop 1 - delay - 2 ns,
b. combinational circuit delay - 4 ns
c. setup time of flip flop 1 - 2 ns
d. setup time of flip flop 2 - 2 ns
e. flip flop 2 delay - 2 ns
2. Write a Verilog code for double synchronizer? and simulate?

Projects :
1. State machine design- Mandatory
2. Dual Port Memory design- Mandatory
3. Serial Adder design- Mandatory
4. FIFO Design and Verification - Mandatory
5. APB Memory design - Optional
1. Design a mealy machine and develop Verilog code for checking the sequence “1011”
overlapping sequence?
2. Design and Verify 256x8 synchronous Memory as shown below?

addr_a[7:0] addr_b[7:0]

datain_a[7:0] datain_b[7:0]
dataout_a[7:0] dataout_b[7:0]
Dual Port Ram (256x8)
write_a write_b
read_a read_b
clk_a clk_b

CONFIDENTIAL
Excel VLSI Technologies and/or Entuple Technologies
 3. Design and Verify a 4 bit serial adder as shown below?
(Refer this site for more information https://www.isabekov.pro/four-bit-serial-adder-
subtractor/)

4. Design and Verify 16x8 asynchronous FIFO as below? (To know more about FIFO – Refer
http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf)

reset

wdata[7:0] rdata[7:0]

w_enable r_enabl
e
wclk rclk

full_flag empty_flag
async_fifo
(16x8)

5. Design RTL for APB protocol based memory (1kx32) and develop test bench to verify?
(Refer APB specification for more information – https://developer.arm.com/docs/ihi0024/c)

APB_MEMORY (DUT)
PCLK

PRESETn

PSEL

PADDR[9:0] APB
Slave 1Kx32
PENABLE state Memory
machine
PWRITE

PREADY

PWDATA[7:0]

PRDATA[7:0]

CONFIDENTIAL
Excel VLSI Technologies and/or Entuple Technologies