Amendment Record: Issue No. Description of Amendment Change Request No. Release Date

Accord’s Standards Manual Issue: 1.
7
Accord Confidential
Document No. ASM008 Page 1 of 59
VHDL Coding Standards
Amendment Record
Change Release
Issue No. Description of Amendment
Request No. Date
Draft 1.0 First draft for comments 23/05/2001
Issue 1.1 Release 17/09/2002
Issue 1.2 Document Reviewed and Released as per 100103 25/05/2004
current requirement
Issue 1.3 Typo corrections and minor modifications 100113 10/08/2005
Issue 1.4 Design and coding guidelines according to 100181 04-08-2008
RMM guidelines incorporated
Issue 1.5 Synchronizer guidelines are incorporated 100209 06-07-2009
along with other best practices
Issue 1.6 Delimiters to VHDL comments (File header 100210 24-07-2009
and Sub-programs header) are inserted
Issue 1.7 Guideline for RULE 2.4 and 4.1 updated, 100406 in 16-06-2015
“Quality”
Is it ensured that the tool used to synthesize
100486 in
the RTL is not duplicating the synchronizer
“cust_details”
flip-flops due to fanout or any other reason.
Document is updated as per the current
requirement i.e. all identifiers maximum size
are increased to 32 characters and some
standards are changed to recommendation
from RULE.
ACC-VHD-STD 5.17 RULE is added.
Appendix B is updated for VHDL code review
checklist to keep the compliance check
against the check items simple.
Additional Note is added to ACC-VHD-STD
8.13 guideline.
ACC-VHD-STD 8.11 guideline is updated
with additional details.
VHDL Code examples provided were
updated to avoid conflicts with defined
guidelines.
ASM008 Controlled copy available in Intra-net Web Page and CM

© Accord Global Technology Solutions Private Limited.
# 72 & 73, Krishna Reddy Colony, Domlur layout
Bangalore - 560071, INDIA
Accord’s Standards Manual Issue: 1.7
Accord Confidential
WRITTEN BY: HARISH A H.
PROJECT LEADER – GNSS TECHNOLOGY

SIGNATURE & DATE: _____________________________________________
APPROVED BY: RAKESH A. NAYAK
SR. MANAGER – GNSS TECHNOLOGY

SIGNATURE & DATE: _____________________________________________
RELEASED BY: B SHYAMALA
SR. MANAGER – QUALITY ASSURANCE

SIGNATURE & DATE: _____________________________________________

Accord Confidential
Table of Contents
1 Objectives .................................................................................................................................................... 5
2 Scope............................................................................................................................................................ 5
3 References ................................................................................................................................................... 5
4 Terms and Definitions ................................................................................................................................ 5
5 Assumptions ............................................................................................................................................... 6
6 Outstanding issues ..................................................................................................................................... 6
7 Document Control ....................................................................................................................................... 6
8 Approvals ..................................................................................................................................................... 6
9 Responsibilities ........................................................................................................................................... 6
10 Distribution .................................................................................................................................................. 6
11 Trace-ability ................................................................................................................................................. 6
12 VHDL Coding Guidelines ............................................................................................................................ 7
Appendix A – Accord’s Synchronization Process ................................................................................................ 33
Appendix B – VHDL code review checklist............................................................................................................ 44

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Table of Figures
Figure 1: Directory structure ................................................................................................................... 32

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1 Objectives
This document defines the standards for VHDL coding
2 Scope
The scope of this document is to define the guidelines for the VHDL coding in accordance with
requirements, digital logic design, and naming guidelines, for PLDs.
In this document, the following conventions for guidelines apply,
Rules [RULE] are guidelines that shall be followed by all designers.
Recommendations [REC] are guidelines that are regarded as best practices, but are left to the
discretion of the designer to follow them.
3 References
➢ Michael Keating, and Pierre Bricaud, “Reuse Methodology Manual for System-On-Chip
Designs,” 3rd edition, 2002
➢ http://godavari/intranet/standards/Reuse_Methodology_Manual.pdf
➢ European Space Agency, “VHDL Modelling Guidelines,” Issue 1, 1994
http://godavari/intranet/standards/ModelGuide.pdf
➢ SC-180, RTCA/DO-254, “Design Assurance Guidance for Airborne Electronic Hardware,”

April 19, 2000
➢ Accord, ASM012 – FPGA Requirements, Design, Validation and Verification Standards
4 Terms and Definitions
Acronym Description
ACC-VHD-STD ACOORD – VHDL - Standard
DUT Design Under Test

FPGA Field Programmable Gate Array
GNSS Global Navigation Satellite System

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HDL Hardware Description Language

PLD Programmable Logic Device
RTL Register Transfer Logic
TB Test Bench
VHDL VHSIC HDL
VHSIC Very High Speed Integrated Circuits
5 Assumptions
None
6 Outstanding issues
None
7 Document Control
This document is under change control. Any changes after internal base lining of the document
will be carried out in accordance with Change Control Procedure.
8 Approvals
Manager – GNSS Technology
9 Responsibilities
All the practitioners are responsible for ensuring adherence to this document.
Project Leaders are responsible to ensure that the team members adhere to the standards
specified in this document.
10 Distribution
The document will be available on intranet web page of M/s. Accord Global Technology Solutions
Private Limited.
11 Trace-ability
None

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12 VHDL Coding Guidelines

This section generalizes the standards for VHDL.
12.1 Trace-ability
ACC-VHD-STD 1.1 [RULE] The source code shall implement all the low level requirements correctly
ACC-VHD-STD 1.2 [RULE] The source code shall implement all the low level requirements completely
ACC-VHD-STD 1.3 [RULE] The source code shall not implement anything outside the low level
requirements
ACC-VHD-STD 1.4 [RULE] The components shall have inputs as defined in low-level requirements
ACC-VHD-STD 1.5 [RULE] The components shall have outputs as defined in low-level requirements
ACC-VHD-STD 1.6 [RULE] The source code shall not contain any statement/component that cannot
be verified
ACC-VHD-STD 1.7 [RULE] Any part of the code which can not be tested (coverage), shall have the
alternate means of verification (analysis, review, etc.)
ACC-VHD-STD 1.8 [RULE] The source code shall be traceable to all the low-level requirements
12.2 Design
12.2.1 Reset
ACC-VHD-STD 2.1 [RULE] System (with sequential logic) shall have a global reset, which can initialise
the system to a known state
ACC-VHD-STD 2.2 [RULE] Use only either synchronous or asynchronous type of resets throughout the
system
ACC-VHD-STD 2.3 [RULE] Reset signal connected to reset of flip-flops shall not be used in the data-
path.
i.e., The only logic function for the reset signal should be a direct clear of all
flip-flops. Never use the reset inputs of a flop to implement state machine
functionality. Reserving reset pins on flops for reset only makes it easier to
generate buffer trees for resets.
ACC-VHD-STD 2.4 [RULE] Each asynchronous reset de-assertion shall be synchronized with the clock
with which it is being used. Ensure the tool used to synthesize the RTL is
not duplicating the synchronizer flip-flops due to fanout or any other
reason.

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Note: Duplicating synchronizer flip-flops leads to functionality failure. As

each flip-flop may independently encounter the metastability.
ACC-VHD-STD 2.5 [REC] Avoid internally generated resets
ACC-VHD-STD 2.6 [REC] The internally generated resets should be used as synchronous resets
ACC-VHD-STD 2.7 [REC] If a conditional reset is required, create a separate signal for the reset
signal, and isolate the conditional reset logic in a separate module at the
top level of the design.
ACC-VHD-STD 2.8 [REC] It is preferred to have pulse stretching mechanism for synchronous resets
ACC-VHD-STD 2.9 [REC] There should be a glitch elimination mechanism for asynchronous resets
12.2.2 Clocks
ACC-VHD-STD 3.1 [RULE] Avoid clocks in data-path
ACC-VHD-STD 3.2 [RULE] Do not instantiate clock buffers in the RTL
ACC-VHD-STD 3.3 [REC] Avoid gated clocks
ACC-VHD-STD 3.4 [REC] If the design requires a gated clock, model it in RTL using synchronous
load registers. This will allow the synthesis tool to insert the actual clock
gating logic.
ACC-VHD-STD 3.5 [REC] Avoid flip-flops operating on both the edges of the clock
ACC-VHD-STD 3.6 [REC] If the design must use a large number of both positive-edge and negative-
edge triggered flip-flops in your design, it may be useful to separate them
into different modules
ACC-VHD-STD 3.7 [REC] Have single clock per module
ACC-VHD-STD 3.8 [REC] Avoid internally generated clocks
ACC-VHD-STD 3.9 [REC] If the design must use a gated clock or an internally generated clock, keep
the clock generation circuitry as a separate module at the top level of the
design.
12.2.3 Multiple Clocks

ACC-VHD-STD 4.1 [RULE] Use synchronizers to transfer data between different clock domains.
Ensure the tool used to synthesize the RTL is not duplicating the
synchronizer flip-flops due to fanout or any other reason.
Note: Duplicating synchronizer flip-flops leads to functionality failure. As

each flip-flop may independently encounter the metastability.
ACC-VHD-STD 4.2 [RULE] Signals entering the synchronizer shall directly come from the output of a

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flip-flop
ACC-VHD-STD 4.3 [REC] Whenever synchronizer is used in the design, it shall be separately defined
and shall be used as a component
ACC-VHD-STD 4.4 [RULE] Signal from faster clock domain, entering the slower clock domain through
a synchronizer, shall be held stable for multiple cycles of slower clock
(depending on the number of stages in the synchronizer)
ACC-VHD-STD 4.5 [RULE] If the signal from the source clock domain is not stable for multiple cycles
of destination clock, use the capture circuit to detect the activity on that
signal and then synchronize the captured signal with the destination clock
ACC-VHD-STD 4.6 [RULE] Do not synchronize a signal from source clock domain, at multiple places,
in the destination clock domain
ACC-VHD-STD 4.7 [RULE] Avoid convergence of more than one control signals from the source clock
domain, in the destination clock domain
ACC-VHD-STD 4.8 [RULE] Use a synchronized enable signal, or handshake signals, to pass the multi-
bit signals across clock domain.
E.g. data enable, FIFO
ACC-VHD-STD 4.9 [REC] Avoid the multi-bit signals crossing clock domain
ACC-VHD-STD 4.10 [RULE] There shall be a constraint file associated with each design
ACC-VHD-STD 4.11 [RULE] The constraint file name shall be design name suffixed with _ucf
ACC-VHD-STD 4.12 [RULE] The constraint file shall define the timing constraints and the location
constraints for all the port signals.
ACC-VHD-STD 4.13 [RULE] The constraint file shall have a header according to the guideline
ACC-VHD-STD 7.1
12.2.4 General
ACC-VHD-STD 5.1 [RULE] The enables for inputs and outputs shall be exclusive.
ACC-VHD-STD 5.2 [RULE] Shall avoid latches in the design
ACC-VHD-STD 5.3 [RULE] Signals/variables shall not be initialised during declaration
ACC-VHD-STD 5.4 [RULE] There shall not be any combinational feedback loops in the design
ACC-VHD-STD 5.5 [RULE] There shall not be any feed-throughs in the design
ACC-VHD-STD 5.6 [RULE] Constants should not be initialised using expressions

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ACC-VHD-STD 5.7 [REC] Avoid asynchronous logic in the synchronous design
ACC-VHD-STD 5.8 [REC] Avoid glue logic at top-level of the design
ACC-VHD-STD 5.9 [REC] Avoid timing-exceptions (false-paths and multi-cycle-paths) in the design
ACC-VHD-STD 5.10 [REC] Register all the outputs of the design
ACC-VHD-STD 5.11 [REC] For each sub-block of a hierarchical macro design, register all output
signals from the sub-block.
ACC-VHD-STD 5.12 [REC] Synthesis specific commands should be avoided in the source
code
For e.g.:
A_REG_PROS: process(clk_sys,rst_sys_n)
variable vprint : std_logic;
Begin
.
.
data_r<= data_a;
--synopsys translate _off
vprint:=data_r;
--synopsys translate_on
.
.
end process A_REG_PROS;
ACC-VHD-STD 5.13 [REC] Use technology independent libraries
ACC-VHD-STD 5.14 [REC] Keep late-arriving signals with critical timing closest to the output of a logic
block.
For example, use the late-arriving signal early in an if-else block.
ACC-VHD-STD 5.15 [REC] Keep memory interface pins at the top level of a macrocell to allow user
choice of memory implementation, interface and test.
ACC-VHD-STD 5.16 [REC] Reduce the number flip-flops falling into meta-stable state
The last state in a state machine shall be:
ACC-VHD-STD 5.17 [RULE] “when others =>”
Statement to encompass default states of all applicable signals end case.
12.3 Coding
12.3.1 File

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ACC-VHD-STD 6.1 [RULE] File name shall be same as entity name.
ACC-VHD-STD 6.2 [RULE] File name shall not contain special characters except underscore
ACC-VHD-STD 6.3 [RULE] Length of file name shall be at least 4 characters, and shall not exceed 32
characters
ACC-VHD-STD 6.4 [RULE] File name shall be in lowercase and begin with a character
ACC-VHD-STD 6.5 [RULE] Name of the file should indicate the functionality
ACC-VHD-STD 6.6 [RULE] Name of the package file shall be suffixed with “_pkg”
For e.g.: math_pkg.vhd
ACC-VHD-STD 6.7 [RULE] Name of the library file shall be suffixed with ”_lib”.
For e.g.: ovrload_lib.vhd
ACC-VHD-STD 6.8 [RULE] Name of the configuration file shall be suffixed with “_cfg”
For e.g.: testcase1_cfg.vhd
ACC-VHD-STD 6.9 [RULE] Configurations shall be in a separate file
ACC-VHD-STD 6.10 [RULE] All file names shall have an extension ’. vhd’
ACC-VHD-STD 6.11 [RULE] Test bench file name shall be prefixed with 'tb_'
For e.g.: tb_controller.vhd
ACC-VHD-STD 6.12 [RULE] File name may contain numerals and underscores
ACC-VHD-STD 6.13 [REC] Number of lines in a file should not exceed 1000
12.3.2 Comments
ACC-VHD-STD 7.1 [RULE] Each file shall have file header at the beginning of the file and header shall
start at the first line and first column of the file.
The file header shall be following format

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--/*--------------------------------------------------------
----------------------------------------------------------
--License Information : Accord Software & Systems Pvt Ltd
-- No.37, K R Colony, Domlur Layout,
-- Bangalore - 560 071
-- Licensed software.
-- All rights reserved
-- Filename : acc_dbb1.vhd
-- Description : This module communicates with the
-- DSP.It receives the programmed data
-- form Dsp and transmits the results.
-- This module is the topmost module
-- which binds all the functional modules
-- including correlator, ptti counter
-- battery backup counter, clock manager
-- serial and ahb communication modules.
-- It instantiates thefollowing modules
-- 1. gps_cor
-- 2. clkmanager
-- 3. serial_comm
-- 4. amba_ahb_slave_driver
-- 5. ptti_counter
-- 6. bbcounter
-- 7. comm_interface
-- 8. acq_clk_ctrl
-- 9. memories
a) dpmem_chnl_ind_result
-- b) dpmem_chnl_ind_prog_params
-- Tools used : Xilinx ISE 9.1.03i
-- Modelsim SE 6.2g Simulator

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-- Device selected : Virtex4(xc4vlx160-10ff1513,-10)

--
-- H/W Platform : Windows XP
--
-- Portability : VHDL-93
--
-- Functions : None
--
-- References : None
--
-- Author : Raghavendra Bhat H
-- raghavendra.b@accord-soft.com
--
-- G.S.Naveen
-- naveen.gs@accord-soft.com
--
-- Modification History :
--Version |Date |Author |Change |Description
Number |Request
--1.1 |10-09-2007 |G.S.Naveen |100032 |Incorporated
| | | ASIC |related
| | | changes
|
--1.2 |15-11-2007 |G.S.Naveen |100033 |Used Flip-flops
| | | |memory for CHI
| | | |Program and
|Results memory
| | |
|instead of
| | |
|BRAMS
--------- |--------- |---------- |------
|-------------
*/--
ACC-VHD-STD 7.2 [RULE] Functions/Procedure shall have a header preceding the

function/procedure definition

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For e.g. :
--/*****************************************************************
-- Function Name : CODEMIX_FUN
-- Description : The function performs code mixing
-- operation. It changes the sign of
-- Inphase/Qphase value based on the
-- code bit value
-- Inputs : arg_inp1 std_logic
arg_inp2 std_logic_vector(6 downto 0)
-- outputs : vres_std_val std_logic_vector(8 downto 0)
-- Libraries Used : IEEE.STD_LOGIC_UNSIGNED.ALL
IEEE.STD_LOGIC_UNSIGNED.ALL
-- Assumptions : None
--*****************************************************************/--
ACC-VHD-STD 7.3 [RULE] Process shall have a process header preceding the process definition
For e.g. :
--/***************************************************************
--** Process name : APY_DATA_CORDIC_PROS
--** Description : Generate time pulses to initiate CORDIC input
--** operations These pulses are generated only upon
--** a new data being recognised
--**************************************************************/--
ACC-VHD-STD 7.4 [RULE] Use comments to describe group of ports
ACC-VHD-STD 7.5 [RULE] There shall be no dangling or irrelevant comment.
ACC-VHD-STD 7.6 [RULE] For indentation use 2 spaces. Do not use tabs
ACC-VHD-STD 7.7 [REC] Use comment appropriately to explain process, functions, procedures
and declarations of types and subtypes. Use comments to explain
ports, signals and variables or group of signals or variables. Comments
for timing behaviour should be present
ACC-VHD-STD 7.8 [REC] There should be comments for each statement
ACC-VHD-STD 7.9 [REC] The comments shall be descriptive and not just direct translations or
repetitions of the VHDL code.
12.3.3 Entity and Architecture

ACC-VHD-STD 8.1 [RULE] Entity name should depict the functionality
ACC-VHD-STD 8.2 [RULE] Top entity port signals shall be of std_logic or std_logic_vector type

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ACC-VHD-STD 8.3 [RULE] Length of entity name shall be at least 4 characters, and shall not
exceed 32 characters
ACC-VHD-STD 8.4 [RULE] Architecture of type Simulation should be prefixed with “sim_”, followed
by it’s entity name
For e.g.: architecture sim_data_decoder of data_decoder

is
ACC-VHD-STD 8.5 [RULE] Architecture of type Structural should be prefixed with “str_”, followed
by it’s entity name
For e.g.: architecture str_data_decoder of data_decoder

is
ACC-VHD-STD 8.6 [RULE] Architecture of type RTL should be prefixed with “rtl_”, followed by it’s
entity name
For e.g.: architecture rtl_data_decoder of data_decoder

is
ACC-VHD-STD 8.7 [RULE] Entity and all its architectures shall be in a single file
ACC-VHD-STD 8.8 [REC] Order of the port signal in ENTITY shall be in the following order
Inputs:
1.Clocks
2.Resets
3.Enables
4.Other control signals
5.data and address lines
Outputs:
1.Clocks
2.Resets
3.Enables
5.data
Port names must be declared in the following order based on modes
1.IN
2.OUT
3.INOUT

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4.BUFFER
5.LINKAGE
For e.g.:
port (
clk_sys : in std_logic; -- System clock
rst_a : in std_logic; -- async. global reset
sclin : in std_logic; -- SCL input signal
sdain : in std_logic; -- SDA input signal
nextsda : in std_logic; -- Input for SDA output register
sdaout : out std_logic; -- SDA output signal
sdain_sync: out std_logic; -- Synchronized SDA input signal
start : out std_logic; -- Start condition detected
stop : out std_logic; -- stop conditions detected
rise_edge : out std_logic; -- Rising edge detected
fall_edge : out std_logic -- Falling edges detected
);
ACC-VHD-STD 8.9 [REC] Order of the port signal in COMPONENT shall be in the following order
Inputs:
1.Clocks
2.Resets
3.Enables
Outputs:
1.Clocks
2.Resets
3.Enables
5.data
1.IN
2.OUT

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3.INOUT
4.BUFFER
5.LINKAGE
ACC-VHD-STD 8.10 [REC] Order of the port signal in port-mapping shall be in the following order
Inputs:
1.Clocks
2.Resets
3.Enables
Outputs:
1.Clocks
2.Resets
3.Enables
5.data
1.IN
2.OUT
3.INOUT
4.BUFFER
5.LINKAGE
ACC-VHD-STD 8.11 [RULE] Ports of mode BUFFER or LINKAGE shall not be used in the
synthesizable designs
ACC-VHD-STD 8.12 [RULE] The port in an entity port declaration shall not be a guarded port.
Furthermore, the declaration shall not impose a range constraint on

the port nor can it alter the resolution of the port from that defined in
the standard logic package.
ACC-VHD-STD 8.13 [RULE] Do not use underscore characters ‘_’ in the entity port declaration for
the top-level entity of a HARD macro.
Note: The reason for the rule above is that VITAL uses underscores as
separators to construct names for SDF back-annotation from the SDF
entries.

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ACC-VHD-STD 8.14 [RULE] Port names shall have same rules as the signals
12.3.4 Signals and Variables

ACC-VHD-STD 9.1 [RULE] Name of all signals shall be in lower case
ACC-VHD-STD 9.2 [RULE] Name of all variables shall be in lower case
ACC-VHD-STD 9.3 [RULE] Do not duplicate signal name
ACC-VHD-STD 9.4 [RULE] There shall not be any unused variables/signals
ACC-VHD-STD 9.5 [RULE] Do not duplicate variable name
ACC-VHD-STD 9.6 [RULE] Name of the signal/variable shall describe the functionality
ACC-VHD-STD 9.7 [RULE] Variable name shall start with character ‘v’
For e.g.: variable vdata : std_logic;
ACC-VHD-STD 9.8 [RULE] Length of signal name shall be at least 4 characters, and shall not
ACC-VHD-STD 9.9 [RULE] Length of variable name shall be at least 4 characters, and shall not
ACC-VHD-STD 9.10 [RULE] Tri-state internal signal name shall be suffixed with “_z”
For e.g.: signal bus_z : std_logic;
ACC-VHD-STD 9.11 [RULE] Asynchronous signal name shall be suffixed with “_a”
For e.g.: signal clear_a : std_logic;
ACC-VHD-STD 9.12 [RULE] Nth phase of the signal shall be suffixed with “_pn”

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For e.g.:
signal enable_p1 : std_logic;
DELAY_PROS:process(clk_sys,rst_dsp_n)
begin
if(rst_dsp_n=’0’)
enable_p1 <= ’0’;
elsif(clk_sys=’1’ and clk_sys’event)
enable_p1 <= enable_a;
enable_p2 <= enable_p1;
enable_p3 <= enable_p2;
end if;
end process DELAY_PROS;
ACC-VHD-STD 9.13 [RULE] Register (flip-flop) output shall be suffixed with “_r”
For e.g.: signal count_r: std_logic_vector(2 downto

0);
REG_PROS:process(clk_sys,rst_dsp_n)
begin
count_r <=”000”;
count_r <= count_nxt;
end if;
end process REG_PROS;
Where, “count_nxt” output of a combinatorial

logic.
ACC-VHD-STD 9.14 [RULE] Use a consistent name for the clock signal as clk. Use “clk_” as prefix,
if there are more than one clock signals
For e.g.: signal clk_i2c_pll: std_logic;
ACC-VHD-STD 9.15 [RULE] Use the same name for the reset throughout the hierarchy of the

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design
ACC-VHD-STD 9.16 [RULE] Reset (both active high and active low) name shall be prefixed with
“rst_”
For e.g.: signal rst_dsp: std_logic;
ACC-VHD-STD 9.17 [RULE] Active low reset shall be suffixed with “_n”
ACC-VHD-STD 9.18 [RULE] Active low signals/variables should be suffixed with “_n”
For e.g.: signal mbist_n: std_logic;
ACC-VHD-STD 9.19 [RULE] Hard coded numeric values shall not be used in the design
For e.g.:
constant C0_4BITS : std_logic_vector(3
downto 0):= “0000”;
constant C1_4BITS : std_logic_vector(3
downto 0):= “0001”;
COUTING_PROS:process(rst_n,clk_sys)
begin
if rst_n=’0’ then
counter<= C0_4BITS;
elsif clk_sys=’1’ and clk_sys’event then
counter<= counter+ C1_4BITS;
end if;
end process COUTING_PROS;
ACC-VHD-STD 9.20 [RULE] Shall use either (x downto 0) or (0 to x) for all multi-bit signals
throughout the design
For e.g.:
signal data_bus :std_logic_vector(0 to 15);
signal addr_bus :std_logic_vector(0 to 7);
or
signal data_bus:std_logic_vector(15 downto 0);
signal addr_bus:std_logic_vector( 7 downto 0);
ACC-VHD-STD 9.21 [REC] Name of the false path signals shall be suffixed with “_fp”
ACC-VHD-STD 9.22 [REC] Name of the signal before being registered into a register with the
same name should be suffixed with “_nxt”

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For e.g.:
signal count_nxt: std_logi_vector(2 downto 0);
count_nxt <= count_r + 1 when count_r <= “110”
else “000”;
REG_PROS:process(clk_sys,rst_dsp_n)
begin
count_r <=“000”;
count_r <= count_nxt;
end if;
ACC-VHD-STD 9.23 [REC] Use a distinctive suffix for state variable names. Recommended
names are <name>_cs for the current state and <name>_ns for the
next state.
For e.g.:
signal state_cs : std_logic_vector(1 to 0);
signal state_ns : std_logic_vector(1 to 0);
ACC-VHD-STD 9.24 [REC] When writing synthesizable code, use signals instead of variables to
ensure that the simulation behavior of the pre-synthesis design
matches that of the post-synthesis netlist.
If the simulation speed can be significantly improved by using

variables, then it is certainly appropriate to do so.
12.3.5 Process and Instances

ACC-VHD-STD 10.1 [RULE] Instance names shall be prefixed with “U_” and shall be in uppercase
ACC-VHD-STD 10.2 [RULE] Length of instance name shall be at least 4 characters, and shall not

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For e.g.:
U_FIRST_INST: clock_generation
port map (
clk_sys => clk_sys,
rst_n => rst_n,
clk_out => clk_out
);
ACC-VHD-STD 10.3 [RULE] Each process shall have a label and label shall be suffixed with
“_PROS”
For e.g.:
REG_PROS: process(clk_sys)
begin
if clk_sys='1' and clk_sys'event then
if we_a='1' then
reg_r(addr_a) <= data_r;
end if;
end if;
ACC-VHD-STD 10.4 [RULE] Length of process label shall be at least 4 characters, and shall not
ACC-VHD-STD 10.5 [RULE] All the signals that are read in a combinational process shall be listed
in the sensitivity list
For e.g.:
COMB_PROS: process(inpt_a, inpt_b)
begin
out_y <= inpt_a xor inpt_b;
end process COMB_PROS;
ACC-VHD-STD 10.6 [RULE] For an asynchronous reset, the reset signal name shall be specified in
the sensitivity list of a process along with the clock name

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For e.g.:
ASYNC_RST_PROS: process(reset_n,clk_sys)
begin
if reset_n='0' then
reg_r(0) <= (others=>’0’);
reg_r(1) <= (others=>’0’);
elsif clk_sys='1' and clk_sys'event then
end if;
end process ASYNC_RST_PROS;
ACC-VHD-STD 10.7 [RULE] For a synchronous reset, the reset signal name shall not be specified
in the sensitivity list of a process along with the clock name
SYNC_RST_PROS: process(clk_sys)
begin
if clk_sys='1' and clk_sys'event then
if reset_n='0' then
reg_r(0) <= (others=>’0’);
reg_r(1) <= (others=>’0’);
else
end if;
end if;
end process SYNC_RST_PROS;
12.3.6 Types
ACC-VHD-STD 11.1 [RULE] User-defined type name shall be in uppercase
ACC-VHD-STD 11.2 [RULE] User-defined type name shall begin with a character
ACC-VHD-STD 11.3 [RULE] User-defined type name may contain numerals and underscores
ACC-VHD-STD 11.4 [RULE] Length of user-defined type name shall be at least 4 characters, and
shall not exceed 32 characters
ACC-VHD-STD 11.5 [RULE] User-defined type name shall not contain special characters except
underscore
For e.g.: type PATTERN_VECTOR_TYP array (0 to 61)

of std_logic;

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ACC-VHD-STD 11.6 [RULE] User-defined type name shall be suffixed with “_TYP”
For e.g.: type PATTERN_VECTOR_TYP array (0 to 61)

of std_logic;
ACC-VHD-STD 11.7 [REC] Number of sub-types should be limited to a maximum of 200
Using too many subtypes makes code difficult to understand
ACC-VHD-STD 11.8 [REC] Time type should not be used
There should not be any delay constants in RTL code. These delay
constants may lead to pre-synthesis simulation and post-synthesis
simulation results mismatch.
ACC-VHD-STD 11.9 [REC] Use enumerated data-types
Create an enumerated type to define the state vector of a state

machine
In VHDL, create an enumerated type for the state vector. In Verilog

use “define” statements to define the state vector

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For e.g.:
architecture str_state of example is
type STATE_TYP is (RESET,GO,STOP,DONE);
signal state_type :STATE_TYP ;
begin
P1_PROS:process(sig_1,sig_2,sig_3)
begin
if (sig_1=’0’ and sig_2=’0’)
state_type<= RESET;
elsif (sig_1=’0’ and sig_2=’1’)
state_type<=GO;
elsif(sig_1=’1’ and sig_3=’0’)
state_type<=STOP;
else
state_type<=DONE;
end if;
end process P1_PROS;
P2_PROS:process (state_type)
begin
case state_type is
when RESET => YELLOW<=’1’;
when GO => GREEN<=’1’;
when STOP => RED<=’0’;
when DONE => BLACK<=’0’;
end case;
end process P2_PROS;
end str_state;
12.3.7 Functions and Procedures

ACC-VHD-STD 12.1 [RULE] Function name shall be in uppercase

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For e.g.:
function ADD2_FUN (
addin1: std_logic_vector;
addin2: std_logic_vector)
return std_logic_vector is
begin
---body of the function
end ADD2_FUN;
ACC-VHD-STD 12.2 [RULE] Function name shall be suffixed with “_FUN”
ACC-VHD-STD 12.3 [RULE] Length of function name shall be at least 4 characters, and shall not
ACC-VHD-STD 12.4 [RULE] Procedure name shall be in uppercase
ACC-VHD-STD 12.5 [RULE] Procedure name shall be suffixed with “_PROR”
ACC-VHD-STD 12.6 [RULE] Length of procedure name shall be at least 4 characters, and shall not
ACC-VHD-STD 12.7 [REC] Use functions when possible, instead of repeating the same sections
of code. If possible, generalize the function to make it reusable.
12.3.8 Language
ACC-VHD-STD 13.1 [RULE] Shall comply with IEEE VHDL standard 1076-1993
ACC-VHD-STD 13.2 [RULE] VHDL keywords shall be in lowercase
ACC-VHD-STD 13.3 [RULE] VHDL or Verilog reserved words shall not be used as identifiers
ACC-VHD-STD 13.4 [RULE] Use only IEEE standard types
ACC-VHD-STD 13.5 [RULE] Use std_logic rather than std_ulogic. Likewise, use std_logic_vector
rather than std_ulogic_vector.
Because, the std_logic and std_logic_vector types provide the

resolution functions required for tri-state buses. The std_ulogic and
std_ulogic_vector types do not provide resolution functions
ACC-VHD-STD 13.6 [RULE] Do not use the type bit or bit_vector
ACC-VHD-STD 13.7 [REC] Use CASE statement instead of IF-THEN-ELSE statement.
Because, the IF-THEN-ELSE statement gets synthesized into a

priority encoder consuming more hardware; if priority is not required by
design then use CASE statement, which just does the multiplexing

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operation.
12.3.9 Constants, Generics, and Packages

ACC-VHD-STD 14.1 [RULE] Constant name shall be in uppercase
ACC-VHD-STD 14.2 [RULE] Constant name shall be prefixed with ‘C’
For e.g.: constant CRESET: std_logic:=’0’;
ACC-VHD-STD 14.3 [RULE] Constant name may contain numerals and underscores
ACC-VHD-STD 14.4 [RULE] Constant name shall not contain special characters except underscore
ACC-VHD-STD 14.5 [RULE] Length of constant name shall be at least 4 characters, and shall not
ACC-VHD-STD 14.6 [RULE] Generics name shall describe function
ACC-VHD-STD 14.7 [RULE] Generics name shall be in uppercase
ACC-VHD-STD 14.8 [RULE] Generics name shall be prefixed with “G_”
For e.g.: G_DATA_LEN: integer;
ACC-VHD-STD 14.9 [RULE] Length of generic name shall be at least 4 characters, and shall not
ACC-VHD-STD 14.10 [REC] Package shall contain constants, functions and procedures used in the
design. And it’s file name same shall be suffixed with _pkg.vhd
ACC-VHD-STD 14.11 [RULE] Package name should indicate the design with which it is associated.
ACC-VHD-STD 14.12 [RULE] Package name shall be same as the package file
ACC-VHD-STD 14.13 [RULE] Length of package name shall be at least 4 characters, and shall not
ACC-VHD-STD 14.14 [REC] If the number of constants in the design is more than 100, then there
shall be a separate constant’s package. The file name shall be
suffixed with “_const_pkg"
For e.g.: acc_dbb_const_pkg.vhd
ACC-VHD-STD 14.15 [RULE] Standard IEEE packages shall not be modified
ACC-VHD-STD 14.16 [REC] If the number of functions and procedures in the design is more than
10, then there shall be a separate function and procedure package.
The file name shall be suffixed with “_fun_pror_pkg"
For e.g.: acc_dbb_fun_pror_pkg.vhd

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ACC-VHD-STD 14.17 [RULE] Package and package-body shall be in the same file.
12.3.10 Readability
ACC-VHD-STD 15.1 [RULE] Explicit mapping (named association rather than positional
association) shall be used for ports and generics
For e.g.:
U_INIT_ACQ_CHANNELS: initch
generic map(
G_DATA_LEN => G_DATA_LEN
)
port map (
--Inputs
clk_sys => clk_sys,
rst_clk_sys_n_r => rst_clk_sys_n_r,
--outputs
start_process8 => start_process8,
start_process9 => start_process9
);
ACC-VHD-STD 15.2 [RULE] Each HDL statement shall be in a separate line
ACC-VHD-STD 15.3 [RULE] Number of characters in a line shall not exceed 132 characters
ACC-VHD-STD 15.4 [REC] Loops and arrays should be used to improve the readability of the
source code. For e.g.:
constant C_NUMBER_TAPS : integer:=4;

SHIFT_DLY_LP:for loop_i in 1 to(C_NUMBER_TAPS-
l)loop
delay(loop_i) := delay(loop_i -1);
end loop SHIFT_DLY_LP;
Arrays are significantly faster to simulate than ‘for’ loops.
ACC-VHD-STD 15.5 [REC] Sequential logic in the state machines, should use one process
without any combinational logic

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For e.g.: sequential process
REGS_PROS: process (rst_n, clk_sys)

begin
if rst_n = ’0’ then
cval_r <= (others => ’0’);
elsif rising_edge(clk_sys) then
cval_r <= val_a;
end if;
end process REGS_PROS;
ACC-VHD-STD 15.6 [REC] Complex intermediate signals in a sequential logic should be

implemented outside the process using concurrent signal assignments
or combinational process.
For e.g.:
val_a<= not(input_a and input_b )
or (input_c and input_d);
12.3.11 Portability
ACC-VHD-STD 16.1 [REC] Do not use generate statements. There is no equivalent construct in
Verilog-95.
ACC-VHD-STD 16.2 [REC] Do not use block constructs. There is no equivalent construct in
Verilog.
ACC-VHD-STD 16.3 [REC] For arithmetic components, use the DesignWare Foundation Library
(for ASIC designs).
12.4 Test bench
ACC-VHD-STD 17.1 [RULE] Test bench shall model the environment of the DUT
ACC-VHD-STD 17.2 [RULE] The same test bench shall be used for behavioural, and place and
route simulation
ACC-VHD-STD 17.3 [RULE] Single test bench shall be able to test multiple test cases
ACC-VHD-STD 17.4 [RULE] The PASS or FAIL verification status of the test case generation, shall
be automated
ACC-VHD-STD 17.5 [RULE] The test bench shall interact with the DUT, considering the timing
aspect of the design
ACC-VHD-STD 17.6 [REC] Use assertion statements to report the status of simulation during run-

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time
ACC-VHD-STD 17.7 [RULE] Test bench shall read the inputs of a test case from a file, and log the
results into a file
ACC-VHD-STD 17.8 [RULE] Name of the input file, and output log file shall be at least 4 characters
and maximum of 32 characters
12.5 Directory structure

ACC-VHD-STD 18.1 [RULE] There shall be 3 main directories called “Source,” “Synthesis,” and
“Simulation”
ACC-VHD-STD 18.2 [RULE] The “Source” directory shall contain “Design_files”, “Packages”, and
“Libraries”. (The block diagram is shown in Figure)
ACC-VHD-STD 18.3 [RULE] The “Design_files” sub-directory shall contain the Design RTL files.
ACC-VHD-STD 18.4 [REC] The “Packages” sub-directory shall contain the Design related
packages (which shall have functions, procedures, constants).
ACC-VHD-STD 18.5 [REC] The “Libraries” sub-directory shall contain the Design related libraries.
ACC-VHD-STD 18.6 [RULE] The “Synthesis” directory shall have sub-directories called as
“Scripts”, “Netlist”, ”Logs“, “Bitfile” and “Work”.
ACC-VHD-STD 18.7 [RULE] The “Scripts” sub-directory shall contain the synthesis specific scripts.
ACC-VHD-STD 18.8 [RULE] The “Netlist” sub-directory shall contain the design netlist, and SDF.
ACC-VHD-STD 18.9 [RULE] The “Logs” sub-directory shall contain the synthesis, translate, MAP,
and PAR reports.
ACC-VHD-STD 18.10 [REC] The “Bitfile” sub-directory shall contain the .bin, .bit, and .rbt files
ACC-VHD-STD 18.11 [RULE] The “Work” directory shall contain output files generated from
synthesis, translate, map and Place-and-Route tool.
ACC-VHD-STD 18.12 [RULE] The “Simulation” directory shall contain 7 sub-directories called
“Inputs”, “Libraries”, “TB”, “Scripts”, “RTL_res”, “Netlist_res”, and
“Work”.
ACC-VHD-STD 18.13 [RULE] The “Inputs” directory shall contain input stimulus file.
ACC-VHD-STD 18.14 [RULE] The “Libraries” directory shall contain simulation related library files.
ACC-VHD-STD 18.15 [RULE] The “TB” directory shall contain test bench files.
ACC-VHD-STD 18.16 [RULE] The “Scripts” sub-directory shall contain tool dependent scripts.
ACC-VHD-STD 18.17 [RULE] The “RTL_res” sub-directory shall contain the results of RTL

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simulation.
ACC-VHD-STD 18.18 [RULE] The “Netlist_res” sub-directory shall contain the result of netlist
simulation (post-layout simulation).
ACC-VHD-STD 18.19 [RULE] The “Work” sub-directory shall contain the compiled design libraries
and simulation specific files.
ACC-VHD-STD 18.20 [RULE] If design is targeted for many technologies, each technology should
have its own directory, and named with its technology name
ACC-VHD-STD 18.21 [RULE] Each version should have the separate directory

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Directory structure :
PROJECT NAME
Source Synthesis Simulation
Libraries Scripts
Logs
Design_files Packages TB RTL_res

Netlist Bitfile
Libraries Netlist_res
Scripts Work
Inputs Work
Figure 1: Directory structure
ASM008, Accord Standards Manual © Accord Software & Systems Pvt. Ltd.
37, Krishna Reddy Colony, Domlur layout
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------------------------------------------------------------------
--License Information : Accord Global Technology Solutions Private
Limited.
-- No. 72 & 73, K R Colony, Domlur Layout,
-- Licensed software. All rights reserved
--
-- Filename : reset_deassertion_synchrzr.vhd
--
-- Description : This file contains the logic to
-- synchronize the deassertion of the
-- reset w.r.t required clock.
--
--
--
--
-- Functions : None
--
--
-- Author : G.S.Naveen
--
-- Modification History : 1.0
-- Version Number| Date | Author |Change Request
-----------------|------------|-----------------|----------------
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity reset_deassertion_synchrzr is
generic(
G_ACTIVE_RST_STATE : std_logic
);
© Accord Software & Systems Pvt. Ltd.
Accord Confidential
12. Appendix A – Accord’s Synchronization Process

12.6 Reset synchronizer
12.6.1 VHDL Code

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port(
rst_to_be_synchrnzd : in std_logic;
clk_synch : in std_logic;
scan_mode : in std_logic;
rst_synch_a : out std_logic
);
end reset_deassertion_synchrzr;
architecture reset_deassertion_synchrzr of
reset_deassertion_synchrzr is
signal sync_ff_1_qout_r : std_logic;
component clk_mux
port(
clk_in_0 : in std_logic;
clk_in_1 : in std_logic;
clk_select : in std_logic;
clk_out : out std_logic
);
end component;
begin
--*********************************************************************
--**PROCESS NAME:SYNC_RST_REMOVAL_PROS
--**DESCRIPTION : Synchronize the reset removal of the w.r.t the given
--** clock
--** It's a three stage synchronizer
--*********************************************************************
SYNC_RST_REMOVAL_PROS : process(rst_to_be_synchrnzd,clk_synch)
begin
if(rst_to_be_synchrnzd = '0') then
sync_ff_1_qout_r <= G_ACTIVE_RST_STATE;

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elsif(clk_synch'event and clk_synch = '1') then

sync_ff_1_qout_r <= not G_ACTIVE_RST_STATE;
sync_ff_2_qout_r <= sync_ff_1_qout_r;
sync_ff_3_qout_r <= sync_ff_2_qout_r;
end if;
end process SYNC_RST_REMOVAL_PROS;
U_RESET_MUX : clk_mux
port map(
clk_in_0 => sync_ff_3_qout_r,
clk_in_1 => rst_to_be_synchrnzd,
clk_select => scan_mode,
clk_out => rst_synch_a
);
end reset_deassertion_synchrzr;
12.6.2 Instantiation template
U_SYNC_RESET : reset_deassertion_synchrzr
generic map(
G_ACTIVE_RST_STATE =>
)
port map(
rst_to_be_synchrnzd => ,
clk_synch => ,
scan_mode => ,
rst_synch_a =>
);
12.7 Single edge data synchronizer
12.7.1 VHDL Code

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------------------------------------------------------------------
--
-- Filename : single_edge_data_synchrnzr.vhd
--
-- synchronize the given edge of the
-- signal w.r.t required clock.
--
--
--
--
--
-- Functions : None
--
--
--
-----------------|------------|-----------------|----------------
-----------------------------------------------------------------
library ieee;
entity single_edge_data_synchrnzr is
generic(
G_EDGE_TO_BE_SYNCNZD : std_logic
ASM008 ); Controlled copy available in Intra-net Web Page and CM
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port(
data_sig_to_be_synchrnzd : in std_logic;
rst_clk_synch : in std_logic;
single_edge_synch_data_sig_r : out std_logic
);
end single_edge_data_synchrnzr;
architecture single_edge_data_synchrnzr of
single_edge_data_synchrnzr is
signal sync_edge_ff_1_qout_r : std_logic;
signal sync_dff_1_qout_r : std_logic;
begin
--*******************************************************************
--**PROCESS NAME:SYNC_EDGE_PROS
--**DESCRIPTION : Synchronize the given edge of the signal w.r.t the
--* given clock
--*******************************************************************
SYNC_EDGE_PROS : process(data_sig_to_be_synchrnzd,clk_synch)
begin
if(data_sig_to_be_synchrnzd = not(G_EDGE_TO_BE_SYNCNZD)) then
sync_edge_ff_1_qout_r <= not G_EDGE_TO_BE_SYNCNZD;
sync_edge_ff_1_qout_r <= G_EDGE_TO_BE_SYNCNZD;
end if;
end process SYNC_EDGE_PROS;
--********************************************************************
--**PROCESS NAME: DFF_EDGE_SYNC_PROS
--** clock
--********************************************************************
DFF_EDGE_SYNC_PROS : process(rst_clk_synch,clk_synch)
begin
if(rst_clk_synch = '0') then
sync_dff_1_qout_r <= G_EDGE_TO_BE_SYNCNZD;
sync_dff_2_qout_r <= G_EDGE_TO_BE_SYNCNZD;

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sync_dff_1_qout_r <= sync_edge_ff_1_qout_r;
sync_dff_2_qout_r <= sync_dff_1_qout_r;
end if;
end process DFF_EDGE_SYNC_PROS;
single_edge_synch_data_sig_r <= sync_dff_2_qout_r;
end single_edge_data_synchrnzr;
U_SINGL_EDG_SYNC3 : single_edge_data_synchrnzr
generic map(
G_EDGE_TO_BE_SYNCNZD =>
)
port map(
data_sig_to_be_synchrnzd => ,
rst_clk_synch => ,
clk_synch => ,
single_edge_synch_data_sig_r =>
);
12.8 Dual edge data synchronizer
12.8.1 VHDL Code

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------------------------------------------------------------------
--
-- Filename : dual_edge_data_synchrzr.vhd
--
-- synchronize the both the edges of the
-- signal w.r.t required clock.
--
--
--
--
--
-- Functions : None
--
--
--
-----------------|------------|-----------------|----------------
-----------------------------------------------------------------
library ieee;

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entity dual_edge_data_synchrzr is
generic(
G_ACTIVE_RST_STATE : std_logic
);
port(
data_sig_to_be_synchrnzd : in std_logic;
rst_clk_synch : in std_logic;
dual_edge_synch_data_out_r : out std_logic
);
end dual_edge_data_synchrzr;
architecture dual_edge_data_synchrzr of dual_edge_data_synchrzr is

begin
--********************************************************************
--**PROCESS NAME: DFF_EDGE_SYNC_PROS
--** clock
--** It's 2-stage synchronizer
--********************************************************************
DFF_EDGE_SYNC_PROS : process(rst_clk_synch,clk_synch)
begin
if(rst_clk_synch = '0') then
sync_dff_1_qout_r <= G_ACTIVE_RST_STATE;
sync_dff_2_qout_r <= G_ACTIVE_RST_STATE;
sync_dff_1_qout_r <= data_sig_to_be_synchrnzd;
sync_dff_2_qout_r <= sync_dff_1_qout_r;
end if;
end process DFF_EDGE_SYNC_PROS;
dual_edge_synch_data_out_r <= sync_dff_2_qout_r;
end dual_edge_data_synchrzr;

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U_DAT_SYNC1 : dual_edge_data_synchrzr
generic map(
G_ACTIVE_RST_STATE =>
)
port map(
data_sig_to_be_synchrnzd => ,
rst_clk_synch => ,
clk_synch => ,
dual_edge_synch_data_out_r =>
);

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Appendix B – VHDL code review checklist
Compliance
ID Standard Remarks
(Yes/No)
Trace-ability
The source code shall implement all the low level

ACC-VHD-STD 1.1
requirements correctly
The source code shall implement all the low level

ACC-VHD-STD 1.2
requirements completely
The source code shall not implement anything outside

ACC-VHD-STD 1.3
the low level requirements
The components shall have inputs as defined in low-

ACC-VHD-STD 1.4
level requirements
The components shall have outputs as defined in low-

ACC-VHD-STD 1.5
level requirements
The source code shall not contain any

ACC-VHD-STD 1.6
statement/component that cannot be verified
Any part of the code which cannot be tested

ACC-VHD-STD 1.7 (coverage), shall have the alternate means of
verification (analysis, review, etc.)
The source code shall be traceable to all the low-level

ACC-VHD-STD 1.8
requirements
Design
System (with sequential logic) shall have a global reset,

ACC-VHD-STD 2.1
which can initialise the system to a known state
Use only either synchronous or asynchronous type of

ACC-VHD-STD 2.2
resets throughout the system
Reset signal connected to reset of flip-flops shall not be used

ACC-VHD-STD 2.3 in the data-path.
i.e., The only logic function for the reset signal should

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be a direct clear of all flip-flops. Never use the reset

inputs of a flop to implement state machine
functionality. Reserving reset pins on flops for reset
only makes it easier to generate buffer trees for resets.
Each asynchronous reset de-assertion shall be

synchronized with the clock with which it is being used.
ACC-VHD-STD 2.4 Ensure that the tool used to synthesize the RTL is not
duplicating the synchronizer flip-flops due to fanout or
any other reason.
ACC-VHD-STD 2.5 Avoid internally generated resets
The internally generated resets should be used as

ACC-VHD-STD 2.6
synchronous resets
If a conditional reset is required, create a separate

signal for the reset signal, and isolate the conditional
ACC-VHD-STD 2.7
reset logic in a separate module at the top level of the
design.
It is preferred to have pulse stretching mechanism for

ACC-VHD-STD 2.8
synchronous resets
There should be a glitch elimination mechanism for

ACC-VHD-STD 2.9
asynchronous resets
ACC-VHD-STD 3.1 Avoid clocks in data-path
ACC-VHD-STD 3.2 Do not instantiate clock buffers in the RTL
ACC-VHD-STD 3.3 Avoid gated clocks
If the design requires a gated clock, model it in RTL

ACC-VHD-STD 3.4 using synchronous load registers. This will allow the
synthesis tool to insert the actual clock gating logic.
ACC-VHD-STD 3.5 Avoid flip-flops operating on both the edges of the clock
If the design must use a large number of both positive-

edge and negative-edge triggered flip-flops in your
ACC-VHD-STD 3.6
design, it may be useful to separate them into different
modules
ACC-VHD-STD 3.7 Have single clock per module
ACC-VHD-STD 3.8 Avoid internally generated clocks

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If the design must use a gated clock or an internally

ACC-VHD-STD 3.9
generated clock, keep the clock generation circuitry as
a separate module at the top level of the design.
Use synchronizers to transfer data between different

clock domains. Ensure that the tool used to synthesize
ACC-VHD-STD 4.1
the RTL is not duplicating the synchronizer flip-flops
due to fanout or any other reason.
Signals entering the synchronizer shall directly come

ACC-VHD-STD 4.2
from the output of a flip-flop
Whenever synchronizer is used in the design, it shall

ACC-VHD-STD 4.3 be separately defined and shall be used as a
component
Signal from faster clock domain, entering the slower

clock domain through a synchronizer, shall be held
ACC-VHD-STD 4.4
stable for multiple cycles of slower clock (depending on
the number of stages in the synchronizer)
If the signal from the source clock domain is not stable

for multiple cycles of destination clock, use the capture
ACC-VHD-STD 4.5 circuit to detect the activity on that signal and then
synchronize the captured signal with the destination
clock
Do not synchronize a signal from source clock domain,

ACC-VHD-STD 4.6
at multiple places, in the destination clock domain
Avoid convergence of more than one control signals

ACC-VHD-STD 4.7 from the source clock domain, in the destination clock
domain
Use a synchronized enable signal, or handshake signals, to

pass the multi-bit signals across clock domain.
ACC-VHD-STD 4.8
E.g. data enable, FIFO
ACC-VHD-STD 4.9 Avoid the multi-bit signals crossing clock domain
There shall be a constraint file associated with each

ACC-VHD-STD 4.10
design
The constraint file name shall be design name suffixed

ACC-VHD-STD 4.11
with _ucf

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The constraint file shall define the timing constraints

ACC-VHD-STD 4.12
and the location constraints for all the port signals.
ACC-VHD-STD 4.13 The constraint file shall have a header according to the
guideline
ACC-VHD-STD 7.1
ACC-VHD-STD 5.1 The enables for inputs and outputs shall be exclusive.
ACC-VHD-STD 5.2 Shall avoid latches in the design
Signals/variables shall not be initialised during

ACC-VHD-STD 5.3
declaration
There shall not be any combinational feedback loops in

ACC-VHD-STD 5.4
the design
ACC-VHD-STD 5.5 There shall not be any feed-throughs in the design
ACC-VHD-STD 5.6 Constants should not be initialised using expressions
ACC-VHD-STD 5.7 Avoid asynchronous logic in the synchronous design
ACC-VHD-STD 5.8 Avoid glue logic at top-level of the design
Avoid timing-exceptions (false-paths and multi-cycle-

ACC-VHD-STD 5.9
paths) in the design
ACC-VHD-STD 5.10 Register all the outputs of the design
For each sub-block of a hierarchical macro design,

ACC-VHD-STD 5.11
register all output signals from the sub-block.
Synthesis specific commands should be avoided in the

ACC-VHD-STD 5.12
source code
ACC-VHD-STD 5.13 Use technology independent libraries
Keep late-arriving signals with critical timing closest to the

output of a logic block.
ACC-VHD-STD 5.14
For example, use the late-arriving signal early in an if-
else block.
Keep memory interface pins at the top level of a

ACC-VHD-STD 5.15 macrocell to allow user choice of memory
implementation, interface and test.

Accord Confidential
Reduce the number flip-flops falling into meta-stable

ACC-VHD-STD 5.16
state
The last state in a state machine shall be:
“when others =>”
ACC-VHD-STD 5.17
Statement to encompass default states of all applicable
signals end case.
Coding
ACC-VHD-STD 6.1 File name shall be same as entity name.
File name shall not contain special characters except

ACC-VHD-STD 6.2
underscore
Length of file name shall be at least 4 characters, and

ACC-VHD-STD 6.3
File name shall be in lowercase and begin with a

ACC-VHD-STD 6.4
character
ACC-VHD-STD 6.5 Name of the file should indicate the functionality
Name of the package file shall be suffixed with “_pkg”

ACC-VHD-STD 6.6
For e.g.: math_pkg.vhd
Name of the library file shall be suffixed with ”_lib”.

ACC-VHD-STD 6.7
For e.g.: ovrload_lib.vhd
Name of the configuration file shall be suffixed with “_cfg”

ACC-VHD-STD 6.8
For e.g.: testcase1_cfg.vhd
ACC-VHD-STD 6.9 Configurations shall be in a separate file
ACC-VHD-STD 6.10 All file names shall have an extension ’. vhd’
Test bench file name shall be prefixed with 'tb_'

ACC-VHD-STD 6.11
For e.g.: tb_controller.vhd
ACC-VHD-STD 6.12 File name may contain numerals and underscores
ACC-VHD-STD 6.13 Number of lines in a file should not exceed 1000
ACC-VHD-STD 7.1 Each file shall have file header at the beginning of the file

Accord Confidential
and header shall start at the first line and first column of the
file.
Functions/Procedure shall have a header preceding the

ACC-VHD-STD 7.2
function/procedure definition
Process shall have a process header preceding the

ACC-VHD-STD 7.3
process definition
ACC-VHD-STD 7.4 Use comments to describe group of ports
ACC-VHD-STD 7.5 There shall be no dangling or irrelevant comment.
ACC-VHD-STD 7.6 For indentation use 2 spaces. Do not use tabs
Use comment appropriately to explain process,

functions, procedures and declarations of types and
ACC-VHD-STD 7.7 subtypes. Use comments to explain ports, signals and
variables or group of signals or variables. Comments
for timing behaviour should be present
ACC-VHD-STD 7.8 There should be comments for each statement
The comments shall be descriptive and not just direct

ACC-VHD-STD 7.9
translations or repetitions of the VHDL code.
ACC-VHD-STD 8.1 Entity name should depict the functionality
Top entity port signals shall be of std_logic or

ACC-VHD-STD 8.2
std_logic_vector type
Length of entity name shall be at least 4 characters,

ACC-VHD-STD 8.3
and shall not exceed 32 characters
Architecture of type Simulation should be prefixed with

“sim_”, followed by it’s entity name
ACC-VHD-STD 8.4
For e.g.: architecture sim_data_decoder of
data_decoder is
Architecture of type Structural should be prefixed with “str_”,

followed by it’s entity name
ACC-VHD-STD 8.5
For e.g.: architecture str_data_decoder of
data_decoder is

Accord Confidential
Architecture of type RTL should be prefixed with “rtl_”,

ACC-VHD-STD 8.6 followed by it’s entity name
For e.g.: architecture rtl_data_decoder of

data_decoder is
ACC-VHD-STD 8.7 Entity and all its architectures shall be in a single file
Order of the port signal in ENTITY shall be in the following

order
Inputs:
1.Clocks
2.Resets
3.Enables
Outputs:
1.Clocks
ACC-VHD-STD 8.8
2.Resets
3.Enables
5.data
Port names must be declared in the following order based on

modes
1.IN
2.OUT
3.INOUT
4.BUFFER
5.LINKAGE
Order of the port signal in COMPONENT shall be in the

following order
ACC-VHD-STD 8.9 Inputs:
1.Clocks
2.Resets
3.Enables

Accord Confidential

Outputs:
1.Clocks
2.Resets
3.Enables
5.data

modes
1.IN
2.OUT
3.INOUT
4.BUFFER
5.LINKAGE
Order of the port signal in port-mapping shall be in the

following order
Inputs:
1.Clocks
2.Resets
3.Enables
ACC-VHD-STD 8.10
Outputs:
1.Clocks
2.Resets
3.Enables
5.data

modes
1.IN
2.OUT

Accord Confidential
3.INOUT
4.BUFFER
5.LINKAGE
Ports of mode BUFFER or LINKAGE shall not be used

ACC-VHD-STD 8.11
in the synthesizable designs
The port in an entity port declaration shall not be a guarded

port.
ACC-VHD-STD 8.12 Furthermore, the declaration shall not impose a range

constraint on the port nor can it alter the resolution of
the port from that defined in the standard logic
package.
Do not use underscore characters ‘_’ in the entity port

ACC-VHD-STD 8.13
declaration for the top-level entity of a HARD macro.
ACC-VHD-STD 8.14 Port names shall have same rules as the signals
ACC-VHD-STD 9.1 Name of all signals shall be in lower case
ACC-VHD-STD 9.2 Name of all variables shall be in lower case
ACC-VHD-STD 9.3 Do not duplicate signal name
ACC-VHD-STD 9.4 There shall not be any unused variables/signals
ACC-VHD-STD 9.5 Do not duplicate variable name
Name of the signal/variable shall describe the

ACC-VHD-STD 9.6
functionality
Variable name shall start with character ‘v’

ACC-VHD-STD 9.7
For e.g.: variable vdata : std_logic;
Length of signal name shall be at least 4 characters,

ACC-VHD-STD 9.8
Length of variable name shall be at least 4 characters,

ACC-VHD-STD 9.9
Tri-state internal signal name shall be suffixed with “_z”

ACC-VHD-STD 9.10
For e.g.: signal bus_z : std_logic;

Accord Confidential
Asynchronous signal name shall be suffixed with “_a”

ACC-VHD-STD 9.11
For e.g.: signal clear_a : std_logic;
ACC-VHD-STD 9.12 Nth phase of the signal shall be suffixed with “_pn”
ACC-VHD-STD 9.13 Register (flip-flop) output shall be suffixed with “_r”
Use a consistent name for the clock signal as clk. Use “clk_”
as prefix, if there are more than one clock signals
ACC-VHD-STD 9.14
For e.g.: signal clk_i2c_pll: std_logic;
Use the same name for the reset throughout the

ACC-VHD-STD 9.15
hierarchy of the design
Reset (both active high and active low) name shall be

prefixed with “rst_”
ACC-VHD-STD 9.16
For e.g.: signal rst_dsp: std_logic;
ACC-VHD-STD 9.17 Active low reset shall be suffixed with “_n”
Active low signals/variables should be suffixed with “_n”

ACC-VHD-STD 9.18
For e.g.: signal mbist_n: std_logic;
ACC-VHD-STD 9.19 Hard coded numeric values shall not be used in the design
Shall use either (x downto 0) or (0 to x) for all multi-bit

ACC-VHD-STD 9.20
signals throughout the design
Name of the false path signals shall be suffixed with

ACC-VHD-STD 9.21
“_fp”
Name of the signal before being registered into a register

ACC-VHD-STD 9.22
with the same name should be suffixed with “_nxt”
Use a distinctive suffix for state variable names.

ACC-VHD-STD 9.23 Recommended names are <name>_cs for the current state
and <name>_ns for the next state.
When writing synthesizable code, use signals instead of

variables to ensure that the simulation behavior of the pre-
synthesis design matches that of the post-synthesis netlist.
ACC-VHD-STD 9.24
If the simulation speed can be significantly improved by
using variables, then it is certainly appropriate to do so.

Accord Confidential
Instance names shall be prefixed with “U_” and shall be

ACC-VHD-STD 10.1
in uppercase
Length of instance name shall be at least 4 characters, and

ACC-VHD-STD 10.2
Each process shall have a label and label shall be suffixed

ACC-VHD-STD 10.3
with “_PROS”
Length of process label shall be at least 4 characters,

ACC-VHD-STD 10.4
All the signals that are read in a combinational process shall

ACC-VHD-STD 10.5
be listed in the sensitivity list
For an asynchronous reset, the reset signal name shall be

ACC-VHD-STD 10.6 specified in the sensitivity list of a process along with the
clock name
For a synchronous reset, the reset signal name shall not be

ACC-VHD-STD 10.7 specified in the sensitivity list of a process along with the
clock name
ACC-VHD-STD 11.1 User-defined type name shall be in uppercase
ACC-VHD-STD 11.2 User-defined type name shall begin with a character
User-defined type name may contain numerals and

ACC-VHD-STD 11.3
underscores
Length of user-defined type name shall be at least 4

ACC-VHD-STD 11.4
characters, and shall not exceed 32 characters
User-defined type name shall not contain special characters

except underscore
ACC-VHD-STD 11.5
For e.g.: type PATTERN_VECTOR_TYP array (0
to 61) of std_logic;
User-defined type name shall be suffixed with “_TYP”

ACC-VHD-STD 11.6
For e.g.: type PATTERN_VECTOR_TYP array (0
to 61) of std_logic;
Number of sub-types should be limited to a maximum of 200

ACC-VHD-STD 11.7
Using too many subtypes makes code difficult to
understand

Accord Confidential
Time type should not be used
There should not be any delay constants in RTL code.

ACC-VHD-STD 11.8
These delay constants may lead to pre-synthesis
simulation and post-synthesis simulation results
mismatch.
Use enumerated data-types
Create an enumerated type to define the state vector of a

ACC-VHD-STD 11.9 state machine
In VHDL, create an enumerated type for the state vector. In

Verilog, use “define” statements to define the state vector
ACC-VHD-STD 12.1 Function name shall be in uppercase
ACC-VHD-STD 12.2 Function name shall be suffixed with “_FUN”
Length of function name shall be at least 4 characters,

ACC-VHD-STD 12.3
ACC-VHD-STD 12.4 Procedure name shall be in uppercase
ACC-VHD-STD 12.5 Procedure name shall be suffixed with “_PROR”
Length of procedure name shall be at least 4

ACC-VHD-STD 12.6
characters, and shall not exceed 32 characters
Use functions when possible, instead of repeating the

ACC-VHD-STD 12.7 same sections of code. If possible, generalize the
function to make it reusable.
ACC-VHD-STD 13.1 Shall comply with IEEE VHDL standard 1076-1993
ACC-VHD-STD 13.2 VHDL keywords shall be in lowercase
VHDL or Verilog reserved words shall not be used as

ACC-VHD-STD 13.3
identifiers
ACC-VHD-STD 13.4 Use only IEEE standard types
Use std_logic rather than std_ulogic. Likewise, use

std_logic_vector rather than std_ulogic_vector.
ACC-VHD-STD 13.5
Because, the std_logic and std_logic_vector types
provide the resolution functions required for tri-state
buses. The std_ulogic and std_ulogic_vector types do
Accord Confidential
not provide resolution functions
ACC-VHD-STD 13.6 Do not use the type bit or bit_vector
Use CASE statement instead of IF-THEN-ELSE statement.
Because, the IF-THEN-ELSE statement gets

ACC-VHD-STD 13.7 synthesized into a priority encoder consuming more
hardware; if priority is not required by design then use
CASE statement, which just does the multiplexing
operation.
ACC-VHD-STD 14.1 Constant name shall be in uppercase
Constant name shall be prefixed with ‘C’

ACC-VHD-STD 14.2
For e.g.: constant CRESET:
std_logic:=’0’;
ACC-VHD-STD 14.3 Constant name may contain numerals and underscores
Constant name shall not contain special characters

ACC-VHD-STD 14.4
except underscore
Length of constant name shall be at least 4 characters,

ACC-VHD-STD 14.5
ACC-VHD-STD 14.6 Generics name shall describe function
ACC-VHD-STD 14.7 Generics name shall be in uppercase
Generics name shall be prefixed with “G_”

ACC-VHD-STD 14.8
For e.g.: G_DATA_LEN: integer;
Length of generic name shall be at least 4 characters,

ACC-VHD-STD 14.9
Package shall contain constants, functions and

ACC-VHD-STD 14.10 procedures used in the design. And it’s file name same
shall be suffixed with _pkg.vhd
Package name should indicate the design with which it

ACC-VHD-STD 14.11
is associated.
ACC-VHD-STD 14.12 Package name shall be same as the package file

Accord Confidential
Length of package name shall be at least 4 characters,

ACC-VHD-STD 14.13
If the number of constants in the design is more than 100,

then there shall be a separate constant’s package. The file
ACC-VHD-STD 14.14 name shall be suffixed with “_const_pkg"
For e.g.: acc_dbb_const_pkg.vhd
ACC-VHD-STD 14.15 Standard IEEE packages shall not be modified
If the number of functions and procedures in the design is

more than 10, then there shall be a separate function and
procedure package. The file name shall be suffixed with
ACC-VHD-STD 14.16 “_fun_pror_pkg"
For e.g.: acc_dbb_fun_pror_pkg.vhd
ACC-VHD-STD 14.17 Package and package-body shall be in the same file.
Explicit mapping (named association rather than positional

ACC-VHD-STD 15.1
association) shall be used for ports and generics
ACC-VHD-STD 15.2 Each HDL statement shall be in a separate line
Number of characters in a line shall not exceed 132

ACC-VHD-STD 15.3
characters
Loops and arrays should be used to improve the readability

of the source code. For e.g.:
ACC-VHD-STD 15.4
Arrays are significantly faster to simulate than ‘for’
loops.
Sequential logic in the state machines, should use one

ACC-VHD-STD 15.5
process without any combinational logic
Complex intermediate signals in a sequential logic should be

ACC-VHD-STD 15.6 implemented outside the process using concurrent signal
assignments or combinational process.
Do not use generate statements. There is no equivalent

ACC-VHD-STD 16.1
construct in Verilog-95.
Do not use block constructs. There is no equivalent

ACC-VHD-STD 16.2
construct in Verilog.
ACC-VHD-STD 16.3 For arithmetic components, use the DesignWare

Accord Confidential
Foundation Library (for ASIC designs).
Test bench
ACC-VHD-STD 17.1 Test bench shall model the environment of the DUT
The same test bench shall be used for behavioural, and

ACC-VHD-STD 17.2
place and route simulation
Single test bench shall be able to test multiple test

ACC-VHD-STD 17.3
cases
The PASS or FAIL verification status of the test case

ACC-VHD-STD 17.4
generation, shall be automated
The test bench shall interact with the DUT, considering

ACC-VHD-STD 17.5
the timing aspect of the design
Use assertion statements to report the status of

ACC-VHD-STD 17.6
simulation during run-time
Test bench shall read the inputs of a test case from a

ACC-VHD-STD 17.7
file, and log the results into a file
Name of the input file, and output log file shall be at

ACC-VHD-STD 17.8
least 4 characters and maximum of 32 characters
Directory Structure
There shall be 3 main directories called “Source,”

ACC-VHD-STD 18.1
“Synthesis,” and “Simulation”
The “Source” directory shall contain “Design_files”,

ACC-VHD-STD 18.2 “Packages”, and “Libraries”. (The block diagram is
shown in Figure)
The “Design_files” sub-directory shall contain the

ACC-VHD-STD 18.3
Design RTL files.
The “Packages” sub-directory shall contain the Design

ACC-VHD-STD 18.4 related packages (which shall have functions,
procedures, constants).
The “Libraries” sub-directory shall contain the Design

ACC-VHD-STD 18.5
related libraries.
ACC-VHD-STD 18.6 The “Synthesis” directory shall have sub-directories

Accord Confidential
called as “Scripts”, “Netlist”, ”Logs“, “Bitfile” and “Work”.
The “Scripts” sub-directory shall contain the synthesis

ACC-VHD-STD 18.7
specific scripts.
The “Netlist” sub-directory shall contain the design

ACC-VHD-STD 18.8
netlist, and SDF.
The “Logs” sub-directory shall contain the synthesis,

ACC-VHD-STD 18.9
translate, MAP, and PAR reports.
The “Bitfile” sub-directory shall contain the .bin, .bit,

ACC-VHD-STD 18.10
and .rbt files
The “Work” directory shall contain output files

ACC-VHD-STD 18.11 generated from synthesis, translate, map and Place-
and-Route tool.
The “Simulation” directory shall contain 7 sub-

ACC-VHD-STD 18.12 directories called “Inputs”, “Libraries”, “TB”, “Scripts”,
“RTL_res”, “Netlist_res”, and “Work”.
ACC-VHD-STD 18.13 The “Inputs” directory shall contain input stimulus file.
The “Libraries” directory shall contain simulation related

ACC-VHD-STD 18.14
library files.
ACC-VHD-STD 18.15 The “TB” directory shall contain test bench files.
The “Scripts” sub-directory shall contain tool dependent

ACC-VHD-STD 18.16
scripts.
The “RTL_res” sub-directory shall contain the results of

ACC-VHD-STD 18.17
RTL simulation.
The “Netlist_res” sub-directory shall contain the result

ACC-VHD-STD 18.18
of netlist simulation (post-layout simulation).
The “Work” sub-directory shall contain the compiled

ACC-VHD-STD 18.19
design libraries and simulation specific files.
If design is targeted for many technologies, each

ACC-VHD-STD 18.20 technology should have its own directory, and named
with its technology name
ACC-VHD-STD 18.21 Each version should have the separate directory


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Accord’s Standards Manual Issue: 1.

VHDL Coding Standards

ASM008 Controlled copy available in Intra-net Web Page and CM

VHDL Coding Standards

WRITTEN BY: HARISH A H.

PROJECT LEADER – GNSS TECHNOLOGY

APPROVED BY: RAKESH A. NAYAK

SR. MANAGER – GNSS TECHNOLOGY

RELEASED BY: B SHYAMALA

SR. MANAGER – QUALITY ASSURANCE

ASM008 Controlled copy available in Intra-net Web Page and CM

VHDL Coding Standards

4 Terms and Definitions ................................................................................................................................ 5

6 Outstanding issues ..................................................................................................................................... 6

7 Document Control ....................................................................................................................................... 6

12 VHDL Coding Guidelines ............................................................................................................................ 7

Appendix A – Accord’s Synchronization Process ................................................................................................ 33

Appendix B – VHDL code review checklist............................................................................................................ 44

ASM008 Controlled copy available in Intra-net Web Page and CM

VHDL Coding Standards

Figure 1: Directory structure ................................................................................................................... 32

ASM008 Controlled copy available in Intra-net Web Page and CM

VHDL Coding Standards

In this document, the following conventions for guidelines apply,

Rules [RULE] are guidelines that shall be followed by all designers.

➢ European Space Agency, “VHDL Modelling Guidelines,” Issue 1, 1994

➢ SC-180, RTCA/DO-254, “Design Assurance Guidance for Airborne Electronic Hardware,”

➢ Accord, ASM012 – FPGA Requirements, Design, Validation and Verification Standards

4 Terms and Definitions

ACC-VHD-STD ACOORD – VHDL - Standard

DUT Design Under Test

ASM008 Controlled copy available in Intra-net Web Page and CM

VHDL Coding Standards

HDL Hardware Description Language

ASM008 Controlled copy available in Intra-net Web Page and CM

VHDL Coding Standards

12 VHDL Coding Guidelines

ASM008 Controlled copy available in Intra-net Web Page and CM

VHDL Coding Standards

Note: Duplicating synchronizer flip-flops leads to functionality failure. As

ACC-VHD-STD 2.5 [REC] Avoid internally generated resets

ACC-VHD-STD 3.2 [RULE] Do not instantiate clock buffers in the RTL

ACC-VHD-STD 3.3 [REC] Avoid gated clocks

ACC-VHD-STD 3.7 [REC] Have single clock per module

ACC-VHD-STD 3.8 [REC] Avoid internally generated clocks

12.2.3 Multiple Clocks

Note: Duplicating synchronizer flip-flops leads to functionality failure. As

ASM008 Controlled copy available in Intra-net Web Page and CM

VHDL Coding Standards

E.g. data enable, FIFO

ACC-VHD-STD 5.2 [RULE] Shall avoid latches in the design

ACC-VHD-STD 5.3 [RULE] Signals/variables shall not be initialised during declaration

ACC-VHD-STD 5.6 [RULE] Constants should not be initialised using expressions

ASM008 Controlled copy available in Intra-net Web Page and CM

VHDL Coding Standards

ACC-VHD-STD 5.7 [REC] Avoid asynchronous logic in the synchronous design

ACC-VHD-STD 5.8 [REC] Avoid glue logic at top-level of the design

ACC-VHD-STD 5.10 [REC] Register all the outputs of the design

ACC-VHD-STD 5.13 [REC] Use technology independent libraries

For example, use the late-arriving signal early in an if-else block.

ASM008 Controlled copy available in Intra-net Web Page and CM

VHDL Coding Standards

ACC-VHD-STD 6.1 [RULE] File name shall be same as entity name.