HCMC University of Technology and Education

FACULTY FOR HIGH QUALITY TRAINING

ELECTRONIC PRINCIPLES
www.hcmute.edu.vn
 I. Introduction

FET: Field-Effect Transistor

➔JFET: Junction Field-Effect Transistor
➔MOSFET: Metal Oxide Semiconductor
Field-Effect Transistor
➔IGBT: Insulated Gate Bipolar Transistor

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 I. Introduction
▪ The term field-effect relates to the depletion region
formed in the channel of an FET as a result of a voltage
applied on one of its terminals (gate)
▪ It is a voltage-controlled device, where the voltage
between two of the terminals (gate and source)
controls the current through the device
▪ FETs are the preferred device in low-voltage switching
applications because they are generally faster than
BJTs when turned on and off. The IGBT is generally
used in high-voltage switching applications.
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 II. JFET
Basic Structure and symbol

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 II. JFET
Basic Structure and symbol

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 II. JFET
Basic Structure and symbol

Current-controlled device Voltage-controlled device

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 II. JFET
Basic Structure and symbol

JFET versus BJT.

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 II. JFET
Basic Structure and symbol

ID

IG = 0 IS

IG = 0, ID = IS

Voltage-controlled device 8
 II. JFET
Basic operation

Operating
with a
reverse-
biased pn
junction to
control
current in a
channel
A biased n-channel JFET
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 II. JFET
Basic operation

JFET with VGS = 0 V and a variable VDS (VDD)

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 II. JFET
Basic operation

JFET with VGS = 0 V and a variable VDS (VDD)

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 II. JFET
Basic operation

JFET with VGS = 0 V and a variable VDS (VDD)

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 II. JFET
Basic operation

The drain characteristic curve of a JFET for

VGS 0 showing pinch-off voltage
JFET with VGS = 0 V and a variable VDS (VDD)
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 II. JFET
Basic operation

Shockley’s equation:

JFET with VGS < 0 V 15

 II. JFET
Basic operation
JFET with VGS < 0 V
When VGS =VP, ID = 0 mA
When VGS = 0 V, ID = IDSS

Shockley’s equation:

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 III. JFET BIASING
1. Self-Bias IG = 0 ➔ VRG = 0
➔ VG = 0
VG = VGS + VRS
0 = VGS + VRS
VGS = - VRS
VGS = - ID*RS

VDD = VRD + VDS + VRS

VDS = VDD - ID*(RD +RS)
VDD = ID*RD + VDS + ID*RS
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III. JFET BIASING
1. Self-Bias

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 III. JFET BIASING
2. Fixed-Bias configuration
VGS = - VGG
VDD = VRD + VDS VDD = ID*RD + VDS

VDS = VDD - ID*RD

VGS = - VGG 19
 III. JFET BIASING
2. Fixed-Bias configuration
IDSS=10mA, VP=-4V

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III. JFET BIASING
3. Voltage-Divider Bias

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 III. JFET BIASING
3. Voltage-Divider Bias

VDD = VRD + VDS + VRS

VDS = VDD - ID*(RD +RS)
VDD = ID*RD + VDS + ID*RS

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IDSS=10mA, VP= - 4V
Deternine Q(ID, VDS),
VRD, VRS, VD, VS.

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IV. JFET SMALL-SIGNAL AMPLIFIERS

1. JFET AC Equivalent Circuit

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 IV. JFET SMALL-SIGNAL AMPLIFIERS

2. Transconductance factor, gm

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IV. JFET SMALL-SIGNAL AMPLIFIERS
3. JFET Fixed-bias Configuration

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 IV. JFET SMALL-SIGNAL AMPLIFIERS
3. JFET Fixed-bias Configuration

Zin = RG AV = VO / Vin = - gm*(RD//RL)

ZO = RD Vin = VRG = Vgs
V0= VRD//RL = - Id*(RD//RL)
V0= VRD//RL = - gm*Vgs*(RD//RL)
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For the circuits shown in the following figures, deternine Q(ID, VDS), ZI, ZO, AV
Figure 2.24: IDSS=10mA, VP=-4V,

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 IV. JFET SMALL-SIGNAL AMPLIFIERS
4. JFET self-bias Configuration with bypassed CS
+VDD

AV = VO / Vin = - gm*(RD//RL)
Zin = RG
ZO = RD Vin = VRG = Vgs
V0= VRD//RL = - Id*(RD//RL)
V0= VRD//RL = - gm*Vgs*(RD//RL) 31
 IV. JFET SMALL-SIGNAL AMPLIFIERS
4. JFET self-bias Configuration without CS
+VDD

AV = VO / Vin = - gm*(RD//RL) / (1+ gm*RS)

Zin = RG
Vin = VRG = Vgs + VRS
ZO = RD Vin = VRG = Vgs + Id*RS = Vgs + gm*Vgs*RS
V0= VRD//RL = - Id*(RD//RL)
V0= VRD//RL = - gm*Vgs*(RD//RL)
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IV. JFET SMALL-SIGNAL AMPLIFIERS
4. JFET self-bias Configuration
+V without bypassed CS
DD

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IV. JFET SMALL-SIGNAL AMPLIFIERS

5. JFET voltage-divider
Configuration

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Figure 2.25: IDSS=12mA, VP=-6V
Q(ID, VDS), ZI, ZO, AV ????
VDD = 18 V

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