Pathak Anushri

Roll No.:208

Fault types and Models

Introduction
In order to deal with the existence of good and bad parts it is necessary to propose a “fault model”, i.e. a
model for how faults occur and their impact on circuits. Chip testing is usually multi purpose and attempts
to detect faults in fabrication, design, and failures due to stressful operating conditions, i.e. reliability
problems. The input vectors are applied to devise under test (DUT) and circuit under test (CUT) as its
stimuli. Its output are measured and compared with the desired outputs and if they match then quality of
DUT or CUT is determined. But with this method also there are various difficulties involved such as –only
I/O pins are accessible, at-speed test is not possible, signal integrity problem due to impedance mismatch,
etc.. Here, in this topic, we will study different types of faults and their models.

The main goals of Fault Models are :

Model defects in the device at the highest level of abstraction possible
o Reduces the number of individual defects that have to be considered
o Reduces the complexity of the device description that must be used in test
generation and analysis
o Allows test generation and analysis to be done as early in the design process as
possible
Model as high a percentage as possible of the actual physical defects that can
occur in the device.

Mainly the faults are caused due to physical defects. The examples of physical defects are:

Defects in silicon substrate

Photolithographic defects
Mask contaminated and scratches
Process variations and abnormalities
Oxide defects.

Plasma processes used for strip resist and etch oxide in CMOS technologies may degrade the quality of the
silicon surface if it is protected of the plasma by a too thin oxide capping. Using AFM measurements, we
have identified this degradation as a silicon roughness increase.

The physical defects can cause electrical faults and logical faults.

The electrical faults include :

Shorts (bridging faults) & opens

Transistor stuck-on, stuck-open
Resistive shorts and opens
Excessive change in threshold voltage
Excessive steady-state currents

The logical faults include :

Logical struck-at-0 or struck-at-1

Slower transition
AND-bridging, OR bridging
  Electrical Faults

Stuck-On, Stuck-Open

gate
S D

n+ n+

(a)

gate
S D

n+ n+
(b)

Bridging Faults

Assumptions
1) Two nodes of a circuit are shorted together
2) Usually assumed to be a low resistance path (hard short)
3) Three classes are typically considered:
i. Bridging within a logic element (transistor gates, sources, or drains shorted
together)
ii. Bridging between logic nodes (i.e. inputs or outputs of logic elements) without
feedback
iii. Bridging between logic nodes with feedback
4) Typically not considered is bridging of non-logical nodes between logic elements (transistor shorts
across logic elements)

Advantages
1) Covers a large percentage of physical defects - some research indicates that bridging faults
account for up to 30% of all defects
Disadvantages
1) ATPG algorithms are more complex - testing requires setting the two bridged nodes to opposite
values and observing the effect
2) Requires a lower level circuit description for bridging faults within logic elements

 Logical Faults

Logical struck-at-0 or struck-at-1

The most popular model is called the “Struck-at” model. With this model, a faulty gate input is modeled as
a “struck at 0” or “stuck at 1”.
These faults are of two types : 1) Single Stuck-at Fault Model &
2) Multiple Stuck-at Fault Model.
Single Stuck-at Fault Model:

Fault-Free Gate Faulty Gate

Fault: A s-a-1
A B C A B C
Vcc
0 0 0 0 0 0
0 1 0 A 0 1 1
1 0 0 C 1 0 0
1 1 1 B
1 1 1

Assumptions
1) Only one line in the circuit is faulty at a time
2) The fault is permanent (as opposed to transient)
3) The effect of the fault is as if the faulty node is tied to either Vcc (s-a-1), or Gnd (s-a-0)
4) The function of the gates in the circuit is unaffected by the fault

Advantages
1) Can be applied at the logic level or module level
2) Reasonable numbers of faults 2n (n=number of circuit nodes)
3) Algorithms for automatic test pattern generation (ATPG) and faults simulation are well developed
and efficient
4) Research indicates that the single stuck-at fault model covers about 90% of the possible
manufacturing defects in CMOS circuits
5) Source-drain shorts, oxide pinholes, missing features, diffusion contaminants, metallization shorts,
etc.
6) Other useful fault models (stuck-open, bridging faults) can be mapped into (sequences of) stuck-at
faults

Disadvantages
1) Does not cover all defects in CMOS or other devices

Multiple Stuck-at Fault Model.:

Assumptions
1) Same as single stuck-at faults except:
2) 2 or more lines in the circuit can be faulty at the same time
Advantage
1) If used in conjunction with single stuck-at faults, it covers a greater percentage of physical defects
Disadvantages
1) Large number of faults 3n-1 (n=number of circuit nodes)
2) Algorithms for ATPG and fault simulation are much more complex and not as well developed
3) Does not cover a significantly larger number of detects that single stuck-at faults

Slower transition model

It is also called Delay Fault Model. It causes timing failures at target speed. The various factors due to
which this may occur are:
1) Improper estimation of on-chip interconnect delays and other timing considerations.
2) Excessive variations in the fabrication process which cause significant variations in circuit delays
and clock skews.
 3) Opens in metal lines connecting parallel transistors which make the effective transistor size much
smaller.
4) Aging effects such as hot-carrier induced delay increase.
Assumptions
1) The logic function of the circuit-under-test is error free
2) Some physical defect, such as process variations, etc., makes some delays in the circuit-under-test
greater than some defined bounds
3) Two delay fault models are typically used:
 Gate delay, or transitional fault model
 Path delay fault model

Transitional Delay Fault Model

A logical model for a defect that delays either a rising or falling transition on a specific line in the circuit
Slow-to-rise
Slow-to-fall
Advantage
1) If a delay fault is large enough, it behaves as a temporary stuck-at fault, and single
stuck-at fault testing techniques can be applied
Disadvantages
1) Two patterns are required for detection initialization and transition detection
(propagation)
2) The minimum delay fault size that can be detected is difficult to determine

Delay = 2
1
Slow-to- 0 E
Rise Fault B
Z

0 1 Delay = 2
A Delay = 6

0 6 8
C 1 10 12
D
Delay = 2
Delay = 2
Delay = 2

Example of Minimum Delay Fault Detectable

In the above example when the input is 0, output is 0 and when it is 1 the output is 1. Now consider that
each gate has an internal delay of 2ns. Then at the input of last OR gate 1 terminal will have 6ns delay
while other 4ns. So at output total 12ns (6+4+2) . Thus due to transition delay the output is delayed by 12
ns.

Path Delay Fault Model

A fault model in which the total delays in a path from inputs to outputs in a circuit exceeds some
maximum value.
Advantages
1) Detects more delay faults - i.e., in transitional fault model, the delay of a faulty gate
may be compensated for by other faster gates in the path
2) Can be used with more aggressive statistical design philosophy
Disadvantages
1) Large number of possible paths in circuit - exponential with number of gates
2) Algorithms for test generation are more complex and less well developed

The fault models mentioned above are used in fault simulation aimed at
Test generation
Construction of fault dictionaries, or
Circuit analysis in the presence of faults.