`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 10/13/2021 11:03:41 AM

// Design Name:

// Module Name: 8bitrom_tb

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module 8bitrom_tb;

wire [7:0] data_out;

reg clock;

reg [3:0] address;

8bitrom TB (.data_out(data_out), .address(address), .clock(clock));

initial
 begin

clock = 0;

#5 address=0;

#5 address=1;

#5 address=2;

#5 address=3;

#5 address=4;

#5 address=5;

end

always

begin

#3 clock = ~clock;

end

endmodule