`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 10/13/2021 10:58:59 AM

// Design Name:

// Module Name: 8bitrom

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module rom(

input wire [2:0] address,

input wire [1:0] clock,

output reg [7:0] data_out);

reg [7:0] ROM [0:5];

 initial

begin

ROM[0] = 8'h86;

ROM[1] = 8'hAA;

ROM[2] = 8'h96;

ROM[3] = 8'hE0;

ROM[4] = 8'h20;

ROM[5] = 8'h00;

end

always@(posedge clock)

begin

data_out = ROM[address];

end

endmodule