Memory

Prof. Dhaval Shah

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Outline
 Introduction to memory
 Classification of memory
 Various types of memory
 Read only Memory
 Random Access Memory
 Programmable Logic Devices
 Programmable Array Logic
 Programmable Logic Array
 Other form of Memory
 Magnetic Core Memory
 Charge Coupled Device

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Introduction to memory
 Memory is the basic requirement of every
automatic computational system.
 Data Memory
 Program Memory
 Main Memory
 Peripheral Memory

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Classification of memory

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Types of Memory

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Types of Memories
 Static
 Information are stored in latches
 remains valid as long as power is applied
 short read/write cycle
 Dynamic
 Information are stored in the form of charges
on capacitors
 the stored charge tends to discharge with time
 need to be refreshed (read and write back)
 reduced power consumption
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 Larger memory capacity Digital Circuits

Types of Memories (conti…)
 Volatile
 lose stored information when power is turned
off
 SRAM, DRAM
 Non-volatile
 Retains its stored information after the
removal of power
 ROM
 EPROM, EEPROM
 Flash memory
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Read-Only Memory
 Store permanent binary information
 2k x n ROM

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An Example of ROM
 32x8 ROM
 5-to-32 decoder
 8 OR gates
 each has 32 inputs
 32x8 internal programmable connections

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ROM truth table (partial)

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Combinational Circuit Implementation

 ROM: a decoder + OR gates

 sum of minterms
 a Boolean function = sum of minterms
 For an n-input, m-output combinational ckt
 2n  m ROM

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Design procedure:
1. Determine the size of ROM
2. Obtain the programming truth table of the
ROM
3. The truth table = the fuse pattern

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 ROM implementation
 Truth table

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ROM TYPES
 Read only Memory (ROM)
 MROM
 PROM
 EPROM
 EEPROM

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MROM

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PROM Array before programming

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PROM Array after programming

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Application of ROM

 Microcontroller Program Storage

 Bootstrap Memory
 Data Tables
 Data Converters
 Character and Function Generator

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Random-Access Memory
 A memory unit
 stores binary information in groups of bits
(words)
 8 bits (a byte), 2 bytes, 4 bytes

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Block diagram of RAM

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A 1024*16 Memory

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Write and Read Operations
 Write operation
• Apply the binary address to the address lines
• Apply the data bits to the data input lines
• Activate the write input
 Read operation
• Apply the binary address to the address lines
• Activate the read input

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Timing Waveforms
 The operation of the memory unit is
controlled by an external device
 The access time
 Time required to select a word and read it
 The cycle time
 Time required to complete a write operation
 Read and write operations must synchronized
with an external clock

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Internal Construction
 A RAM of m words and n bits per word
 m*n binary storage cells
 Decoding circuits to select individual words
 k-to-2k decoder

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 Memory Structure and SRAM
Output enable
Chip select

Storage
Write enable cells
Data in / D Q / / Data out
g g g
Address / FF
h C Q
0

D Q /
g
FF
C Q
Address
1
decoder
.
. WE
. D Q / D in
g D out
FF Addr
C Q CS OE
2h –1

Conceptual inner structure of a 2h  g SRAM chip and its shorthand representation.

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DRAM and SRAM

DRAM vs. SRAM Memory Cell Complexity

Word line Word line Vcc

Pass
transistor

Capacitor
Compl.
Bit Bit
bit
line line
line
(a) DRAM cell (b) Typical SRAM cell

Single-transistor DRAM cell, which is considerably simpler than SRAM cell,

leads to dense, high-capacity DRAM memory chips.
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Programmable Logic
Device

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Combinational PLD

 Programmable Read Only Memory

 Fixed AND – Programmable OR
 Programmable Array Logic
 Programmable AND – Fixed OR
 Programmable Logic Array
 Programmable AND – Programmable OR

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Programmable Logic Array
 PLA
 an array of programmable AND gates
 can generate any product terms of the inputs
 an array of programmable OR gates
 can generate the sums of the products
 more flexible than ROM
 use less circuits than ROM
 only the needed product terms are generated

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F1 = AB + AC + ABC

F2 = (AC + BC)

XOR gates can invert the

outputs

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PLA (cont..)

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PLA (cont..)
 The size of a PLA
 The number of inputs
 The number of product terms (AND gates)
 The number of outputs (OR gates)
 When implementing with a PLA
 reduce the number of distinct product terms
 the number of terms in a product is not
important

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 PAL

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Sequential Programmable Devices
 Sequential programmable logic device
 SPLD
 PLD + flip-flops

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 We Hope that this
Memory
will remain forever to your
Memory
Thank You!
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