Instructions and Addressing

in MiniMIPS
Sachin Gajjar
sachin.gajjar@nirmauni.ac.in
Reading Material
• Chapter 5 Instructions and Addressing
• Book - Computer Architecture from Microprocessor to Super
Computer by Behrooz Parahami, Oxford Publications
 TOPICS
1. Abstract View of MiniMIPS Hardware
2. Instruction Formats
3. Simple Arithmetic and Logic Instructions
4. Load and Store Instructions
5. Jump and Branch Instructions
6. Addressing Modes
MiniMIPS; is a hypothetical machine that is close to the real MIPS processors, a
family of processors offered by a company MiniMIPS
 MiniMIPS (minimal MIPS)
• A RISC (reduced instruction-set computer) –simplicity and uniformity
of instruction formats, designs that aim to execute the most commonly
used operations as fast as possible
• The MiniMIPS (minimal MIPS) is a load/store instruction set,
• meaning that data elements must be copied or "loaded" into registers
before they can be processed;
• operation results also go into registers and must be explicitly copied
back into memory through separate "store" operations.
 MiniMIPS (minimal MIPS)
• The assembly language programmer is concerned with:
 Registers
 Memory locations where data might be stored
 Machine instructions that operate on and store data in registers or
memory
 Memory and processing subsystems for MiniMIPS.
. . .
Loc 0 Loc 4 Loc 8 m  2 32
4 B / location Memory
up to 2 30 words Loc Loc
m 8 m 4
. . .
32 bit wide, 32 GPP
EIU $0 Execution FPU $0 Floating -
(M ain proc.) $1 & integer (C oproc. 1) $1 point unit
$2 unit $2

$31 $31
Integ er FP
ALU
mul/di v arith

Hi Lo
TMU BadVaddr Tra p &
(C oproc. 0) Status memo ry
Cause unit
Chapter Chapter Chapter EPC
10 11 12

Figure 5.1 Memory and processing subsystems for MiniMIPS.

 1. Abstract View of Hardware
• Memory unit, up to 230 words (232 bytes), 1 word = 32 bits
• an execution and integer unit (EIU) - interprets and executes the basic MiniMiPs instructions,
• has 32 general-purpose registers, each of which is 32 bits wide and can thus hold the content of one
memory location
• a floating-point unit (FPU),
• trap and memory unit (TMU).
• Branch address value, status of interrupt (enable/disable), cause of interrupt, EPC register (to
store/retrieve value of PC during an INT)
• The arithmetic logic unit (ALU) executes addition, subtraction, and logical instructions.
• A separate arithmetic unit is dedicated to multiplication and division instructions whose results are
placed in two special registers, named "Hi" and "Lo," from where they can be moved into general-
purpose registers.
 $0
$1
0 $zero
$at
A 4-b yte word
3
Register Conventions
Reserved for assembl er use sits in consecutive
$2 $v0 m em ory address es 2
$3 $v1 Procedure results according to the 1
$4 $a0 big-endian order 0
(m ost significant
Each cell is 8 bits, a byte
$5 $a1 Procedure
Saved byte has the
$6 $a2 arguments
lowest address )
$7 $a3 • Word=32-bit data element
$8 $t0
$9 $t1 Byte num bering: 3 2 1 0 • a byte addressable memory
$10 $t2 When loading • Size of register is 32 bit
$11 $t3 Temporary a byte into a
$12 $t4 values register, it goes
$13 $t5 (10 registers) in the low end Byte
$14 $t6
$15 $t7 Word
$16 $s0 Doublew ord
$17 $s1
$18 $s2 Saved
$19 $s3 across
Operands procedure
$20 $s4
$21 $s5 calls
(8 registers)
$22 $s6
$23 $s7 A doubleword
$24 $t8 More sits in consecutive
$25 $t9 temporari es registers or
$26 $k0 m em ory locations
$27 $k1 Reserved for OS (kernel) according to the
$28 $gp Global pointer big-endian order
$29 $sp Stack pointer (m ost significant
Saved word com es first)
$30 $fp Fram e pointer
$31 $ra Return address Figure 5.2 Registers and data sizes in MiniMIPS.
Heap memory
In addition, coprocessor 0 contains registers that are useful to handle
exceptions.

These registers are part of coprocessor 0's register set and are accessed by
the lwc0, mfc0, mtc0, and swc0 instructions.
Storage Conventions
MiniMIPS uses the "big endian" scheme

MSB LSB

LSB= bits 24-31 of data

LSB= bits 0-7 of data
 2. Instruction Formats
High-level language statement: a = b + c

Assembly language instruction: add $t8, $s2, $s1

(Keil’s disassembly window, importance of
looking assembly code for C program)
Machine language instruction: 000000 10010 10001 11000 00000 100000
ALU-type Register Register Register Addition
instruction 18 17 24 Unused opcode

Register Register
Instruction file Data cache file
cache (not used)

P $17 ALU
C $18
$24

Instruction Register Data Register

Operation
fetch readout read/store writeback

Figure 5.3 A typical instruction for MiniMIPS and steps in its execution.
 2. Instruction Formats
MiniMIPS add & subtract instructions; e.g., compute:
g = (b + c)  (e + f)
add $t8,$s2,$s3 # put the sum b + c in $t8
add $t9,$s5,$s6 # put the sum e + f in $t9
sub $s7,$t8,$t9 # set g to ($t8)  ($t9)

• The preceding instruction sequence effectively computes g by

performing the operations a = b + c, d = e + f, and g = a - d, with
temporary values a and d held in registers $t8 and $t9, respectively.
• Instructions are executed from top to bottom unless a different order of
execution is explicitly specified via jump or branch instructions
 2. Instruction Formats
• In writing machine language programs, we need to supply integers that
specify memory addresses or numerical constants.
• Such numbers are specified in decimal (radix-10) or hexadecimal
(radix-16, or hex for short) format and are automatically converted to
the binary format for machine processing.
Decimal and hex constants
Decimal 25, 123456, 2873
Hexadecimal 0x59, 0x12b4c6, 0xffff0000
 2. Instruction Formats
• A machine instruction for an arithmetic logic operation specifies an opcode,
one or more source operands, and, usually, one destination operand.
• Opcode is a binary code (bit pattern) that defines an operation.
• The operands of an arithmetic or logical instruction may come from a
variety of sources (register, memory, constant)
• The method used to specify where the operands are to be found and where
the result must go is referred to as the addressing mode (or scheme).
 Distinguish the
instructions and
Operation to be
3 Major Instruction Formats
performed
op rs rt rd sh fn
31 25 20 15 10 5 0
R 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Opcode Source Source Destination Shift Opcode
register 1 register 2 register amount extension

op rs rt operand / offset
31 25 20 15 0
I 6 bits 5 bits 5 bits 16 bits
Opcode Source Destination Imm ediate operand
or base or data or address offset for load/store/branch

op jump target address

31 25 0
J 6 bits 1 0 0 0 0 0 0 0 0 0 0 0 26
0 bits
0 0 0 0 0 0 0 1 1 1 1 0 1
Opcode Memory word address (byte address di vided by 4)

MiniMIPS instructions come in only three formats: register (R), immediate (I), and jump (J).
 3. Simple Arithmetic and Logic Instructions
• ADD/SUB instructions work on registers containing whole (32-bit) words.
add $t0,$s0,$s1 # set $t0 to ($s0)+($s1)
sub $t0,$s0,$s1 # set $t0 to ($s0)-($s1)
Below is the machine representations of the instructions
op rs rt rd sh fn
31 25 20 15 10 5 0
R 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 x 0
ALU Source Source Destination Unused add = 32
instruction register 1 register 2 register sub = 34

The arithmetic instructions add and sub have a format that is common to all two-operand ALU
instructions. For these, the fn field specifies the arithmetic/logic operation to be performed.
 3. Simple Arithmetic and Logic Instructions
• Logical instructions operate on a pair of operands on a bit-by-bit basis.
Logical instructions in MiniMIPS include the following:
and $t0,$s0,$s1 # set $t0 to ($s0)($s1)
or $t0,$s0,$s1 # set $t0 to ($s0)($s1)
xor $t0,$s0,$s1 # set $t0 to ($s0)($s1)
nor $t0,$s0,$s1 # set $t0 to (($s0)($s1))’
 3. Simple Arithmetic and Logic Instructions
• Machine representations for these logic instructions are similar to that
of ADD/SUB, but with the function field holding 36 (100100) for and,
37 (100101) for or, 38 (100110) for xor, and 39 (100111) for nor.

op rs rt rd sh fn
31 25 20 15 10 5 0
R 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 x 0
ALU Source Source Destination Unused add
36 = 32
- 39
instruction register 1 register 2 register sub = 34
 3. Simple Arithmetic and Logic Instructions
• Often, one operand of an arithmetic or logical operation is a constant.
• While it is possible to place this constant in a register and then perform the desired
operation on two registers, it would be more efficient to use instructions that
directly specify the desired constant in an I-format (Immediate) instruction.
• Constant must be small enough to fit in 16-bit field that is available for this
purpose.
• Thus, for signed integer values the valid range is from -32,768 to 32,767, while for
hex constants any 4-digit number in the range [0x0000, 0xffff] is acceptable.
addi $t0,$s0,61 # set $t0 to ($s0)+61
 3. Simple Arithmetic and Logic Instructions
addi $t0,$s0,61 # set $t0 to ($s0)+61
op rs rt operand / offset
31 25 20 15 0
I 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
addi = 8 Source Destination Imm ediate operand
Instructions such as addi allow us to perform an arithmetic or logic operation for which one operand is a small constant.

• The machine representation of addi is above.

• There is no "subtract immediate" instruction, as its effect can be accomplished by adding a negative value.
• MiniMIPS has a 32-bit adder, so the 16-bit immediate operand must be converted to an equivalent 32-bit value
before it is applied as input to the adder.
• A signed number must be sign-extended if it is to result in the same numerical value in a wider format.
• Sign extension simply means that the most significant bit of a 16-bit signed value is repeated 16 times to fill the
upper half of the corresponding 32-bit version.
• So, a positive number is extended with 0’s while a negative number is extended with 1’s.
 3. Simple Arithmetic and Logic Instructions
The immediate/I-format version of logical instructions is given below.
addi $t0,$s0,61 # set $t0 to ($s0)+61
andi $t0,$s0,61 # set $t0 to ($s0)61
ori $t0,$s0,61 # set $t0 to ($s0)61
xori $t0,$s0,0x00ff # set $t0 to ($s0) 0x00ff

Machine representations for these logic instructions are similar to that of addi, but with the opcode
field holding 12 (001100) for andi, 13 (001101) for ori, and 14 (001110) for xori.
One use of logical instructions with I-format is Masking of bits

op rs rt operand / offset
31 25 20 15 0
I 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
addi = 8 Source Destination Imm ediate operand
• Example 5.1: Extracting fields from a word A 32-bit word in $s0 holds a byte of data in bit positions
0-7 and a status flag in bit position 10. Other bits in the word have arbitrary (unpredictable) values.
Unpack the information in this word, putting the data byte in register $t0 and the status flag in register
$t1. At the end, register $t0 should hold an integer in [0, 255] corresponding to the data byte and register
$t1 should hold a nonzero value iff the status flag is 1.
• Solution: Fields of a word can be extracted by ANDing the word with a predefined mask, a word that
has 1s in bit positions of interest and 0s elsewhere. For example, ANDing a word with Ox000000ff
(which in binary has 1s only in its 8 least significant bit positions) has the effect of extracting the
rightmost byte. Any desired flag bit can be similarly extracted through ANDing with a mask that has a
single 1 in the desired position. Thus, the following two instructions accomplish what is required:
andi St0, $s0, Ox00ff #mask with eight 1s at right end
andi $t1, $s0, 0x0400 #mask with single 1 in position 10
• Note that the nonzero value left in $t1 in case the flag bit is 1 is equal to 210= 1024. We will see later than a
shift instruction can be used to leave 0 or l in $t1 according to the flag bit value.
 4. Load and Store Instructions
• Basic load and store instructions transfer whole words (32 bits) between memory registers.
• Each such instruction specifies a register and a memory address.
• The register, which is the data destination for load and data source for store, is specified in the rt
field of an I-format instruction.
• The memory address is specified in two parts that are added to yield the address: the l6-bit
signed integer in the instruction is a constant offset which is added to base value in register rs.
• In assembly language format, the source/destination register rt is specified first, followed by the
constant offset and the base register rs in parentheses.
• Putting rs in parentheses is reminiscent of the indexing notation A(i) in high-level languages.
lw $t0,40($s3) # load mem[40+($s3)] into $t0
sw $t0,A($s3) # store ($t0) into mem[A+($s3)]
# “($s3)” means “content of $s3”
 Machine Instructions format Load and Store
op rs rt operand / offset
31 25 20 15 0
I 1 0 x 0 1 1 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
lw = 35 Base Data Offset rel ati ve to base
sw = 43 register register
Note on base and offset:
Memory The memory address is the sum
of (rs ) and an imm ediate value.
Address in
A[0] Calling one of these the base
base register
A[1] and the other the offset is quite
A[2] arbitrary. It would m ake perfect
sense to interpret the address
.
. Offset = 4i A($s3) as having the base A
. and the offset ($s3). However,
Element i a 16-bit base confines us to a
A[i]
of array A small portion of m emory space.

MiniMIPS lw and sw instructions and their memory addressing convention that allows
for simple access to array elements via a base address and an offset (offset = 4i leads
us to the i th word).
 4. Load and Store Instructions
"load upper immediate" (lui) allows us to place an arbitrary constant in a desired register

lui $s0,61 # The immediate value 61 is

# loaded in upper half of $s0
# with lower 16b set to 0s

op rs rt operand / offset
31 25 20 15 0
I 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
lui = 15 Unused Destination
Imm ediate operand

0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Content of $s0 after the instruction is executed

The lui instruction allows us to load an arbitrary 16-bit value into the upper half of a
register while setting its lower half to 0s.
 Example 5.2: Loading arbitrary bit patterns into registers

Show how each of these bit patterns can be loaded into $s0:
0010 0001 0001 0000 0000 0000 0011 1101
1111 1111 1111 1111 1111 1111 1111 1111
Solution
Upper half of bit pattern has hex representation: 0x2110
Lower half has hex representation: 0x003d
lui $s0,0x2110 # put the upper half in $s0
ori $s0,0x003d # put the lower half in $s0

Same can be done, with immediate values changed to 0xffff for the
second bit pattern. But, the following is simpler and faster:

nor $s0,$zero,$zero # because (0  0) = 1

 5. Jump and Branch Instructions
• Following two unconditional jump instructions are available in Mini MIPS:

Unconditional jump and jump through register instructions $ra is the symbolic
name for reg. $31
j verify # go to mem loc named “verify” (return address)
jr $ra # go to address that is in $ra;
# $ra may hold a return address

Jump register, or jr specifies a register as holding the Jump target address.

This register is often $ra. and the instruction jr $ra is used to effect a return from a
procedure to the point from which the procedure was called.
Machine representations of MiniMIPS Jump instructions
For the j instruction. the 26-bit address field in the instruction is augmented with 00 to the right and 4 high-order bits of
the program counter (PC) to the left to form a complete 32-bit address. (memory address is of 32 bits)
This is called pseudo direct addressing
op jump target address
31 25 0
J 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
j = 2

x x x x 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
From PC
Effecti ve tar get add ress (3 2 bits)

op rs rt rd sh fn
31 25 20 15 10 5 0
R 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
ALU Source Unuse d Unuse d Unuse d jr = 8
instruction register

Jump instruction j of MiniMIPS is a J-type instruction which is shown along with how its effective
target address is obtained.
The jump register (jr) instruction is R-type, with its specified register often being $ra.
 Branch Instructions
• Conditional branch instructions allow us to transfer control to a given address when a condition of interest is
met.
• Conditional branches use PC-relative addressing - the 16-bit signed offset in the instruction is multiplied by 4
and the result added to the PC contents to get a 32-bit branch target address.
bltz $s1,L # branch on ($s1)< 0, L is label
beq $s1,$s2,L # branch on ($s1)=($s2)
bne $s1,$s2,L # branch on ($s1)($s2)

op rs rt operand / offset
31 25 20 15 0
I 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
bltz = 1 Source Zero Relati ve branch distance in words

op rs rt operand / offset
31 25 20 15 0
I 0 0 0 1 0 x 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
beq = 4 Source 1 Source 2 Relati ve branch distance in words
bne = 5

Conditional branch instructions of MiniMIPS. I type instructions.

 5. Jump and Branch Instructions
• If label specified is too far to be reachable via a 16-bit. offset (a very rare
occurrence), assembler automatically replaces beq $s0, $s1, L1 with a pair of
Mini-MIPS instructions:
bne $s1,$s2,L2 # skip jump if (s1)(s2)
j L1 # go to L1 if (s1)=(s2)
L2: ...
• Here, notation '"L2:" defines unspecified instruction appearing on that line as
having symbolic address L2.
• Therefore, in writing branch instructions, we can use symbolic names freely
without worrying whether corresponding address is reachable from the current
instruction by means of a 16-bit offset.
 5. Jump and Branch Instructions
slt $s1,$s2,$s3 # if ($s2)<($s3), set $s1 to 1
# else set $s1 to 0; set less than
# often followed by beq/bne
slti $s1,$s2,61 # if ($s2)<61, set $s1 to 1
# else set $s1 to 0, immediate version of slt
op rs rt rd sh fn
31 25 20 15 10 5 0
R 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0
ALU Source 1 Source 2 Destination Unused slt = 42
instruction register register

op rs rt operand / offset
31 25 20 15 0
I 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
slti = 10 Source Destination Imm ediate operand

Comparison instructions of MiniMIPS.

 5. Jump and Branch Instructions
• Branch and jump instructions can be used to form conditional and repetitive computation
structures akin to "if-then" and "while" of high-level languages. The if-then statement
if (i == j) x = x + y;
might be translated to the following MiniMIPS assembly language program fragment:
bne $s1,$s2,endif # branch on ij
add $t1,$t1,$t2 # execute the “then” part
endif: ...

• If the condition in the "if' statement were i < j, then the first instruction in the sequence
above would be replaced by the following two instructions (the rest would not change):
slt $t0,$s1,$s2 # set $t0 to 1 if i<j
beq $t0,$0,endif # branch if ($t0)=0; i.e. ij
# i.e., i not< j

• Many other conditional branches can be similarly synthesized.

 Example 5.3: Compiling if-then-else statements

Show a sequence of MiniMIPS instructions corresponding to:

if (i<=j) x = x+1; z = 1; else y = y–1; z = 2*z

Solution
Similar to the “if-then” statement, but we need instructions for the “else” part and a
way of skipping the “else” part after the “then” part.
slt $t0,$s2,$s1 # j<i? (inverse condition)
bne $t0,$zero,else # if j<i goto else part
addi $t1,$t1,1 # begin then part: x = x+1
addi $t3,$zero,1 # z = 1
j endif # skip the else part
else: addi $t2,$t2,-1 # begin else part: y = y–1
add $t3,$t3,$t3 # z = z+z
endif:...
 6. Addressing Modes
• Addressing mode is method by which location of an operand is specified
within an instruction. MiniMIPS uses six addressing modes
 6. Addressing Modes
1. Implied Addressing:
Operand comes from, or result goes to, a predefined place that is not explicitly
specified in the instruction.
jal instruction which always saves address of next instruction in sequence into
register $ra.
 6. Addressing Modes
2. Immediate addressing:
Operand is given in the instruction itself.
Examples include addi, andi, ori, and xori instructions in which the second
operand (the lower half of it) is supplied as part of the instruction.
 6. Addressing Modes
3. Register addressing:
Operand is taken from, or result placed in, a specified register.
R-type instructions in MiniMIPS specify up to three registers as locations of
their operand(s) and/or result.
Registers are specified by their 5-bit indices.
 6. Addressing Modes
4. Base addressing:
Operand is in memory and its location is computed by adding an offset
(16-bit signed integer) to the contents of a specified base register.
This is the addressing mode of 1w and sw instructions.
 6. Addressing Modes
5. PC-relative addressing:
Same as base addressing, but with the register always being the program
counter and the offset appended with two 0’s at the right end (word addressing
is always used).
This is addressing mode is used in and branch instruction allows for branching
to other instructions within ± 215 words of the current instruction.
 6. Addressing Modes
6. Pseudo direct addressing:
In direct addressing, the operand address is supplied as part of the instruction.
For MiniMIPS, this is impossible, given that 32-bit instructions do not have
enough room to carry full 32-bit addresses.
The j instruction comes close to direct addressing because it contains 26 bits of
the jump targct address which is padded with 00 at the right end and 4 bits from
the program counter at the left to form a full 32-bit address; hence the name
"pscudodirect."
 6. Addressing Modes
Addressing Instruction Other el ements invol ved Operand

Impli ed Some p lace

in the machine

Extend,
Imm ediate if required

Reg spec Reg f ile Reg data

Register

Constant offset Me m
Base addr
Reg base Reg Add Me m
Reg f ile data Me mory data

Constant offset Me m
PC-relati ve
Add addr Me m
Me mory data
PC

Pseudodi rect PC Me m
addr Me m
Me mory data

Schematic representation of addressing modes in MiniMIPS.

 6. Addressing Modes
7. Direct addressing:
In direct addressing, the address of operand is supplied as part of the instruction.
Not possible in MiniMIPS
1) LOAD R1, 100 Load the content of memory address 100 to register R1.

2) LOAD R1, R2 Load the content of register R2 to register R1.

 6. Addressing Modes
7. Indexed addressing:
• For accessing Elements of Array
• One or more registers are dedicated to indexing.
• The content of one of these index registers would be added to the base address
• Base address can be specified directly or via one of the preceding addressing
modes.
• Eg. 8086, Base Registers (CS, DS, SS, ES) and index registers (PC, DI, SI, SP)
 6. Addressing Modes
7. Update addressing:
• one of the registers involved in forming the address (typically a register used as
index) is updated so that a new address computation yields the address of the
next array element.
• Update addressing requires the addition of a constant (±1 or ±a power of 2) to
the designated register.
• Saves an instruction in many common loops and can also speed up execution
if index updating is done parallel with executing the main part of the
instruction.
 6. Addressing Modes
7. Update addressing:
 6. Addressing Modes
7. Indirect addressing:
• The instruction contains the address of operand (in register or memory)
• requires a two-stage process for obtaining an operand.
• In the first stage, the designated location (a register or a memory word) is consulted; it
yields an address rather than an operand.
• If the first stage specifies a register, the addressing mode is known as register indirect,
• In the second stage, this address is used to retrieve the operand itself.
 MiniMIPS Instructions
Instruction Usage op fn
Copy Load upper immediate lui rt,imm 15
Add add rd,rs,rt 0 32
Subtract sub rd,rs,rt 0 34
Arithmetic
Set less than slt rd,rs,rt 0 42
Add immediate addi rt,rs,imm 8
op rs rt rd sh fn
R
31
6 bits
25
5 bits
20
5 bits
15
5 bits
10
5 bits
5
6 bits
0
Set less than immediate slti rd,rs,imm 10
0 36
Opcode Source Source Destination Shift Opcode
register 1 register 2 register amount extension AND and rd,rs,rt
op rs rt operand / offset
I
31
6 bits
25
5 bits
20
5 bits
15
16 bits
0
OR or rd,rs,rt 0 37
0 38
Opcode Source Destination Imm ediate operand
or base or data or address offset
XOR xor rd,rs,rt
op jump target address

0 39
31 25 0
J 6 bits 1 0 0 0 0 0 0 0 0 0 0 0 26
0 bits
0 0 0 0 0 0 0 1 1 1 1 0 1 NOR nor rd,rs,rt
Opcode Memory word address (byte address di vided by 4)

AND immediate andi rt,rs,imm 12

Logic
OR immediate ori rt,rs,imm 13
XOR immediate xori rt,rs,imm 14
Load word lw rt,imm(rs) 35
Memory access Store word sw rt,imm(rs) 43
Jump j L 2
Jump register jr rs 0 8
Control transfer Branch less than 0 bltz rs,L 1
Table 5.1 Branch equal beq rs,rt,L 4
Branch not equal bne rs,rt,L 5
 Example 5.5: Finding the maximum value in a list of numbers

List A is stored in memory beginning at the address given in $s1.

List length is given in $s2.
Find the largest integer in the list and copy it into $t0.
Solution
Scan the list, holding the largest element identified thus far in $t0.
lw $t0,0($s1) # initialize maximum to A[0]
addi $t1,$zero,0 # initialize index i to 0
loop: add $t1,$t1,1 # increment index i by 1
beq $t1,$s2,done # if all elements examined, quit
add $t2,$t1,$t1 # compute 2i in $t2
add $t2,$t2,$t2 # compute 4i in $t2
add $t2,$t2,$s1 # form address of A[i] in $t2
lw $t3,0($t2) # load value of A[i] into $t3
slt $t4,$t0,$t3 # maximum < A[i]?
beq $t4,$zero,loop # if not, repeat with no change
addi $t0,$t3,0 # if so, A[i] is the new maximum
j loop # change completed; now repeat
done: ... # continuation of the program

Note that the list has been assumed to be nonempty, containing at least the element A[0].
Thank You