td LI | ‘Question Paper Code: 14VES11T04 Hall Ticket No: MADANAPALLE INSTITUTE OF TECHNOLOGY & SCIENCE, MADANAPALLE (UGC-AUTONOMOUS) M.Tech | Year I Semester (R14) Supplementary End Semester Examinations — Feb 2018 (Regulations: R14) ANALOG & DIGITAL IC DESIGN (VIS! & Embedded Systems) ‘Max Marks: 60 Attempt all the questions. All parts of the question must be answered in one place only. In Q.no 1 to 5 answer either Part-A or B only Time: 3Hrs Q.1(A) Explain about MOS modeling in detail for all regions of operations. 12M OR Q.1(8) With circuit diagram, derive an expression for gain in source follower with current 22M mirror. Q.2(A) Discuss about op-amp compensation techniques. 12M OR Q.2(B) Consider the circuit shown in fig.2 with the following device geometries (in um). 22M Transi [Q [G2 [Gs [Gm Qs Os ye stor w/t | 20/0.8 | 20/0.8 |5/0.8 | 5/0.8 | 40/0.8 | 10/0.8 | 40/08 | 40/0.8 Let 1, =9014,¥,,=0.7¥,V,, =-O.8V,1,Coy = 16014 V3, 1)Cay = 40UAIV? 7, |= 1OV Vg = Vas = 2.57 For all devices evaluate 1p, oy]. |Vos|+8m»%o Also find As,Az, the de open loop voltage gain, the input common mode range, and the output voltage range. Neglect the effect, of Va on bias current. +¥op Tree eLirt 2. v v Ks Fig2 Page 1 of 2Q.3(A)_ With circuit diagram explain about high swing current mirrors. 22M OR Q.3(B) With circuit diagram explain about folded cascode op-amp. 12M 'Q.4(A) With complete block diagram explain sigma-delta ADC 12M oR Q.4(B) Explain about digital decimation filters. 22M Q.5(A) i) Explain modified Booth’s algorithm 12M ii) Explain pipeline multiplier array oR Q.5(B) i) Explain carry look ahead adders 12M ii) Explain about serial parallel! multiplier ee END Page 2 of 2