AREA DELAY POWER EFFICIENT FIXED-POINT LMS

ADAPTIVE FILTER WITH LOW ADAPTION-DELAY

A Mini Project Report submitted to

JNTU Hyderabad in partial fulfillment
of the requirements for the award of the degree

BACHELOR OF TECHNOLOGY
In
ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted by

VINNAKOTA DRUVYA SRAVANI 18RG1A04B8

ASURI SAI SAMPADHA 18RG1A0465

SURBIRYAL SINDHUJA 18RG1A04A9

YENUGU SUSHMA 18RG1A04C0

Under the Guidance of

Mrs. AFFROSE B.Tech., M.Tech (PhD),
PROFESSOR

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

MALLA REDDY COLLEGE OF ENGINEERING FOR WOMEN
(Approved by AICTE New Delhi and Affiliated to JNTUH)
(An ISO 9001 : 2015 Certified Institution)
Maisammaguda, Medchal (M), Hyderabad-500100, T.S.

i
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

MALLA REDDY COLLEGE OF ENGINEERING FOR WOMEN

(Approved by AICTE New Delhi and Affiliated to JNTUH)
An ISO 9001: 2015 Certified Institution
Maisammaguda, Medchal (M), Hyderabad-500100, T.S.
JANUARY 2021

CERTIFICATE
This is to certify that, the mini project entitled “AREA DELAY POWER
EFFICIENT FIXED-POINT LMS ADAPTIVE FILTER WITH LOW ADAPTION
DELAY” has been submitted by Vinnakota Druvya Sravani
(18RG1A04B8), Asuri Sai Sampadha (18RG1A0465), Surbiryal
Sindhuja (18RG1A04A9), Yenugu Sushma (18RG1A04C0) in
partial fulfillment of the requirements for the award of BACHELOR OF
TECHNOLOGY in ELECTRONICS & COMMUNICATION ENGINEERING .
This record of bonafide work carried out by them under my guidance and
supervision. The result embodied in this mini project report has not
been submitted to any other University or Institute for the award of
any degree.

Mrs. AFFROSE Dr. Archek Praveen Kumar

Professor Head of the Department

ii
Project Guide

External Examiner

i
 ACKNOWLEDGEMENT

The Mini Project work carried out by our team in the Department of
Electronics and Communication Engineering, Malla Reddy College of
Engineering for Women, Hyderabad. This work is original and has not
been submitted in part or full for any degree or diploma of any other
university.
We wish to acknowledge our sincere thanks to our project guide Mrs.
Affrose, Professor in Department of Electronics & Communication
Engineering for formulating the problem, analysis, guidance and his
continuous supervision during the project work.
We acknowledge our sincere thanks to Dr. Archek Praveen Kumar,
Professor, Head of the ECE Department, Dr.Kanaka Durga Returi, Dean
Academics and Professor in Department of Computer Science Engineering
and Dr. Vaka Murali Mohan, Principal and Professor in Department of
Computer Science Engineering, MRCEW for their kind cooperation in
making this Mini Project work a success.
We extend our gratitude to our beloved Chairman Sri. Ch. Malla
Reddy and our Secretary Sri. Ch. Mahender Reddy for their kind
cooperation in providing the infrastructure for successful completion of our
mini project work
We convey our special thanks to the entire Teaching faculty and non-
teaching staff members of the Electronics and Communication Engineering
Department for their support in making this project work a success.

VINNAKOTA DRUVYA SRAVANI 18RG1A04B8

ASURI SAI SAMPADHA 18RG1A0465
SURBIRYAL SINDHUJA 18RG1A04A9
YENUGU SUSHMA 18RG1A04CO

iii
 INDEX
LIST OF CONTENTS PAGE NO
ABSTRACT
1.LIST OF FIGUTRES
CHAPTER 1 - INTRODUCTION
1.1 Least mean square filter
1.2 Relationship to the least mean square filter
1.3 Definition of symbols
1.4 Simplifications
1.5 Adaptive filter
1.6 Tapped delay line FIR filter
1.7 Adaptive linear combiner
1.8 LMS algorithm
CHAPTER 2 – LITERATURE SURVEY
CHAPTER 3 – VERY LARGE SCALE INTEGRATION
3.1 Introduction
CHAPTER 4 – DESIGN CLASSIFICATION
4.1 Analog
4.2 ASCI
4.3 VLSI design styles
4.4 FPGA
4.5 Gate array design
4.6 Standard-cells based design
4.7 Full custom design
CHAPTER 5 – VERILOG
5.1 Introduction
5.2 History
5.3 Verilog code structure
5.4 Verilog design issues
5.5 Compilation
5.6 Data types
CHAPTER 6 – DESIGN REUSABILITY
6.1 Easiest to learn
6.2 Forward and backward annotation
6.3 High level constructs
6.4 Language extensions
6.5 Low level constructs
6.6 Operators

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6.7 Readability
6.8 Importance of HDL’s
6.9 Popularity of Verilog hdl
6.10 Typical design flow
CHAPTER 7 – XLINX
7.1 XLINX ISE overview
7.2 Design entry
7.3 Synthesis
7.4 Implementation
7.5 Project navigator overview
7.6 Using a sources window
7.7 Using the process window
7.8 Process types and status
7.9 Running process
7.1.0 Setting process properties
7.1.1 Using the transcript window and toolbar
CHAPTER 8 – CREATING A PROJECT
8.1 To create a project
8.2 Display incremental messages
8.3 Using ISE example projects
8.4 Creating a source file
8.5 Adding a source file to a project
8.6 FPGA Design flow overview
8.7 Functional verification
CHAPTER 9 – DESIGN SYNTHESIS
9.1 Design implementation
9.2 Timing verification
9.3 XLINX device programming
9.4 FPGA basic flow
OUTPUT
CONCLUSION
REFERENCE

v
 ABSTRACT

In this paper, we present an efficient architecture for the

implementation of a delayed least mean square adaptive filter. For achieving
lower adaptation-delay and area-delay-power efficient implementation, we
use a novel partial product generator and propose a strategy for optimized
balanced pipelining across the time-consuming combinational blocks of the
structure. From synthesis results, we find that the proposed design offers
nearly 17% less area-delay product (ADP) and nearly 14% less energy-delay
product (EDP) than the best of the existing systolic structures, on average,
for filter lengths N = 8, 16, and 32. We propose an efficient fixed-point
implementation scheme of the proposed architecture, and derive the
expression for steady-state error. We show that the steady-state mean
squared error obtained from the analytical result matches with the
simulation result. Moreover, we have proposed a bit-level pruning of the
proposed architecture, which provides nearly 20% saving in ADP and 9%
saving in EDP over the proposed structure before pruning without
noticeable degradation of steady-state-error performance.

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 CHAPTER 1
INTRODUCTION

THE LEAST MEAN SQUARE (LMS) adaptive filter is the most

popular and most widely used adaptive filter, not only because of its
simplicity but also because of its satisfactory convergence performance. The
direct-form LMS adaptive filter involves a long critical path due to an inner-
product computation to obtain the filter output. The critical path is required
to be reduced by pipelined implementation when it exceeds the desired
sample period. Since the conventional LMS algorithm does not support
pipelined implementation because of its recursive behavior, it is modified to
a form called the delayed LMS (DLMS) algorithm which allows pipelined
implementation of the filter. A lot of work has been done to implement the
DLMS algorithm in systolic architectures to increase the maximum usable
frequency but, they involve an adaptation delay of N cycles for filter length
N, which is quite high for large order filters. Since the convergence
performance degrades considerably for a large adaptation delay,
Visvanathan et al. Have proposed a modified systolic architecture to reduce
the adaptation delay. A transpose-form LMS adaptive filter is suggested in,
where the filter output at any instant depends on the delayed versions of
weights and the number of delays in weights varies from 1 to N. Van and
Feng have
proposed a systolic architecture, where they have used relatively large
processing elements (PEs) for achieving a lower adaptation delay with the
critical path of one MAC operation. Ting et al. have proposed a fine-grained
pipelined design to limit the critical path to the maximum of one addition
time, which supports high sampling frequency, but involves a lot of area
overhead for pipelining and higher power consumption than in , due to its
large number of pipeline latches. Further effort has been made by Meher
and Maheshwari to reduce the number of adaptation delays. Meher and

1
Park have proposed a 2-bit multiplication cell, and used that with an
efficient adder tree for pipelined inner-product computation to minimize the
critical path and silicon area without increasing the number of adaptation
delays The existing work on the DLMS adaptive filter does not discuss the
fixed-point implementation issues, e.g., location of radix point, choice of
word length, and quantization at various stages of computation, although
they directly affect the convergence performance, particularly due to the
recursive behavior of the LMS algorithm. Therefore, fixed-point
implementation issues are given adequate emphasis in this paper. Besides,
we present here the optimization of our previously reported design to reduce
the number of pipeline delays along with the area, sampling period, and
energy consumption. The proposed design is found to be more efficient in
terms of the power-delay product (PDP) and energy-delay product (EDP)
compared to the existing structures.

Least mean squares filter

Least mean squares (LMS) algorithms are a class of adaptive filter used to
mimic a desired filter by finding the filter coefficients that relate to
producing the least mean squares of the error signal (difference between the
desired and the actual signal). It is a stochastic gradient descent method in
that the filter is only adapted based on the error at the current time. It was
invented in 1960 by Stanford University professor Bernard Widrow and his
first Ph.D. student, Ted Hoff.

Relationship to the least mean squares filter:

The realization of the causal Wiener filter looks a lot like the solution to the
least squares estimate, except in the signal processing domain. The least
squares solution, for input matrix   and output vector   is

The FIR least mean squares filter is related to the Wiener filter, but
minimizing the error criterion of the former does not rely on cross-

2
correlations or auto-correlations. Its solution converges to the Wiener filter
solution. Most linear adaptive filtering problems can be formulated using the

block diagram above. That is, an unknown system   is to be identified

and the adaptive filter attempts to adapt the filter   to make it as close

as possible to  , while using only observable signals  ,   and 

; but  ,   and   are not directly observable. Its solution is closely

related to the Wiener filter.

Definition of symbols
 is the number of the current input sample
 is the number of filter taps

 (Hermitian transpose or conjugate transpose)

 estimated filter; interpret as the estimation of the filter

coefficients after n samples

The basic idea behind LMS filter is to approach the optimum filter

weights  , by updating the filter weights in a manner to converge to

the optimum filter weight. The algorithm starts by assuming a small weights
(zero in most cases), and at each step, by finding the gradient of the mean
square error, the weights are updated. That is, if the MSE-gradient is
positive, it implies, the error would keep increasing positively, if the same
weight is used for further iterations, which means we need to reduce the

3
weights. In the same way, if the gradient is negative, we need to increase the
weights. So, the basic weight update equation is :

where   represents the mean-square error. The negative sign indicates that,
we need to change the weights in a direction opposite to that of the gradient
slope.

The mean-square error, as a function of filter weights is a quadratic function

which means it has only one extrema, that minimises the mean-square
error, which is the optimal weight. The LMS thus, approaches towards this
optimal weights by ascending/descending down the mean-square-error vs
filter weight curve.

The idea behind LMS filters is to use steepest descent to find filter

weights   which minimize a cost function. We start by defining the cost

function as

where   is the error at the current sample n and   denotes

the expected value.

This cost function ( ) is the mean square error, and it is minimized by

the LMS. This is where the LMS gets its name. Applying steepest
descent means to take the partial derivatives with respect to the individual
entries of the filter coefficient (weight) vector

where   is the gradient operator

4
Now,   is a vector which points towards the steepest ascent of the cost
function. To find the minimum of the cost function we need to take a step in

the opposite direction of  . To express that in mathematical terms

where   is the step size(adaptation constant). That means we have found a
sequential update algorithm which minimizes the cost function.
Unfortunately, this algorithm is not realizable until we

know  .

Generally, the expectation above is not computed. Instead, to run the LMS
in an online (updating after each new sample is received) environment, we
use an instantaneous estimate of that expectation. See below.

Simplifications

For most systems the expectation function   must be

approximated. This can be done with the following unbiased estimator

where   indicates the number of samples we use for

that estimate. The simplest case is 

For that simple case the update algorithm follows as

Indeed this constitutes the update algorithm for

the LMS filter.

5
Adaptive Filter:

An adaptive filter is a system with a linear filter that has a transfer

function controlled by variable parametersters and a means to adjust those
parameters according to anoptimization algorithm. Because of the
complexity of the optimization algorithms, most adaptive filters are digital
filters. Adaptive filters are required for some applications because some
parameters of the desired processing operation (for instance, the locations of
reflective surfaces in a reverberant space) are not known in advance or are
changing. The closed loop adaptive filter uses feedback in the form of an
error signal to refine its transfer function.

Generally speaking, the closed loop adaptive process involves the use of
a cost function, which is a criterion for optimum performance of the filter, to
feed an algorithm, which determines how to modify filter transfer function to
minimize the cost on the next iteration. The most common cost function is
the mean square of the error signal.

As the power of digital signal processors has increased, adaptive filters have

become much more common and are now routinely used in devices such as
mobile phones and other communication devices, camcorders and digital
cameras, and medical monitoring equipment.

The recording of a heart beat (an ECG), may be corrupted by noise from

the AC mains. The exact frequency of the power and its harmonics may vary
from moment to moment.

One way to remove the noise is to filter the signal with a notch filter at the
mains frequency and its vicinity, which could excessively degrade the quality
of the ECG since the heart beat would also likely have frequency
components in the rejected range.

To circumvent this potential loss of information, an adaptive filter could be

used. The adaptive filter would take input both from the patient and from
the mains and would thus be able to track the actual frequency of the noise
as it fluctuates and subtract the noise from the recording. Such an adaptive
6
technique generally allows for a filter with a smaller rejection range, which
means, in this case, that the quality of the output signal is more accurate
for medical purposes

The idea behind a closed loop adaptive filter is that a variable filter is
adjusted until the error (the difference between the filter output and the
desired signal) is minimized. The Least Mean Squares (LMS) filter and
the Recursive Least Squares (RLS) filter are types of adaptive filter.

fig:1.1 Least mean square filter

Adaptive Filter. k = sample number, x = reference input, X = set of
recent values of x, d = desired input, W = set of filter coefficients, ε =
error output, f = filter impulse response, * = convolution, Σ =
summation, upper box=linear filter, lower box=adaption algorithm

fig:1.2 Recursive Least Squares (RLS) filter

Adaptive Filter, compact representation. k = sample number, x =
reference input, d = desired input, ε = error output, f = filter impulse
response, Σ = summation, box=linear filter and adaption algorithm.

7
There are two input signals to the adaptive filter: dk and xk which are
sometimes called the primary input and the reference input respectively.[2]

 which includes the desired signal plus undesired interference and

 which includes the signals that are correlated to some of the
undesired interference in  .
k represents the discrete sample number.

The filter is controlled by a set of L+1 coefficients or weights.

 represents the set or vector of weights,

which control the filter at sample time k.

where   refers to the  'th weight at k'th time.

 represents the change in the weights that occurs as a result of

adjustments computed at sample time k.

These changes will be applied after sample time k and before they are
used at sample time k+1.

The output is usually   but it could be   or it could

even be the filter coefficients.[3](Widrow)

The input signals are defined as follows:

where:

g = the desired signal,

g' = a signal that is correlated with the desired signal g ,
u = an undesired signal that is added to g , but not correlated
with g or g'
u' = a signal that is correlated with the undesired signal u ,but not
correlated with g or g' ,
8
 v = an undesired signal (typically random noise) not correlated
with g , g' , u, u' or v' ,
v' = an undesired signal (typically random noise) not correlated
with g , g' , u, u' or v.

The output signals are defined as follows:

.
where:

 = the output of the filter if the input was only g' ,

 = the output of the filter if the input was only u' ,
 = the output of the filter if the input was only v' .

Tapped delay line FIR filter

If the variable filter has a tapped delay line Finite Impulse Response

(FIR) structure, then the impulse response is equal to the filter coefficients.
The output of the filter is given by

where   refers to the  'th weight at k'th time.

Ideal case

In the ideal case  . All the undesired signals in   

are represented by  .   consists entirely of a signal correlated
with the undesired signal in  .
9
The output of the variable filter in the ideal case is

 .

The error signal or cost function is the difference between   and 

. The desired signal gk passes through

without being changed.

The error signal   is minimized in the mean square sense when   is
minimized. In other words,   is the best mean square estimate of  . In the
ideal case,   and  , and all that is left after the subtraction is   
which is the unchanged desired signal with all undesired signals removed.

Signal components in the reference input

In some situations, the reference input x_k includes components of the

desired signal. This means g' ≠ 0.Perfect cancelation of the undesired
interference is not possible in the case, but improvement of the signal to
interference ratio is possible. The output will be

. The desired signal will be

modified (usually decreased).

The output signal to interference ratio has a simple formula referred to

as power inversion.

where

 = output signal to interference ratio.

 = reference signal to interference ratio.

 = frequency in the z-domain.

10
This formula means that the output signal to interference ratio at a
particular frequency is the reciprocal of the reference signal to interference
ratio.[4]

Adaptive Linear Combiner

Fig:1.3 Adaptive linear combiner

Adaptive linear combiner showing the combiner and the adaption
process. k = sample number, n=input variable index, x = reference
inputs, d = desired input, W = set of filter coefficients, ε = error
output, Σ = summation, upper box=linear combiner, lower
box=adaption algorithm.

Fig :1.4 adaption linear combiner

Adaptive linear combiner, compact representation. k = sample
number, n=input variable index, x = reference inputs, d = desired
input, ε = error output, Σ = summation.

The adaptive linear combiner (ALC) resembles the adaptive tapped delay line
FIR filter except that there is no assumed relationship between the X values.
If the X values were from the outputs of a tapped delay line, then the

11
combination of tapped delay line and ALC would comprise an adaptive filter.
However, the X values could be the values of an array of pixels. Or they
could be the outputs of multiple tapped delay lines. The ALC finds use as an
adaptive beam former for arrays of hydrophones or antennas.

where   refers to the  'th weight at k'th time.

LMS ALGORITM
If the variable filter has a tapped delay line FIR structure, then the
LMS update algorithm is especially simple. Typically, after each sample, the
coefficients of the FIR filter are adjusted as follows: [5](Widrow)

for 

μ is called the convergence factor.

The LMS algorithm does not require that the X values have any particular
relationship; therefor it can be used to adapt a linear combiner as well as an
FIR filter. In this case the update formula is written as:

The effect of the LMS algorithm is at each time, k, to make a small change in
each weight. The direction of the change is such that it would decrease the
error if it had been applied at time k. The magnitude of the change in each
weight depends on μ, the associated X value and the error at time k. The
weights making the largest contribution to the output,  , are changed the
most. If the error is zero, then there should be no change in the weights. If
the associated value of X is zero, then changing the weight makes no
difference, so it is not changed.

Convergence

μ controls how fast and how well the algorithm converges to the
optimum filter coefficients. If μ is too large, the algorithm will not converge.
If μ is too small the algorithm converges slowly and may not be able to track
12
changing conditions. If μ is large but not too large to prevent convergence,
the algorithm reaches steady state rapidly but continuously overshoots the
optimum weight vector. Sometimes, μ is made large at first for rapid
convergence and then decreased to minimize overshoot. Widrow and Stearns
state in 1985 that they have no knowledge of a proof that the LMS algorithm
will converge in all cases. [6] However under certain assumptions about
stationarity and independence it can be shown that the algorithm will
converge if

where

 = sum of all input power

 is the RMS value of the  'th input

In the case of the tapped delay line filter, each input has the same RMS
value because they are simply the same values delayed. In this case the total
power is

where

 is the RMS value of  , the input stream.[7]

This leads to a normalized LMS algorithm in which case the convergence

criteria becomes:  .

13
 CHAPTER 2

LITERATURE SURVEY
R. Rocher, D. Menard, O. Sentieys, and P. Scalart, “Accuracy evaluation of

fixed-point LMS algorithm,” in Proc. IEEE International Conference on

Acoustics, Speech, and Signal Processing (ICASSP), May 2004, 237–240.

Pramod Kumar Meher (SM’03) received the degrees of BSc (Honours), MSc in

Physics and PhD in science from Sambalpur University, Sambalpur,India, in

1976, 1978, and 1996, respectively.

14
 Currently, he is a Senior Scientist with the Institute for
Infocomm

Research, Singapore. Prior to this assignment he was a visiting faculty with

the

School of Computer Engineering, Nanyang Technological University,

Singapore.

He was a Professor of Computer Applications With Utkal University,

Bhubaneswar, India from 1997 to 2002, a Reader in Electronics with

Berhampur University, Berhampur, India from 1993 to 1997, and a Lecturer

in

Physics with various Government Colleges in India from 1981 to 1993. His

research interest includes design of dedicated and reconfigurable

architectures

for computation-intensive algorithms pertaining to signal, image and video

processing, communication, bio-informatics and intelligent computing. He

has

contributed more than 180 technical papers to various reputed journals and

conference proceedings.

Dr. Meher is a Fellow of the Institution of Electronics and

Telecommunication Engineers, India and a Senior Member of IEEE. He has

Served as Associate Editor for the IEEE Transactions on Circuits and

Systems:

Express Briefs during 2008-2011. Currently, he is serving as a speaker for

the Distinguished Lecturer Program (DLP) of IEEE Circuits Systems Society,

and Associate Editor for the IEEE Transactions on Circuits and Systems-I:

Regular Papers, IEEE Transactions on Very Large Scale Integration (VLSI)

Systems, and Journal of Circuits, Systems, and Signal Processing. He was

the

recipient of the Samanta Chandrasekhar Award for excellence in research in

15
engineering and technology for the year 1999.

Sang Yoon Park (S’03-M’11) received the B.S.,M.S., and Ph.D.

degrees in Department of Electrical Engineering and Computer Science from

Seoul National University, Seoul, Korea, in 2000, 2002, and 2006,

respectively.

He joined the School of Electrical and Electronic Engineering, Nanyang

Technological University, Singapore as a Research Fellow in 2007. Since

2008,

he has been with Institute for Infocomm Research, Singapore, where he is

currently a Research Scientist. His research interest includes dedicated

reconfigurable architectures and algorithms for low-power/low-area/high-

performance digital signal processing

R. Rocher,D.Menard ,O.Sentieys and P.Scalart, “Accuracy

evaluation of fixed-point LMS algorithm, ’’ in Proc. IEEE International

Conference on Acoustics, Speech and Signal processing, May 2004, where

he is

currently a Research Scientist. His research interest includes dedicated

reconfigurable architectures and algorithms.

L.K Ting , R. Woods and C.F.N Cowan ,Virtex FPGA

implementation

of pipelined adaptive LMS predictor for electronic support measures

receivers ,

IEEE transactions on Very Large Scale Integration Systems. He was the

recipient of the Samanta Chandrasekhar Award for excellence in research in

engineering and technology for the year 1999.

P. K. Meher and M. Maheswari, “A high speed FIR adaptive filter

arcitechture using a modified delayed LMS algorithm, ” in Proc. IEEE

16
International Symposium on circuits and systems (ISCAS), Rio dejaneiro,

Brazil, May 2011. Currently, he is a Senior Scientist with the Institute for

Infocomm Research, Singapore.

In 1989, Gateway Design Automation (and rights to Verilog)

was purchased by Cadence who put Verilog in the public domain in the
following year. This move did much to promote the use of Verilog since other
companies were able to develop alternatives tools to those of Cadence which,
in turn, allowed users to adopt Verilog without dependency on a single
(primarily workstation-tool) supplier. In 1992, work began to create an IEEE
standard (IEEE-1364) and in December 1995 the final draft was approved.
Thus Verilog has become an n international standard - which will further
increase its commercial development and use. At present, there is standards
activity to extend Verilog beyond purely digital circuits. This includes
Verilog-MS for "mixed signal specification" and Verilog- A for "analog"
design; the latter was recently approved (June 1996) by the board of Open
Verilog International and is now under consideration by the IEEE. In
addition, work is underway to automate the proof of "equivalence [between]
behavioral and synthesizable specifications" (see the Cambridge web site
below) to which Verilog readily lends itself.
CHAPTER 3
VERY-LARGE-SCALE INTEGRATION
INTRODUCTION
The electronics industry has achieved a phenomenal growth over the
last two decades, mainly due to the rapid advances in integration
technologies, large-scale systems design - in short, due to the advent of
VLSI. The number of applications of integrated circuits in high-performance
computing, telecommunications, and consumer electronics has been rising
steadily, and at a very fast pace. Typically, the required computational
power (or, in other words, the intelligence) of these applications is the
driving force for the fast development of this field. Gives an over view of the

17
prominent trends in information technologies over the next few decades. The
current leading-edge technologies (such as low bit-rate video and cellular
communications) already provide the end-users a certain amount of
processing power and portability. This trend is expected to continue, with
very important implications on VLSI and systems design. One of the most
important characteristics of information services is their increasing need for
very high processing power and bandwidth (in order to handle real-time
video, for example). The other important characteristic is that the
information services tend to become more and more personalized (as
opposed to collective services such as broadcasting), which means that the
devices must be more intelligent to answer individual demands, and at the
same time they must be portable to allow more flexibility/mobility.

Very-large-scale integration (VLSI) is the process of creating integrated

circuits by combining thousands of transistor-based circuits into a single
chip. VLSI began in the 1970s when complex semiconductor and
communication technologies were being developed. The microprocessor is a
VLSI device. The term is no longer as common as it once was, as chips have
increased in complexity into the hundreds of millions of transistors. VLSI
stands for "Very Large Scale Integration". This is the field which involves
packing more and more logic devices into smaller and smaller areas. Thanks
to VLSI, circuits that would have taken board full of space can now be put
into a small space few millimeters across! This has opened up a big
opportunity to do things that were not possible before.

VLSI has been around for a long time, there is nothing new about it,
but as a side effect of advances in the world of computers, there has been a
dramatic proliferation of tools that can be used to design VLSI circuits.
Alongside, obeying Moore's law, the capability of an IC has increased
exponentially over the years, in terms of computation power, utilization of
available area, yield. The combined effect of these two advances is that
people can now put diverse functionality into the IC's, opening up new
18
frontiers. Examples are embedded systems, where intelligent devices are put
inside everyday objects, and ubiquitous computing where small computing
devices proliferate to such an extent that even the shoes you wear may
actually do something useful like monitoring your heartbeats.

Verilog was developed at a time when designers were looking for tools
to combine different levels of simulation. In the early 1980s, there were
switch-level simulators, gate-level simulators, functional simulators (often
written ad-hoc in software) and no simple means to combine them. Further,
the more-widespread, traditional programming languages themselves
were/are essentially sequential and thus "semantically challenged" when
modeling the concurrency of digital circuitry.Verilog was created by Phil
Moore in 1983-4 at Gateway Design Automation and the first simulator was
written a year later. It borrowed much from the existing languages of the
time: the concurrency aspects may be seen in both Modula and (earlier)
Simulate; the syntax is deliberately close to that of C; and the methods for
combining different levels of abstraction owe much to Hilo.

In 1989, Gateway Design Automation (and rights to Verilog) was

purchased by Cadence who put Verilog in the public domain in the following
year. This move did much to promote the use of Verilog since other
companies were able to develop alternatives tools to those of Cadence which,
in turn, allowed users to adopt Verilog without dependency on a single
(primarily workstation-tool) supplier. In 1992, work began to create an IEEE
standard (IEEE-1364) and in December 1995 the final draft was approved.
Thus Verilog has become an n international standard - which will further
increase its commercial development and use. At present, there is standards
activity to extend Verilog beyond purely digital circuits. This includes
Verilog-MS for "mixed signal specification" and Verilog- A for "analog"
design; the latter was recently approved (June 1996) by the board of Open
Verilog International and is now under consideration by the IEEE. In
addition, work is underway to automate the proof of "equivalence [between]
19
behavioral and synthesizable specifications" (see the Cambridge web site
below) to which Verilog readily lends itself.

While Verilog emerged from developments within private companies,

its main rival came from the American Department of Defense (DOD). In
1981, the DOD sponsored a workshop on hardware description languages
as part of its Very High Speed Integrated Circuits (VHSIC) program, and the
outcome formed a specification for the VHSIC hardware description
language (VHDL) in 1983. There is, of course, the question as to which
language is better. And this, of course, is a hard question to answer without
causing excitement and rebuttals from the marketing departments of the
less preferred language. However, the following points featured in a recent
debate in the VHDL and Verilog news groups.

The main factor is the language syntax - since Verilog is based on C

and VHDL is based on ADA. Verilog is easier to learn since C is a far simpler
language. It also produces more compact code: easier both to write and to
read. Furthermore, the large number of engineers who already know C
(compared to those who know ADA) makes learning and training easier.
VHDL is very strongly typed, and allows programmer to define their own
types although, in practice, the main types used are either the basic types of
the language itself, or those defined by the IEEE. The benefit is that type
checking is performed by the compiler which can reduce errors; the
disadvantage is that changing types must be done explicitly. Verilog has two
clear advantages over VHDL It allows switch-level modeling which some
designers find useful for exploring new circuits. It ensures that all signals
are initialized to "unknown" which ensure s that all designers will produce
the necessary logic to initialize their de sign - the base types in VHDL
initialize to zero and the "hasty" designer may omit a global reset.

20
 CHAPTER 4
DESIGNS CLASSIFICATION

There are Three Categories in today`s VLSI domain they are:

Analog
Small transistor count precision circuits such as Amplifiers, Data
converters, filters, Phase locked loops, Sensors etc.

ASIC
Progress in the fabrication of IC's has enabled us to create fast and
powerful circuits in smaller and smaller devices. This also means that we
can pack a lot more of functionality into the same area. The biggest
application of this ability is found in the design of ASIC's. These are IC's that
are created for specific purposes - each device is created to do a particular
job, and do it well. The most common application area for this is DSP -
21
signal filters, image compression, etc. To go to extremes, consider the fact
that the digital wristwatch normally consists of a single IC doing all the
time-keeping jobs as well as extra features like games, calendar, etc.

SOC
These are highly complex mixed signal circuits (digital and analog all
on the same chip). A network processor chip or a wireless radio chip is an
example of a SoC.

VLSI DESIGN STYLES

Several design styles can be considered for chip implementation of
specified algorithms or logic functions. Each design style has its own merits
and shortcomings, and thus a proper choice has to be made by designers in
order to provide the functionality at low cost.

FPGA
Fully fabricated FPGA chips containing thousands of logic gates or
even more, with programmable interconnects, are available to users for their
custom hardware programming to realize desired functionality. This design
style provides a means for fast prototyping and also for cost-effective chip
design, especially for low-volume applications. A typical field programmable
gate array (FPGA) chip consists of I/O buffers, an array of configurable logic
blocks (CLBs), and programmable interconnect structures. The
programming of the inter connects is implemented by programming of RAM
cells whose output terminals are connected to the gates of MOS pass
transistors. A general architecture of FPGA.A more detailed view showing
the locations of switch matrices used for interconnect routing. A simple CLB
(model XC2000 from XILINX) It consists of four signal input terminals (A, B,
C, D), a clock signal terminal, user-programmable multiplexers, an SR-
latch, and a look-up table (LUT). The LUT is a digital memory that stores the

22
truth table of the Boolean function. Thus, it can generate any function of up
to four variables or any two functions of three variables.

CLB is configured such that many different logic functions can be

realized by programming its array. More sophisticated CLBs have also been
introduced to map complex functions. The typical design flow of an FPGA
chip starts with the behavioral description of its functionality, using a
hardware description language such as VHDL. The synthesized architecture
is then technology-mapped (or partitioned) into circuits or logic cells. At this
stage, the chip design is completely described in terms of available logic
cells. Next, the placement and routing step assigns individual logic cells to
FPGA sites (CLBs) and determines the routing patterns among the cells in
accordance with the net list. After routing is completed, the on-chip
Performance of the design can be simulated and verified before downloading
the design for programming of the FPGA chip. The programming of the chip
remains valid as long as the chip is powered-on or until new programming is
done. In most cases, full utilization of the FPGA chip area is not possible -
many cell sites may remain unused.

The largest advantage of FPGA-based design is the very short turn-

around time, i.e., the time required from the start of the design process until
a functional chip is available. Since no physical manufacturing step is
necessary for customizing the FPGA chip, a functional sample can be
obtained almost as soon as the design is mapped into a specific technology.
The typical price of FPGA chips are usually higher than other realization
alternatives (such as gate array or standard cells) of the same design, but for
small-volume production of ASIC chips and for fast prototyping, FPGA offers
a very valuable option.

Gate array design

In view of the fast prototyping capability, the gate array (GA) comes
after the FPGA. While the design implementation of the FPGA chip is done

23
with user programming, that of the gate array is done with metal mask
design and processing. Gate array implementation requires a two-step
manufacturing process: The first phase, which is based on generic
(standard) masks, results in an array of uncommitted transistors on each
GA chip. These uncommitted chips can be stored for later customization,
which is completed by defining the metal interconnects between the
transistors of the array Since the patterning of metallic interconnects is
done at the end of the chip fabrication, the turn-around time can be still
short, a few days to a few weeks. a corner of a gate array chip which
contains bonding pads on its left and bottom edges, diodes for I/O
protection, nMOS transistors and pMOS transistors for chip output driver
circuits in the neighboring areas of bonding pads, arrays of nMOS
transistors and pMOS transistors, underpass wire segments, and power and
ground buses along with contact windows.

Magnified portion of the internal array with metal mask design (metal
lines highlighted in dark) to realize a complex logic function. Typical gate
array platforms allow dedicated areas, called channels, for intercell routing.
The availability of these routing channels simplifies the interconnections,
even using one metal layer only. The interconnection patterns to realize
basic logic gates can be stored in a library, which can then be used to
customize rows of uncommitted transistors according to the net list. While
most gate array platforms only contain rows of uncommitted transistors
separated by routing channels, some other platforms also offer dedicated
memory (RAM) arrays to allow a higher density where memory functions are
required. The layout views of a conventional gate array and a gate array
platform with two dedicated memory banks.
With the use of multiple interconnect layers, the routing can be achieved
over the active cell areas; thus, the routing channels can be removed as in
Sea-of-Gates (SOG) chips. Here, the entire chip surface is covered with
uncommitted nMOS and pMOS transistors. As in the gate array case,
neighboring transistors can be customized using a metal mask to form basic
24
logic gates. For intercell routing, however, some of the uncommitted
transistors must be sacrificed. This approach results in more flexibility for
interconnections, and usually in a higher density. The basic platform of a
SOG chip is shown in offers a brief comparison between the channeled (GA)
vs. the channel less (SOG) approaches.

Standard-cells based design

The standard-cells based design is one of the most prevalent full custom
design styles which require development of a full custom mask set. The
standard cell is also called the police. In this design style, all of the
commonly used logic cells are developed, characterized, and stored in a
standard cell library. A typical library may contain a few hundred cells
including inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-
latches, and flip-flops. Each gate type can have multiple implementations to
provide adequate driving capability for different fan outs. For instance, the
inverter gate can have standard size transistors, double size transistors, and
quadruple size transistors so that the chip designer can choose the proper
size to achieve high circuit speed and layout density. The characterization of
each cell is done for several different categories. It consists of

 delay time vs. load capacitance

 circuit simulation model
 timing simulation model
 fault simulation model
 cell data for place-and-route
 mask data
To enable automated placement of the cells and routing of inter-cell
connections, each cell layout is designed with a fixed height, so that a
number of cells can be abutted side-by-side to form rows. The power and
ground rails typically run parallel to the upper and lower boundaries of the
cell, thus, neighboring cells share a common power and ground bus. The
input and output pins are located on the upper and lower boundaries of the

25
cell. The layout of a typical standard cell. Notice that the nMOS transistors
are located closer to the ground rail while the pMOS transistors are placed
closer to the power rail.

Full custom design

Although the standard-cells based design is often called full custom
design, in a strict sense, it is somewhat less than fully custom since the
cells are pre-designed for general use and the same cells are utilized in
many different chip designs. In a fuller custom design, the entire mask
design is done anew without use of any library. However, the development
cost of such a design style is becoming prohibitively high. Thus, the concept
of design reuse is becoming popular in order to reduce design cycle time and
development cost. The most rigorous full custom design can be the design of
a memory cell, be it static or dynamic. Since the same layout design is
replicated, there would not be any alternative to high density memory chip
design. For logic chip design, a good compromise can be achieved by using a
combination of different design styles on the same chip, such as standard
cells, data-path cells and PLAs. In real full-custom layout in which the
geometry, orientation and placement of every transistor is done individually
by the designer, design productivity is usually very low - typically 10 to 20
transistors per day, per designer.

26
 CHAPTER-5

VERILOG
INTRODUCTION

Verilog HDL is a Hardware Description Language (HDL). A Hardware

Description Language is a language used to describe a digital system, for
example, a computer or a component of a computer. One may describe a
digital system at several levels. For example, an HDL might describe the
layout of the wires, resistors and transistors on an Integrated Circuit (IC)
chip, i.e., the switch level or, it might describe the logical gates and flip flops
in a digital system, i.e., the gate level. An even higher level describes the
registers and the transfers of vectors of information between registers. This
is called the Register Transfer Level (RTL). Verilog supports all of these
levels. However, this handout focuses on only the portions of Verilog which
support the RTL level.

Verilog is one of the two major Hardware Description Languages (HDL)

used by hardware designers in industry and academia. VHDL is the other
27
one. The industry is currently split on which is better. Many feel that Verilog
is easier to learn and use than VHDL. As one hardware designer puts it, "I
hope the competition uses VHDL." VHDL was made an IEEE Standard in
1987, while Verilog is still in the IEEE standardization process.
HISTORY
Verilog was introduced in 1985 by Gateway Design System
Corporation, now a part of Cadence Design Systems, Inc.'s Systems
Division. Until May, 1990, with the formation of Open Verilog International
(OVI), Verilog HDL was a proprietary language of Cadence. Cadence was
motivated to open the language to the Public Domain with the expectation
that the market for Verilog HDL-related software products would grow more
rapidly with broader acceptance of the language. Cadence realized that
Verilog HDL users wanted other software and service companies to embrace
the language and develop Verilog-supported design tools.

Verilog HDL allows a hardware designer to describe designs at a high

level of abstraction such as at the architectural or behavioral level as well as
the lower implementation levels (i. e. , gate and switch levels) leading to Very
Large Scale Integration (VLSI) Integrated Circuits (IC) layouts and chip
fabrication. A primary use of HDLs is the simulation of designs before the
designer must commit to fabrication. This handout does not cover all of
Verilog HDL but focuses on the use of Verilog HDL at the architectural or
behavioral levels. The handout emphasizes design at the Register Transfer
Level (RTL).
VERILOG CODE STRUCTURE
The Verilog language describes a digital system as a set of modules.
Each of these modules has an interface to other modules to describe how
they are interconnected. Usually we place one module per file but that is not
a requirement. The modules may run concurrently, but usually we have one
top level module which specifies a closed system containing both test data
and hardware models. The top level module invokes instances of other
modules.
28
 Modules can represent bits of hardware ranging from simple gates to
complete systems, e. g., a microprocessor. Modules can either be specified
behaviorally or structurally (or a combination of the two). A behavioral
specification defines the behavior of a digital system (module) using
traditional programming language constructs, e. g., ifs, and assignment
statements. A structural specification expresses the behavior of a digital
system (module) as a hierarchical interconnection of sub modules. At the
bottom of the hierarchy the components must be primitives or specified
behaviorally. Verilog primitives include gates, e. g., nand, as well as pass
transistors (switches).

The <module name> is an identifier that uniquely names the module.

The <port list> is a list of input, inout and output ports which are used to
connect to other modules. The <declares> section specifies data objects as
registers, memories and wires as wells as procedural constructs such as
functions and tasks. The <module items> may be initial constructs, always
constructs, continuous assignments or instances of modules.
VERILOG DESIGN ISSUES
There are now two industry standard hardware description languages,
VHDL and Verilog. The complexity of ASIC and FPGA designs has meant an
increase in the number of specialist design consultants with specific tools
and with their own libraries of macro and mega cells written in either VHDL
or Verilog. As a result, it is important that designers know both VHDL and
Verilog and that EDA tools vendors provide tools that provide an
environment allowing both languages to be used in unison. For example, a
designer might have a model of a PCI bus interface written in VHDL, but
wants to use it in a design with macros written in Verilog
CAPABILITY
Hardware structure can be modeled equally effectively in both VHDL
and Verilog. When modeling abstract hardware, the capability of VHDL can
sometimes only be achieved in Verilog when using the PLI. The choice of
which to use is not therefore based solely on technical capability but on:
29
 Personal preferences

 EDA tool availability

 commercial, business and marketing issues

The modeling constructs of VHDL and Verilog cover a slightly different

spectrum across the levels of behavioral abstraction; see Figure . HDL
modeling capability

COMPILATION
The Verilog language is still rooted in it's native interpretative mode.
Compilation is a means of speeding up simulation, but has not changed the
original nature of the language. As a result care must be taken with both the
compilation order of code written in a single file and the compilation order of
multiple files. Simulation results can change by simply changing the order
of compilation.
DATA TYPES
Compared to VHDL, Verilog data types are very simple, easy to use
and very much geared towards modeling hardware structure as opposed to
abstract hardware modeling. Unlike VHDL, all data types used in a Verilog
model are defined by the Verilog language and not by the user. There are net
data types, for example wire, and a register data type called reg. A model
with a signal whose type is one of the net data types has a corresponding
electrical wire in the implied modeled circuit. Objects, that is signals, of type
reg hold their value over simulation delta cycles and should not be confused
with the modeling of a hardware register. Verilog may be preferred because
of it's simplicity.

NETS AND REGISTERS

Apart from the port declarations, it is also possible to make
declarations that are entirely internal to the module. These declarations may
correspond to:

30
 Net variables correspond to structural connections between two or
more elements within the module. These are most often declared within a
model using the keyword wire. Alternative specifications of nets also exist to
define, for example, tristable nets (e.g., triand, trior), nets that can
implement wired AND or wired OR logic functions (e.g., wand, wor), and
power/ground nets (supply1 and supply0). The default value of a wire data
type is the tristate value z.

Register variables correspond to elements with memory that can store

their value until they are next updated. The most commonly used register
data type is denoted by the keyword reg, and its default value is the
unknown value x. The differences between a register declaration and a
hardware implementation of a register are subtle and include the fact that
the former may or may not be clocked and may be changed asynchronously.
In many cases, though, there is a one-to-one relationship between the two:
the burden of ensuring this is placed on the designer, who can force
synchronicity by updating the register variable in the Verilog description
only on the onset of a clock.

Unless specified in terms of an array, both the wire and reg keywords
represent a single bit. Particularly in the case of stored variables, more
compact representations are often convenient. To facilitate this, Verilog
permits register variables of type integer and real to store integer and real
variables, respectively. For example, in specifying the value of a counter, an
integer variable may be more convenientto use, and may make the
description more readable than the use of an array of bits. Another stored
variable that is provided for convenience is the integer time data type, which
is most commonly used in conjunction with the system function $time that
provides the current time point of the simulation as an integer. A
corresponding data type realtime can be used to store time in the form of a
real number.

31
 The following rules govern the mapping of ports of a module to nets or
registers:
• From the inside, an input must be a net data type, but not a register data
type. The connection external to the module may be either a register or a
net.
• An output port may be either a net or a register variable from the inside,
but must be a net variable on the outside.
• An input port must be a net both from the inside and the outside. The
rationale for this convention could be understood by observing that the
designer does not inadvertently specify a latency of more than one, i.e., two
storage elements are not inadvertently connected in series. In cases where
such a connection is desired, the notation permits such a connection
through an explicit and conscious action of connecting a net to a register.
VECTORS AND ARRAYS
It is often convenient to conceptualize groups of nets or registers in
terms of an array, for example, in case of a bus or a hardware register. For
this purpose, Verilog permits the definition of a vector for net and reg data
types. For example, an eight-bit address bus may be specified using the
declaration.

A few common applications of vectors and arrays are:

• Memory, in the form of RAMs, ROMs or register files, may be modeled
using arrays of vectors, as in the case of the cache declaration above.
• Strings of characters can be stored in reg vectors; the caveat here is that
each character requires eight bits, so that a string of n bits requires the
declaration of a reg vector of dimension 8×n.

CONSTANTS
The keyword parameter in Verilog announces the declaration of a
constant and assigns a value to it. Parameter values may be declared by
providing their values with the description. For example, within a module
my_module, one may define parameter number_of_bits = 32;
32
 The defparam statement in the upper level module permits the
declared values of the parameter within a module to be overridden. For
example, the value of the parameter number_of_bits in the module
my_module may be overridden in the upper level module. The my_module
x(); and my_module y(); statements will, respectively, instantiate the module
my_module and override the value of the internally declared parameter,
number_of_bits, from its default value of 32 to 16 and 64, respectively.
Alternatively, parameter instances can also be overridden during module
instantiation.

When xyz is instantiated, the parameters may be overridden as follows

xyz #(5,6,7,8) xyz1; This statement overrides the values of p1 through p4
with the numbers 5, 6, 7 and 8, respectively. Note that the order of
parameters in the instantiation corresponds directly to the order in which
they are defined in the module. If all of the parameters are not specified,
then the parameters are overridden in order of appearance.

NUMBER REPRESENTATION
Verilog permits numbers to be represented using a binary, octal, hex
or decimal representation. Apart from the normally permissible values (0
and 1 for binary, 0 through 7 for octal, 0 through F for hex, and 0 through 9
for decimal), each digit may take on the values x (unknown) or z (high
impedance). A number may be represented in a sized or unsized form,
depending on whether the number of bits is specified or not. A sized number
is represented in the form size ’ base_format number where size corresponds
to the number of bits, base_format takes on one of the possible values of b
(binary), o (octal), h (hex) or d (decimal), and number is the actual value of
the number. It is important to note that regardless of the base that is used,
the size refers to the number of binary bits in the representation. Examples
of numbers in a sized format include 8’b11111111, 8’o377, 8’h FF and

33
8’d255 In contrast, unsized numbers are written without a size specification,
which defaults to a value that varies with the simulator.

CHAPTER 6
DESIGN REUSABILITY
There is no concept of packages in Verilog. Functions and procedures
used within a model must be defined in the module. To make functions and
procedures generally accessible from different module statements the
functions and procedures must be placed in a separate system file and
included using the `include compiler directive.
EASIEST TO LEARN
Starting with zero knowledge of either language, Verilog is probably
the easiest to grasp and understand. This assumes the Verilog compiler
directive language for simulation and the PLI language is not included. If
these languages are included they can be looked upon as two additional
languages that need to be learned. VHDL may seem less intuitive at first for
two primary reasons. First, it is very strongly typed; a feature that makes it

34
robust and powerful for the advanced user after a longer learning phase.
Second, there are many ways to model the same circuit, specially those with
large hierarchical structures.
FORWARD AND BACK ANNOTATION
A spin-off from Verilog is the Standard Delay Format (SDF). This is a
general purpose format used to define the timing delays in a circuit. The
format provides a bidirectional link between, chip layout tools, and either
synthesis or simulation tools, in order to provide more accurate timing
representations. The SDF format is now an industry standard in it's own
right.

HIGH LEVEL CONSTRUCTS

Except for being able to parameterize models by overloading
parameter constants, there is no equivalent to the high-level VHDL modeling
statements in Verilog.

LANGUAGE EXTENSIONS
The use of language extensions will make a model non standard and
most likely not portable across other design tools. However, sometimes they
are necessary in order to achieve the desired results. The Programming
Language Interface (PLI) is an interface mechanism between Verilog models
and Verilog software tools. For example, a designer, or more likely, a Verilog
tool vendor, can specify user defined tasks or functions in the C
programming language, and then call them from the Verilog source
description. Use of such tasks or functions make a Verilog model
nonstandard and so may not be usable by other Verilog tools. Their use is
not recommended. Libraries There is no concept of a library in Verilog. This
is due to it's origins as an interpretive language.

LOW LEVEL CONSTRUCTS

35
 The Verilog language was originally developed with gate level modeling
in mind, and so has very good constructs for modeling at this level and for
modeling the cell primitives of ASIC and FPGA libraries. Examples include
User Defined Primitive s (UDP), truth tables and the specify block for
specifying timing delays across a module.

OPERATORS
The majority of operators are the same between the two languages.
Verilog does have very useful unary reduction operators that are not in
VHDL. A loop statement can be used in VHDL to perform the same operation
as a Verilog unary reduction operator. VHDL has the mod operator that is
not found in Verilog.
READABILITY
This is more a matter of coding style and experience than language
feature. VHDL is a concise and verbose language; its roots are based on Ada.
Verilog is more like C because its constructs are based approximately 50%
on C and 50% on Ada. For this reason an existing C programmer may prefer
Verilog over VHDL. Although an existing programmer of both C and Ada may
find the mix of constructs somewhat confusing at first. Whatever HDL is
used, when writing or reading an HDL model to be synthesized it is
important to think about hardware intent.

IMPORTANCE OF HDLS

HDLs have many advantages compared to traditional schematic-based

design.

 Designs can be described at a very abstract level by use of HDLs.

Designers can write their RTL description without choosing a specific
fabrication technology. Logic synthesis tools can automatically convert
the design to any fabrication technology. If a new technology emerges,
designers do not need to redesign their circuit. They simply input the
RTL description to the logic synthesis tool and create a new gate-level
36
 netlist, using the new fabrication technology. The logic synthesis tool
will optimize the circuit in area and timing for the new technology.
 By describing designs in HDLs, functional verification of the design
can be done early in the design cycle. Since designers work at the RTL
level, they can optimize and modify the RTL description until it meets
the desired functionality. Most design bugs are eliminated at this
point. This cuts down design cycle time significantly because the
probability of hitting a functional bug at a later time in the gate-level
netlist or physical layout is minimized.

 Designing with HDLs is analogous to computer programming. A

textual description with comments is an easier way to develop and
debug circuits. This also provides a concise representation of the
design, compared to gate-level schematics. Gate-level schematics are
almost incomprehensible for very complex designs.

HDL-based design is here to stay. With rapidly increasing complexities of

digital circuits and increasingly sophisticated EDA tools, HDLs are now the
dominant method for large digital designs. No digital circuit designer can
afford to ignore HDL-based design.
POPULARITY OF VERILOG HDL
Verilog HDL has evolved as a standard hardware description language.
Verilog HDL offers many useful features
 Verilog HDL is a general-purpose hardware description language that
is easy to learn and easy to use. It is similar in syntax to the C
programming language. Designers with C programming experience
will find it easy to learn Verilog HDL.
 Verilog HDL allows different levels of abstraction to be mixed in the
same model. Thus, a designer can define a hardware model in terms
of switches, gates, RTL, or behavioral code. Also, a designer needs to
learn only one language for stimulus and hierarchical design.

37
  Most popular logic synthesis tools support Verilog HDL. This makes it
the language of choice for designers.

 All fabrication vendors provide Verilog HDL libraries for postlogic

synthesis simulation. Thus, designing a chip in Verilog HDL allows
the widest choice of vendors.

 The Programming Language Interface (PLI) is a powerful feature that

allows the user to write custom C code to interact with the internal
data structures of Verilog. Designers can customize a Verilog HDL
simulator to their needs with the PLI.

TRENDS IN HDLS
 The speed and complexity of digital circuits have increased rapidly.
Designers have responded by designing at higher levels of abstraction.
Designers have to think only in terms of functionality. EDA tools take
care of the implementation details. With designer assistance, EDA
tools have become sophisticated enough to achieve a close-to-
optimum implementation.
 The most popular trend currently is to design in HDL at an RTL level,
because logic synthesis tools can create gate-level netlists from RTL
level design. Behavioral synthesis allowed engineers to design directly
in terms of algorithms and the behavior of the circuit, and then use
EDA tools to do the translation and optimization in each phase of the
design. However, behavioral synthesis did not gain widespread
acceptance. Today, RTL design continues to be very popular. Verilog
HDL is also being constantly enhanced to meet the needs of new
verification methodologies.

 Formal verification and assertion checking techniques have emerged.

Formal verification applies formal mathematical techniques to verify
the correctness of Verilog HDL descriptions and to establish
equivalency between RTL and gate-level netlists. However, the need to

38
 describe a design in Verilog HDL will not go away. Assertion checkers
allow checking to be embedded in the RTL code. This is a convenient
way to do checking in the most important parts of a design.

 New verification languages have also gained rapid acceptance. These

languages combine the parallelism and hardware constructs from
HDLs with the object oriented nature of C++. These languages also
provide support for automatic stimulus creation, checking, and
coverage. However, these languages do not replace Verilog HDL. They
simply boost the productivity of the verification process. Verilog HDL
is still needed to describe the design.

 For very high-speed and timing-critical circuits like microprocessors,

the gate-level netlist provided by logic synthesis tools is not optimal.
In such cases, designers often mix gate-level description directly into
the RTL description to achieve optimum results. This practice is
opposite to the high-level design paradigm, yet it is frequently used for
high-speed designs because designers need to squeeze the last bit of
timing out of circuits, and EDA tools sometimes prove to be
insufficient to achieve the desired results.

 Another technique that is used for system-level design is a mixed

bottom-up methodology where the designers use either existing
Verilog HDL modules, basic building blocks, or vendor-supplied core
blocks to quickly bring up their system simulation. This is done to
reduce development costs and compress design schedules. For
example, consider a system that has a CPU, graphics chip, I/O chip,
and a system bus. The CPU designers would build the next-generation
CPU themselves at an RTL level, but they would use behavioral
models for the graphics chip and the I/O chip and would buy a
vendor-supplied model for the system bus. Thus, the system-level
simulation for the CPU could be up and running very quickly and long

39
 before the RTL descriptions for the graphics chip and the I/O chip are
completed.

TYPICAL DESIGN FLOW

Fig 6.1 Typical Design Flow

A typical design flow for designing VLSI-IC circuits is shown in the below
Figure 1. Unshaded blocks show the level of design representation; shaded
blocks show processes in the design flow.

The design flow shown in Figure 1 is typically used by designers who use
HDLs. In any design, specifications are written first. Specifications describe
abstractly the functionality, interface, and overall architecture of the digital

40
circuit to be designed. At this point, the architects do not need to think
about how they will implement this circuit. A behavioral description is then
created to analyze the design in terms of functionality, performance, and
compliance to standards, and other high-level issues. Behavioral
descriptions are often written with HDLs. The behavioral description is
manually converted to an RTL description in an HDL. The designer has to
describe the data flow that will implement the desired digital circuit. From
this point onward, the design process is done with the assistance of EDA
tools.

Logic synthesis tools convert the RTL description to a gate-level netlist. A

gate-level netlist is a description of the circuit in terms of gates and
connections between them. Logic synthesis tools ensure that the gate-level
netlist meets timing, area, and power specifications. The gate-level netlist is
input to an Automatic Place and Route tool, which creates a layout. The
layout is verified and then fabricated on a chip.

Thus, most digital design activity is concentrated on manually optimizing

the RTL description of the circuit. After the RTL description is frozen, EDA
tools are available to assist the designer in further processes. Designing at
the RTL level has shrunk the design cycle times from years to a few months.
It is also possible to do many design iterations in a short period of time.
Behavioral synthesis tools have begun to emerge recently. These tools can
create RTL descriptions from a behavioral or algorithmic description of the
circuit. As these tools mature, digital circuit design will become similar to
high-level computer programming. Designers will simply implement the
algorithm in an HDL at a very abstract level. EDA tools will help the
designer convert the behavioral description to a final IC chip.

It is important to note that, although EDA tools are available to automate

the processes and cut design cycle times, the designer is still the person
who controls how the tool will perform. EDA tools are also susceptible to the
"GIGO : Garbage In Garbage Out" phenomenon. If used improperly, EDA
41
tools will lead to inefficient designs. Thus, the designer still needs to
understand the nuances of design methodologies, using EDA tools to obtain
an optimized design.

42
 CHAPTER 7

XILINX

XILINX ISE OVERVIEW

The Integrated Software Environment (ISE™) is the Xilinx® design

software suite that allows you to take your design from design entry through
Xilinx device programming. The ISE Project Navigator manages and
processes your design through the following steps in the ISE design flow.

DESIGN ENTRY
Design entry is the first step in the ISE design flow. During design
entry, you create your source files based on your design objectives. You can
create your top-level design file using a Hardware Description Language
(HDL), such as VHDL, Verilog, or ABEL, or using a schematic. You can use
multiple formats for the lower-level source files in your design.

SYNTHESIS
After design entry and optional simulation, you run synthesis. During
this step, VHDL, Verilog, or mixed language designs become netlist files that
are accepted as input to the implementation step.
IMPLEMENTATION
After synthesis, you run design implementation, which converts the
logical design into a physical file format that can be downloaded to the
selected target device. From Project Navigator, you can run the
implementation process in one step, or you can run each of the
implementation processes separately. Implementation processes vary
depending on whether you are targeting a Field Programmable Gate Array
(FPGA) or a Complex Programmable Logic Device (CPLD).

43
VERIFICATION
You can verify the functionality of your design at several points in the
design flow. You can use simulator software to verify the functionality and
timing of your design or a portion of your design. The simulator interprets
VHDL or Verilog code into circuit functionality and displays logical results of
the described HDL to determine correct circuit operation. Simulation allows
you to create and verify complex functions in a relatively small amount of
time. You can also run in-circuit verification after programming your device.

DEVICE CONFIGURATION
After generating a programming file, you configure your device. During
configuration, you generate configuration files and download the
programming files from a host computer to a Xilinx device.
PROJECT NAVIGATOR OVERVIEW
Project Navigator organizes your design files and runs processes to move
the design from design entry through implementation to programming the
targeted Xilinx® device. Project Navigator is the high-level manager for your
Xilinx FPGA and CPLD designs, which allows you to do the following:

 Add and create design source files, which appear in the Sources
window

 Modify your source files in the Workspace

 Run processes on your source files in the Processes window

 View output from the processes in the Transcript window

PROJECT NAVIGATOR MAIN WINDOW

The following figure shows the Project Navigator main window, which
allows you to manage your design starting with design entry through device
configuration.

44
 Fig 7.1 project navigator

1. Toolbar

2. Sources window

3. Processes window

4. Workspace
5. Transcript window
USING THE SOURCES WINDOW
The first step in implementing your design for a Xilinx® FPGA or
CPLD is to assemble the design source files into a project. The Sources tab
in the Sources window shows the source files you create and add to your

45
project, as shown in the following figure. For information on creating
projects and source files, see Creating a Project and Creating a Source File.

Fig 7.2 SOURCES WINDOW

The Design View ("Sources for") drop-down list at the top of the
Sources tab allows you to view only those source files associated with the
selected Design View (for example, Synthesis/Implementation). For details,
see Using the Design Views. The "Number of" drop-down list, Resources
column, and Preserve column are available for designs that use Partitions.
For details, see Using Partitions.

The Sources tab shows the hierarchy of your design. You can collapse
and expand the levels by clicking the plus (+) or minus (-) icons. Each
source file appears next to an icon that shows its file type. The file you select
determines the processes available in the Processes window. You can
double-click a source file to open it for editing in the Workspace. For
information on the different file types, see Source File Types.

You can change the project properties, such as the device family to
target, the top-level module type, the synthesis tool, the simulator, and the
generated simulation language. For information, see Changing Project,
Source, and Snapshot Properties.

46
 Depending on the source file and tool you are working with, additional
tabs are available in the Sources window:

 Always available: Sources tab, Snapshots tab, Libraries tab

 Constraints Editor: Timing Constraints tab
 Floor plan Editor: Translated Netlist tab, Implemented Objects tab
 iMPACT: Configuration Modes tab
 Schematic Editor: Symbols tab
 RTL and Technology Viewers: Design tab
 Timing Analyzer: Timing tab
USING THE PROCESSES WINDOW
The Processes tab in the Processes window allows you to run actions
or "processes" on the source file you select in the Sources tab of the Sources
window. The processes change according to the source file you select.

The Process tab shows the available processes in a hierarchical  view.

You can collapse and expand the levels by clicking the plus (+) or minus (-)
icons. Processes are arranged in the order of a typical design flow: project
creation, design entry, constraints management, synthesis, implementation,
and programming file creation.

Depending on the source file and tool you are working with, additional tabs
are available in the Processes window:

 Always available: Processes tab

 Floor plan Editor: Design Objects tab, Implemented - Selection tab
 iMPACT: Configuration Operations tab
 ISE Simulator: Hierarchy Browser tab
 Schematic Editor: Options tab
 Timing Analyzer: Timing Objects tab

PROCESS TYPES

47
 The following types of processes are available as you work on your
design:
 Tasks
When you run a task process, the ISE software runs in "batch mode,"
that is, the software processes your source file but does not open any
additional software tools in the Workspace. Output from the processes
appears in the Transcript window.
 Reports
Most tasks include report sub-processes, which generate a summary or
status report, for example, the Synthesis Report or Map Report. When
you run a report process, the report appears in the Workspace.
 Tools
When you run a tools process, the related tool launches in standalone
mode or appears in the Workspace where you can view or modify your
design source files.

PROCESS STATUS
As you work on your design, you may make changes that require some or
all of the processes to be rerun. For example, if you edit a source file, it may
require that the Synthesis process and all subsequent process be rerun.
Project Navigator keeps track of the changes you make and shows the status
of each process with the following status icons:

 Running

This icon shows that the process is running.

 Up-to-date

This icon shows that the process ran successfully with no errors or
warnings and does not need to be rerun. If the icon is next to a report
process, the report is up-to-date; however, associated tasks may have

48
 warnings or errors. If this occurs, you can read the report to determine
the cause of the warnings or errors.

 Warnings reported

This icon shows that the process ran successfully but that warnings
were encountered.

 Errors reported

This icon shows that the process ran but encountered an error.

 Out-of-Date

This icon shows that you made design changes, which require that the
process be rerun. If this icon is next to a report process, you can rerun
the associated task process to create an up-to-date version of the
report.

 No icon

If there is no icon, this shows that the process was never run.

RUNNING PROCESSES
To run a process, you can do any of the following:

 Double-click the process

 Right-click while positioned over the process, and select Run from the
popup menu, as shown in the following figure.

49
 Fig 7.3 RUNNING PROCESSES

 Select the process, and then click the Run toolbar button .

 To run the Implement Design process and all preceding processes on

the top module for the design, select Process>Implement Top
Module, or click the Implement Top Module toolbar button .

When you run a process, Project Navigator automatically processes your

design as follows:

 Automatically runs lower-level processes

When you run a high-level process, Project Navigator runs associated
lower-level processes or sub-processes. For example, if you run
Implement Design for your FPGA design, all of the following sub-
processes run: Translate, Map, and Place & Route.
 Automatically runs preceding processes
When you run a process, Project Navigator runs any preceding
processes that are required, thereby "pulling" your design through the
design flow. For example, to pull your design through the entire flow,
double-click Generate Programming File.
 Automatically runs related processes for out-of-date processes
If you run an out-of-date process, Project Navigator runs that process
and any related processes required to bring that process up to date. It
does not necessarily run all preceding processes. For example if you
change your UCF file, the Synthesize process remains up to date, but
the Translate process becomes out of date. If you run the Map process,
Project Navigator runs Translate but does not run Synthesize.

SETTING PROCESS PROPERTIES

Most processes have a set of properties associated with them.
Properties control specific options, which correspond to command line
options. When properties are available for a process, you can right-click
50
while positioned over the process and select Properties from the popup
menu, as shown in the following figure.

Fig 7.4 SETTING PROCESS PROPERTIES

When you select Properties, a Process Properties dialog box appears,

with standard properties that you can set. The Process Properties dialog box
differs depending on the process you select.
After you become familiar with the standard properties, you can set
additional, advanced properties in the Process Properties dialog box;
however, setting these options is not recommended if you are just getting
started with using the ISE software. When you enable the advanced
properties, both standard and advanced properties appear in the Process
Properties dialog box.

USING THE WORKSPACE

When you open a project source file, open the Language Templates, or
run certain processes, such as viewing reports or logs, the corresponding file
or view appears in the Workspace. You can open multiple files or views at
one time. Tabs at the bottom of the Workspace show the names for each file
or view. Click a tab to bring it to the front.

To open a file or view in a standalone window outside of the Project

Navigator Workspace, use the Float toolbar button. To dock a floating
window, use the Dock toolbar button.

51
  Float
 Dock

USING THE TRANSCRIPT WINDOW

The Console tab of the Transcript window shows output messages from
the processes you run. When the following icons appear next to a message,
you can right-click the message and select Goto Answer Record to open the
Xilinx website and show any related Answer Records. If a line number
appears as part of the message, you can right-click the message and select
Goto Source to open the source file with the appropriate line number
highlighted.

 Warning
 Error
Depending on the source file and tool you are working with, additional
tabs are available in the Transcript window:
 Always available: Console tab, Errors tab, Warnings tab, Tcl Shell tab,
Find in Files tab
 ISE Simulator: Simulation Console tab
 RTL and Technology Viewers: View by Name tab, View by Category tab

USING THE TOOLBARS

Toolbars provide convenient access to frequently used commands.
Click once on a toolbar button to execute a command. To see a short popup
description of a toolbar button, hold the mouse pointer over the button for
about two seconds. A longer description appears in the status bar at the
bottom of the main window.

52
 CHAPTER 8
CREATING A PROJECT
Project Navigator allows you to manage your FPGA and CPLD designs
using an ISE™ project, which contains all the files related to your design.
First, you must create a project and then add source files. With your project
open in Project Navigator, you can view and run processes on all the files in
your design. Project Navigator provides a wizard to help you create a new
project, as follows.

7.4.1 TO CREATE A PROJECT

1. Select File > New Project.
2. In the New Project Wizard Create New Project page, do the following:

a) In the Project Name field, enter a name for the project. Follow the
naming conventions described in File Naming Conventions.

53
b) In the Project Location field, enter the directory name or browse to the
directory.
c) In the Top-Level Source Type drop-down list, select one of the
following:
 HDL: Select this option if your top-level design file is a VHDL, Verilog,
or ABEL (for CPLDs) file. An HDL Project can include lower-level
modules of different file types, such as other HDL files, schematics,
and "black boxes," such as IP cores and EDIF files.
 Schematic: Select this option if your top-level design file is a
schematic file. A schematic project can include lower-level modules of
different file types, such as HDL files, other schematics, and "black
boxes," such as IP cores and EDIF files. Project Navigator
automatically converts any schematic files in your design to structural
HDL before implementation; therefore, you must specify a synthesis
tool when working with schematic projects, as described in step 5.
 EDIF: Select this option if you converted your design to this file type,
for example, using a synthesis tool. Using this file type allows you to
skip the Project Navigator synthesis process and to start with the
implementation processes.
 NGC/NGO: Select this option if you converted your design to this file
type, for example, using a synthesis tool. Using this file type allows
you to skip the Project Navigator synthesis process and start with the
implementation processes.
3. Click Next.
4. If you are creating an HDL or schematic project, skip to the next step.
If you are creating an EDIF or NGC/NGO project, do the following in
the Import EDIF/NGC Project page:
a) In the Input Design field, enter the name of the input design file, or
browse to the file and select it.

54
 b) Select Copy the input design to the project directory to copy your file
to the project directory. If you do not select this option, your file is
accessed from the remote location.
c) In the Constraint File field, enter the name of the constraints file, or
browse to the file and select it.
d) Select Copy the constraints file to the project directory to copy your
file to the project directory. If you do not select this option, your file is
accessed from the remote location.
e) Click Next.
3 In the Device Properties page, set the following options. These settings
affect other project options, such as the types of processes that are available
for your design.
 Product Category
 Family
 Device
 Package
 Speed
 Top-Level Source Type
 Synthesis Tool

Select one of the following synthesis tools and the HDL language for your
project. VHDL/Verilog is a mixed language flow. If you plan to run
behavioral simulation, your simulator must support multiple language
simulation.
 XST (Xilinx® Synthesis Technology)
XST is available with ISE Foundation™ software installations. It supports
projects that include schematic design files and projects that include mixed
language source files, such as VHDL and Verilog sources files in the same
project. Synplify and Synplify Pro (Synplicity®, Inc.)
The Synplify® software does not support projects that include mixed
language source files. The Synplify Pro® software supports projects that

55
include mixed language source files, such as VHDL and Verilog sources files
in the same project. The Synplify and Synplify Pro software do not support
projects that include schematic design files.

Precision(Mentor Graphics®, Inc.)

The Precision® software supports projects that include schematic design
files and projects that include mixed language source files, such as VHDL
and Verilog sources files in the same project.
 Simulator
Select one of the following simulators and the HDL language for simulation.
 ISE Simulator(Xilinx®, Inc.)
This simulator allows you to run integrated simulation processes as part
of your ISE design flow. For more information, see the ISE Simulator Help.
 ModelSim (Mentor Graphics®, Inc.)
You can run integrated simulation processes as part of your ISE design
flow using any of the following ModelSim® editions: ModelSim Xilinx Edition
(MXE), ModelSim MXE Starter, ModelSim PE, or ModelSim SE™. For more
information on ModelSim, including the differences between each edition,
see Using the ModelSim Simulator.
 NC-Sim (Cadence®, Inc.)
The NC-Sim simulator is not integrated with ISE and must be run
standalone. For more information, see the documentation provided with the
simulator.
 VCS (Synopsys®, Inc.)
The VCS® simulator is not integrated with ISE and must be run
standalone. For more information, see the documentation provided with the
simulator.
 Other
Select this option if you do not have ISE Simulator or ModelSim installed
or if you want to run simulation outside of Project Navigator. This instructs
Project Navigator to disable the integrated simulation processes for your
project.
56
  Preferred Language
Select one of the following to set your preferred language. The Preferred
Language project property controls the default setting for process properties
that generate HDL output. If the Synthesis Tool and/or Simulator options
are set to a single-language tool, the default language for generated HDL
output files will be automatically chosen appropriately. If both the Synthesis
Tool and Simulator options are set to mixed-language (VHDL/Verilog) tools,
you can use the Preferred Language property to select the language in which
generated HDL output will be created.    
 Verilog
Select this option if both Synthesis Tool and Simulation are set to mixed-
language and you want the default language to be Verilog.
 VHDL
Select this option if both Synthesis Tool and Simulation are set to mixed-
language and you want the default language to be VHDL.
 N/A
This option will appear if both Synthesis Tool and Simulation are set to a
single language.
 Enable Enhanced Design Summary
Select this option to show the number of errors and warnings for each of
the Detailed Reports in the Design Summary.

Enable Message Filtering

Select this option to turn on Message Filtering.

Display Incremental Messages

Select this option to show the number of new messages for the most
recent software run in the Design Summary. You must enable this option
and then run the software to show the number of new messages.

6. If you are creating an EDIF or NGC/NGO project, skip to step 8. If you

are creating an HDL or schematic project,

57
 7. Click Next, and optionally, add existing source files to your project in
the Add Existing Sources page.
8. Click Next to display the Project Summary page.
9. Click Finish to create the project.
WHAT TO EXPECT
Project Navigator creates the project file, project_name.ise, in the
directory you specified. All source files related to the project appear in the
Project Navigator Sources tab. Project Navigator manages your project based
on the project properties (top-level module type, device type, synthesis tool,
and language) you selected when you created the project. It organizes all the
parts of your design and keeps track of the processes necessary to move the
design from design entry through implementation to programming the
targeted Xilinx device.
WHAT TO DO NEXT
You can perform any of the following:
 Create and add source files to your project.
 Add existing source files to your project.
 Run processes on your source files.

USING ISE EXAMPLE PROJECTS

To help familiarize you with the ISE™ software and with FPGA and
CPLD designs, a set of example designs is provided with Project Navigator.
The examples show different design techniques and source types, such as
VHDL, Verilog, ABEL, schematic, or EDIF, and include different constraints
and stimulus files.
TO OPEN AN EXAMPLE
1. Select File > Open Example.
2. In the Open Example Project dialog box, select the Sample Project
Name that you want to use.

58
 To help you choose an example project, the Project Description field
describes each project. In addition, you can scroll to the right to see
additional fields, which provide details about the project.

3. In the Destination Directory field, enter a directory name or browse to

the directory.
4. Click OK.
WHAT TO EXPECT
The example project is placed in the directory you specified in the
Destination Directory field and is automatically opened in Project Navigator.
You can then run processes on the example project and save any changes.
CREATING A SOURCE FILE
A source file is any file that contains information about a design.
Project Navigator provides a wizard to help you create new source files for
your project.
WHAT TO DO FIRST
Open a project in Project Navigator.

TO CREATE A SOURCE FILE

1. Select Project > New Source.
2. In the New Source Wizard, select the type of source you want to
create.

Different source types are available depending on your project

properties (top-level module type, device type, synthesis tool, and
language). Some source types launch additional tools to help you
create the file, as described in Source File Types.

3. Enter a name for the new source file in the File Name field. Follow the
naming conventions described in File Naming Conventions.

59
 4. In the Location field, enter the directory name or browse to the
directory.
5. Select Add to Project to automatically add this source to the project.

6. Click Next.
7. If you are creating a source file that needs to be associated with an
existing source file, select the appropriate source file, and click Next. If
this does not apply, skip to the next step.
8. In the New Source Wizard - Summary window, verify the information
for the new source, and click Finish.

WHAT TO EXPECT
After you click Finish, the New Source wizard closes. In some cases, a
related tool is launched in which you can finish creating your file. After the
source file is created, it appears in the Project Navigator Sources tab. If you
selected Add to Project when creating the source file, the file is automatically
added to the project.

ADDING A SOURCE FILE TO A PROJECT

Project Navigator allows you to add an existing source file to a project.
The source file can reside in the project directory or in a remote directory. If
you generated your source file using the New Source wizard and selected
Add to Project, you do not need to add the source file to your project; it is
automatically part of your project.
WHAT TO DO FIRST
Open a project in Project Navigator.

TO ADD A SOURCE FILE TO A PROJECT

1. Select Project>Add Source.
2. In the Add Existing Sources dialog box, browse to the source file and
select it.
3. Click Open.
60
 4. In the Adding Source Files dialog box, select the Design View in which
you want the source file to appear.

5. Click OK.

WHAT TO EXPECT
The source file is added to your project, and the file appears as part of
the design hierarchy in the Sources tab. If you added a remote source, the
directory path appears with the file name.
If the source file you added refers to files that have not been added to
the project, the file names appear in the design hierarchy as undefined files
. You must add the referenced files to the project for the ISE software to
track changes to the files.
FPGA DESIGN FLOW OVERVIEW
The ISE™ design flow comprises the following steps: design entry,
design synthesis, design implementation, and Xilinx® device programming.
Design verification, which includes both functional verification and timing
verification, takes places at different points during the design flow. This
section describes what to do during each step. For additional details on each
design step, click a box in the following figure.

Fig 8.1 FPGA design flow overview

61
DESIGN ENTRY
Create an ISE project as follows:
1. Create a project.
2. Create files and add them to your project, including a user constraints
(UCF) file.
3. Add any existing files to your project.
4. Assign constraints such as timing constraints, pin assignments, and
area constraints.

FUNCTIONAL VERIFICATION
You can verify the functionality of your design at different points in the
design flow as follows:
 Before synthesis, run behavioral simulation (also known as RTL
simulation).
 After Translate, run functional simulation (also known as gate-level
simulation), using the SIMPRIM library.
 After device programming, run in-circuit verification.

62
 CHAPTER 9
DESIGN SYNTHESIS
DESIGN IMPLEMENTATION
Implement your design as follows:
1. Implement your design, which includes the following steps:
 Translate
 Map
 Place and Route

2. Review reports generated by the Implement Design process, such as

the Map Report or Place & Route Report, and change any of the
following to improve your design:

 Process properties
 Constraints
 Source files

3. Synthesize and implement your design again until design

requirements are met.

TIMING VERIFICATION

63
 You can verify the timing of your design at different points in the design
flow as follows:
 Run static timing analysis at the following points in the design flow:

 After Map
 After Place & Route
 Run timing simulation at the following points in the design flow:
 After Map (for a partial timing analysis of CLB and IOB delays)
 After Place and Route (for full timing analysis of block and net
delays)

XILINX DEVICE PROGRAMMING

Program your Xilinx device as follows:
1. Create a programming file (BIT) to program your FPGA.
2. Generate a PROM, ACE, or JTAG file for debugging or to download to
your device.
3. Use impact to program the device with a programming cable.

FPGA BASIC FLOW

With designs of low to moderate complexity, you can process your design
using the ISE™ Basic Flow as follows:
1. Create an ISE project as follows:
a) Create a project.
b) Create files and add them to your project, including a user constraints
(UCF) file.
c) Add any existing files to your project.
d) Edit the design files to specify design functionality.
e) Optionally, use the Language Templates to assist in coding of the
design.
f) Edit the design test bench or waveform files to drive stimulus for
testing the design files. Optionally, do the following:

64
  Use the Test Bench Waveform Editor to specify stimulus for the
design.
 Use the Language Templates to assist in coding of the test bench.

Assign constraints such as timing constraints, pin assignments, and area

constraints.

2. Run behavioral simulation (also known as RTL simulation).

3. Repeat steps 1 and 2 until desired functionality is achieved.
4. Synthesize your design.
5. Implement your design as follows:

a) Run the Implement Design process on your top module , which

automatically runs the following processes:

 Translate
 Map
 Place and Route

b) Review reports generated by the Implement Design process, such as

the Map Report or the Place and Route Report, and change any of the
following to improve your design:

 Process properties
 Constraints
 Source files
c) Modify the design as necessary, simulate, synthesize, and implement
your design again until design requirements are met.
d) Run timing simulation to verify end functionality and timing of the
design.

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OUTPUT

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CONCLUSION

FIR filter block designed to optimize the PPG unit and it reduces the area
and delay power. It reduces the energy per samples (EPS) value upto 85%
compared to the existing system . An area and the power are reduced with
the FIR filter block. Using the FIR filter block architechture size will be
reduced. The direct -form LMS adaptive filter is more efficient than the
transpose-form LMS adaptive filter . In ten direct form LMS structure there
is no need of pipelined concept . So it consumes more power than existing
system . From this method, more than 92% power consumption is possible
while using the direct form structure.

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REFERENCES

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[4] G. Long, F. Ling, and J. G. Proakis, “The LMS algorithm with delayed coefficient
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[5] ——, “Corrections to ‘The LMS algorithm with delayed coefficient adaptation’,” IEEE
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[6] H. Herzberg, R. Haimi-Cohen, and Y. Be’ery, “A systolic array realization of an LMS

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[7] M. D. Meyer and D. P. Agrawal, “A high sampling rate delayed LMS filter architecture,”
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[8] S. Ramanathan and V. Visvanathan, “A systolic architecture for LMS adaptive filtering
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 [9] Y. Yi, R. Woods, L.-K. Ting, and C. F. N. Cowan, “High speed FPGAbased
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