NXP PMIC Solution For Renesas R-Car H3 Processor: Rev. 1 - 9 December 2020 Application Note

AN13003
NXP PMIC solution for Renesas R-Car H3 processor

Rev. 1 — 9 December 2020 Application note
Document information
Information Content
Keywords R-Car H3 power solution, power management, functional safety, power
sequence
Abstract This application note shows how to supply Renesas R-Car H3 processor
based on NXP multiple power management integrated circuit (PMIC) and how
to achieve the functional safety target.
NXP Semiconductors
AN13003
Revision history
Rev Date Description
1 20201209 initial version
AN13003 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
Application note Rev. 1 — 9 December 2020

2 / 17
NXP Semiconductors
AN13003
1 Introduction
The NXP PMIC solution for R-Car H3 processor includes power-up sequence,
power-down sequence, and safety mechanisms. They enable the system to satisfy
automotive safety integrity level (ASIL) B. The application note also includes schematic
diagrams and the BOM, which makes the completion of power system design easy.
2 Description
R-Car H3 is a high performance automotive computing platform for autonomous-driving
era compliant with the ISO 26262 (ASIL B) functional safety standard.
NXP multi-PMIC power solution for R-Car H3 includes four PMICs. PF82, PF5020,
PF5024, and PF52 are developed in compliance with ISO 26262 process. They highly
integrate multiple regulators so that the power solution is well-suited to supply high
performance ADAS processor like R-Car H3. These PMICs support system application
safety requirements up to ASIL B safety level. There are also quality management (QM)
versions of these PMICs for low-cost design.
PF82, PF5020, PF5024, and PF52 built-in one time programmable (OTP) memory stores
key startup configurations. These NXP PMICs also feature dedicated synchronization
blocks for synchronizing power-up sequence and power-down sequence of multiple
PMICs. To save design effort and reduce the system complexity, no external controller is
needed for system default configuration and power-up synchronization.
Figure 1 shows Renesas R-Car H3 processor power solution block diagram. Four PMICs
are implemented in the system to spread thermal dissipation.

3 / 17
NXP Semiconductors
AN13003
PF82 R-CAR
4.0 V to 5.5 V H3
VIN BUCK1
BUCK2 0.82 V/10 A
PWR_CTRL VDD_0.82V (0.82 V/8 A)
PWRON BUCK3
BUCK4
1.8 V/2.5 A
BUCK5 DDR0_1.8V (1.8 V/0.25 A)
1.8 V/2.5 A
BUCK6 DDR1_1.8V (1.8 V/0.25 A)
3.3 V/2.5 A
BUCK7 D1_3.3V (3.3 V/1 A)
3.3 V/0.4 A
LDO1 VLDOSD0_3.3V (3.3 V/0.17 A)
EN_CTRL
EN
LDO2
FSOB
3.3 V/0.4 A
LDO3 VLDOSD0_3.3V (3.3 V/0.17 A)
I2C
XFAILB LDO4
PGOOD
PF52
VIN BUCK1 0.825 V/16 A
DVFS_0.82V (0.825 V/16 A)
BUCK2
PWRON
EN
I2C
XFAILB
PGOOD
PF5024
VIN BUCK1 1.1 V/5 A
DDR0_1.1V (1.1 V/4 A)
BUCK2
PWRON BUCK3 1.1 V/5 A
DDR1_1.1V (1.1 V/4 A)
BUCK4
EN
I2C
XFAILB
PGOOD
PF5020
VIN BUCK1 1.8 V/5 A
D_1.8V (1.8 V/3 A)
BUCK2
3.3 V/2.5 A
PWRON BUCK3 D2_3.3V (3.3 V/2 A)
2.5 V/0.4 A
LDO VLDO_2.5V (2.5 V/0.3 A)
EN
I2C
XFAILB
PGOOD
aaa-039792
Figure 1. NXP power solution for Renesas R-Car H3

4 / 17
NXP Semiconductors
AN13003
3 Power solution
PF82, PF52, PF5020, and PF5024 PMICs have wide input voltage range from 4.0 V to
5.5 V in this application.
PF82 contains seven high efficiency buck converters and four linear regulators with
load switch options. PF5024 contains four buck converters and PF5020 contains three
buck converters and one linear regulator. PF52 is the primary core power supply and it
contains two high-power buck converters. Each buck converter of PF82, PF5020, and
PF5024 rates up to 2.5 A and linear regulator rates up to 400 mA. Each buck converter
of PF52 rates up to 8 A. Two buck converters configured to dual-phase can supply 16 A
continuous output current. PF82, PF5020, PF5024, and PF52 buck converters support
dynamic voltage scaling (DVS).
PF52 is configured to dual-phase output to supply the full power for the R-Car H3
dynamic voltage and frequency scaling (DVFS) core power. PF5024 is configured to two
dual-phase outputs to supply DDR_1.1V power for R-Car H3. BUCK1 to BUCK4 of PF82
are configured to a quad-phase to provide VDD_0.8V of the R-Car H3 processor. BUCK5
to BUCK7 of PF82 and low dropouts (LDOs) and PF5020 supply power for double data
rate (DDR) I/O, Ethernet, SD card, and other peripherals. Table 1 shows R-Car H3 power
rails requirements and PMIC output configuration.
Table 1. PMIC configuration

Item Power rail Voltage Current Power Power-up Power-up Power-down Power-down
[1]
(V) requirement configuration order delay (ms) order delay (ms)
(mA)
1 VDD_0.8V 0.825 8000 PF82 BUCK1 to 2 1 5 30.5
BUCK4
2 D_1.8V 1.8 3000 PF5020 BUCK1 5 2.5 3 10.5
and BUCK2
3 DDR0_1.8V 1.8 250 PF82 BUCK5 1 0.5 6 40.5
4 DDR1_1.8V 1.8 250 PF82 BUCK6 1 0.5 6 40.5
5 VLDO_2.5V 2.5 300 PF5020 LDO 5 2.5 3 10.5
6 DDR0_1.1V 1.1 4000 PF5024 BUCK1 6 3 2 0.5
and BUCK2
7 DDR1_1.1V 1.1 4000 PF5024 BUCK3 6 3 2 0.5
and BUCK4
[2]
8 DVFS 0.9 16000 PF52 BUCK1 3 1.5 5 30.5
and BUCK2
9 D1_3.3V 3.3 1000 PF82 BUCK7 4 2 4 20.5
10 D2_3.3V 3.3 2000 PF5020 BUCK3 4 2 4 20.5
11 VLDO_SD0 3.3 170 PF82 LDO1 7 3.5 2 0.5
12 VLDO_SD1 3.3 170 PF82 LDO3 7 3.5 2 0.5
nRESET - - RESETBMCU 8 13.5 1 0
[1] The power-up sequence is configured in the OTP and controlled by PMIC itself. No external controller is needed.
[2] The maximum load current of DVFS power rail depends on the application. The maximum value does not exceed 16 A.

5 / 17
NXP Semiconductors
AN13003
The default sequence slots for PMICs are programmed via the OTP configuration
registers. The sequence slot includes timebase and time slot to realize flexibly power-up
sequence and power-down sequence configuration. There are 255 sequence time slots
for each regulator, PGOOD, RESETBMCU can be set from 0 to 254. Time base has
four options: 30 μs, 120 μs, 250 μs, and 500 μs. XFAILB is a bidirectional pin with an
open-drain output used to synchronize the power-up sequence and the power-down
sequence of multiple PMICs. XFAILB pins of all PMICs are connected together for
NXP multi-PMIC power solution. Figure 2 and Figure 3 show the R-Car H3 power-up
sequence and power-down sequence.
PWRON
XFAILB
PF82 BUCK5 DDR0_1V8
PF82 BUCK6 DDR1_1V8

500 µs
PF82 BUCK1 to BUCK4 VDD_0V8
500 µs
PF82 BUCK1 and BUCK2 DVFS_0V8
500 µs
PF82 BUCK7 D1_3V3
PF5020 BUCK3 D2_3V3

500 µs
PF5020 LDO VLDO_2V5
PF82 BUCK1 and BUCK2 D_1V8

500 µs
PF5024 BUCK1 and BUCK2 DDR0_1V1

500 µs
PF82 LDO1 VLDO_SD0
PF82 LDO3 VLDO_SD3

10 ms
RESETBMCU
aaa-039793
Figure 2. Renesas R-Car H3 power-up sequence

6 / 17
NXP Semiconductors
AN13003
PWRON
XFAILB
PF82 BUCK5 DDR0_1V8
PF82 BUCK6 DDR1_1V8

10 ms
PF82 BUCK1 to BUCK4 VDD_0V8
PF82 BUCK1 and BUCK2 DVFS_0V8

10 ms
PF82 BUCK7 D1_3V3
PF5020 BUCK3 D2_3V3

10 ms
PF5020 LDO VLDO_2V5
PF82 BUCK1 and BUCK2 D_1V8

10 ms
PF82 LDO1 VLDO_SD0
PF82 LDO3 VLDO_SD3 500 µs
RESETBMCU
aaa-039794
Figure 3. Renesas R-Car H3 power-down sequence
4 Functional safety
PF82, PF5020, PF5024, and PF52 devices are embedded safety mechanisms and these
PMICs meet ISO 26262 standard and up to ASIL B functional safety level. The safety
mechanism includes the following functional safety features:
• Independent voltage monitoring and fault detection: PMICs feature independent
fault monitoring function per regulator. PMIC fault monitor block can monitor
undervoltage (UV), overvoltage (OV), and Ilim faults. PMIC can indicate output state per
regulator through PGOOD signal.
• Watchdog monitoring and internal watchdog counter: PF82, PF5020, PF5024,
and PF52 feature internal watchdog counters for monitoring R-Car H3 processor. If
the PMIC internal watchdog expiration counter reaches the maximum value, PMIC
watchdog block would trigger a reset event.
2
• I C-bus cyclic redundancy check (CRC) and write protection: The fuses are
2
loaded into the functional I C-bus registers of PMIC. The fuse circuits have CRC error
check routine which reports and protects against register loading errors on the PMIC
registers. If a register loading error is detected, the corresponding flag is asserted. The
2
I C-bus secure write mechanism protects the secure registers of PMIC from wrong
operation.
• Functional safety output (PF82 only): When a fault occurs on the PF82, PF82 can
detect the fault and reset the processor through RESETBMCU pin. It can also trigger
FSOB pin to transfer the system into safe state.

7 / 17
NXP Semiconductors
AN13003
• VIN overvoltage lockout (OVLO) function: All PMICs incorporate a VIN_OVLO circuit
which can monitor the main input supply of PMIC. PMIC monitors its input voltage and
can initiate a power-down sequence when PMIC detects a VIN_OVLO in the system.
• Analog built-in self-test (ABIST): When R-Car H3 power system turns on, the PMICs
routinely implement an ABIST process of all output voltage monitors before starting
power-up sequence. ABIST is for checking state of the voltage monitoring block
(OV/UV) of per regulator whether normal or not. If a failure on the OV/UV monitor is
detected during the ABIST, the PMIC asserts the corresponding ABIST flags.
Figure 4 shows the functional safety-related signal configuration in the R-Car H3 system
application.
RENESAS
PF82
R-CAR H3
POWER SUPPLY POWER
VOLTAGE MONITOR
Watchdog I2C
WD REFRESH
module
RESETBMCU RESET
PGOOD GPIO1
Safety
FSOB
state
ABIST
PF52
POWER SUPPLY POWER
VOLTAGE MONITOR
RESETBMCU
PGOOD GPIO2
ABIST
PF5020
POWER SUPPLY POWER
VOLTAGE MONITOR
RESETBMCU
PGOOD GPIO3
ABIST
PF5024
POWER SUPPLY POWER
VOLTAGE MONITOR
RESETBMCU
PGOOD GPIO4
ABIST
aaa-039795
Figure 4. Functional safety operation with Renesas R-Car H3

8 / 17
NXP Semiconductors
AN13003
5 Schematic
Figure 5 to Figure 9 show R-Car H3 power solution schematic based on NXP PMICs.
VIN_5V VDDIO
V1P5D_PF82 V1P5A_PF82
C5 C4 R5
1 µF 1 µF R9
VIN_5V 470 kΩ 100 kΩ
GND GND
V1P5A FSOB FSOB
41 29
C1 C2
V1P5D PGOOD PF82_PGOOD
0.22 µF 1 µF 40 42 PF82_PGOOD
VIN
GND GND
50 EWARN EWARN
LICELL 20 EWARN
46 PWRON
VDDOTP_PF82 VDDOTP 22 PWRON_IC
53
C13 VDDIO STANDBY PF82_STANDBY
VDDIO 23 STANDBY
GND
GND 54 RESET_MCU RESETBMCU
0.1 µF
SYNCIN PF82 21 RESETBMCU
R15
48
SCL SCL VDDIO
SCL 55 100 kΩ
GND SDA SDA INT PF82_INTB VDDIO
SDA 56 24
TBBEN_PF82_IC TBBEN
14 WDI PF82_MCU
XINTB XINTB 19 WDI R22
39 SYNCOUT 100 kΩ
GND AMUX AMUX 49
AMUX 52 PF82_INTB
51 45 57
AGND DGND EP_GND
GND aaa-039796
Figure 5. PF82 schematic for R-Car H3 power rails (control I/Os part)

9 / 17
NXP Semiconductors
AN13003
VDD_0V8 VIN_5V
R25 SW1FB_B SW1FB

3
0Ω SW1IN
C177 C178 C19 C175 C176 C21 C173 C174 C23 C171 C172 C15 4
LBK1 SW1LX_B SW1LX
22 µF 22 µF 0.1 µF 22 µF 22 µF 0.1 µF 22 µF 22 µF 0.1 µF 22 µF 22 µF 0.1 µF 1 2
5
1 µH
SW2FB
2
GND SW2IN
7
LBK2 SW2LX_B SW2LX
V1P5A_PF82 DDR0_1V8 1 2
6
1 µH
SW3FB
R28 13
SW3IN
100 kΩ C3 8
PF82_VSELECT VSELECT VSNVS C25 C26 C27
LBK3
16 47 22 µF 22 µF 0.1 µF 1 2 SW3LX_B SW3LX
PF82_LDO12_EN LDO2EN 2.2 µF 9
43 1 µH
PF82_XFAILB XFAILB SW4FB
XFAILB 44 GND 12
GND SW4IN
VIN _5V PF82 11 PF82
LDO1OUT VLDO_SD0 1
LBK4
2 SW4LX_B SW4LX
15 10
LDO12IN LDO2OUT 1 µH
17 18 R26
LDO3IN LDO3OUT VLDO_SD1 SW5FB_B SW5FB
26 25 31
LDO4IN LDO4OUT C12 0Ω SW5IN
27 28 32
4.7 µF LBK5 SW5LX_B SW5LX
1 2
33
DDR1_1V8 1 µH
C6 C7 C8 C9 C10 C11
R27 SW6FB_B SW6FB
1 µF 1 µF 1 µF 4.7 µF 4.7 µF 4.7 µF
30
0Ω SW6IN
C30 C31 C32 35
GND GND GND GND LBK6 SW6LX_B SW6LX
GND GND GND 22 µF 22 µF 0.1 µF 1 2
34
1 µH
GND R29 SW7FB_B SW7FB NC

38 1
0Ω SW7IN
37
LBK7 SW7LX_B SW7LX
D1_3V3 1 2
36
VIN_5V 1 µH
C35 C36 C37 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53
22 µF 22 µF 0.1 µF 4.7 µF 0.1 µF 4.7 µF 0.1 µF 4.7 µF 0.1 µF 4.7 µF 0.1 µF 4.7 µF 0.1 µF 4.7 µF 0.1 µF 4.7 µF 0.1 µF
GND GND aaa-039797
Figure 6. PF82 schematic for R-Car H3 power rails (LDO part and BUCK part)

10 / 17
NXP Semiconductors
AN13003
VIN_5V VDDIO
C57
0.1 µF
R34 R35
100 kΩ 100 kΩ GND
RESETBMCU
PF5020_EN1
PF5020_EN2
TBBEN_PF5020
D_1V8
WDI
VIN_5V PF5020_PGOOD4_IC
GND PF5020_PGOOD3_IC
C62 C63 C64
RESETBMCU
PWRON_IC
4.7 µF 0.1 µF 1000 pF
PGOOD4
PGOOD3
PWRON
SW1FB
TBBEN
VDDIO
GND GND GND
EPAD
WDI
EN2
EN1
41 40 39 38 37 36 35 34 33 32 31
D_1V8 SW2FB SCL
1 30 SCL
GND
LBK8 PF5020_SW1_LX SW1IN SDA
1 2 2 29 SDA
1 µH SW1LX VDDOTP
3 28
LBK9 PF5020_SW2_LX
1 2 SW2LX SYNC
1 µH
4 27
SW2IN PGOOD PF5020_PGOOD_IC
C68 C69 C70 C71 VIN_5V 5
PF5020
26
22 µF 22 µF 22 µF 22 µF SWND1IN INTB
6 25 PF5020_INTB
SWND1LX V1P5D V1P5D_PF5020
C72 C73 C75 7 24
4.7 µF 0.1 µF 1000 pF NC1 V1P5A V1P5A_PF5020
GND GND GND GND 8 23
NC2 STANDBY
VIN_5V GND GND GND 9 22 STANDBY
NC3 XFAILB
10 21 XFAILB
C74 C67
C76 C77 C78 11 12 13 14 15 16 17 18 19 20
1 µF 1 µF
4.7 µF 0.1 µF 1000 pF
LDO1OUT
SW1FB
LDO1IN
VIN
AGND
EN4
EN3
VSNV8
PGOOD1
PGOOD2
GND GND GND
D2_3V3
GND GND GND
LBK10 SWND_LX
1 2
1 µH
C80 C81
22 µF 22 µF D2_3V3
GND GND
PF5020_PGOOD1_IC
VIN_5V
VSNVS_OUT VIN_5V
R58 R57
100 kΩ 100 kΩ VLDO_2V5
C79 C84 C83 C82

PF5020_EN4
1 µF 4.7 µF 1 µF 1 µF
PF5020_EN3 GND GND GND GND aaa-039798
Figure 7. PF5020 schematic for R-Car H3 power rails

11 / 17
NXP Semiconductors
AN13003
VIN_5V VDDIO
C85
0.1 µF
R66 R67
100 kΩ 100 kΩ GND
RESETBMCU
PF5024_EN1
PF5024_EN2
TBBEN_PF5024
DDR0_1V1
WDI
VIN_5V PF5024_PGOOD4_IC
C90 C91 C92
RESETBMCU
PWRON_IC
4.7 µF 0.1 µF 1000 pF
PGOOD4
PGOOD3
PWRON
SW1FB
TBBEN
VDDIO
GND GND GND
EPAD
WDI
EN2
EN1
41 40 39 38 37 36 35 34 33 32 31
DDR0_1V1 SW2FB SCL
1 30 SCL
LBK11 PF5024_SW1_LX SW1IN SDA
1 2 2 29 SDA
1 µH SW1LX VDDOTP PF5024_VDDOTP
3 28
LBK12 PF5024_SW2_LX
1 2 SW2LX SYNC
1 µH
4 27 GND
SW2IN PGOOD PF5024_PGOOD_IC
C93 C94 C95 C96 VIN_5V 5
PF5024
26
22 µF 22 µF 22 µF 22 µF SW3IN INTB
6 25 PF5024_INTB
SW3LX V1P5D V1P5D_PF5024
C97 C98 C99 7 24
4.7 µF 0.1 µF 1000 pF SW4LX V1P5A V1P5A_PF5024
GND GND GND GND 8 23
SW4IN STANDBY
VIN_5V GND GND GND 9 22 STANDBY
SW4FB XFAILB
10 21 XFAILB
C101 C100
C105 C106 C107 11 12 13 14 15 16 17 18 19 20
1 µF 1 µF
4.7 µF 0.1 µF 1000 pF
EN4
EN3
NC5
NC6
NC7
PGOOD1
PGOOD2
SW3FB
VIN
AGND
DDR1_1V1 GND GND GND

LBK13 GND GND GND
1 2 PF5024_SW3_LX
1 µH
LBK14 PF5024_SW4_LX
1 2
1 µH
C108 C109 C110 C111 VIN_5V GND PF5024_PGOOD2_IC
22 µF 22 µF 22 µF 22 µF
PF5024_PGOOD1_IC
C102 C103 C104
4.7 µF 0.1 µF 1000 pF
GND GND GND GND
GND GND GND
VIN_5V DDR1_1V1
VIN_5V
R88 R87
100 kΩ 100 kΩ
C112 C113
PF5024_EN4
1 µF 4.7 µF
PF5024_EN3 GND GND aaa-039799
Figure 8. PF5024 schematic for R-Car H3 two DDR power rails

12 / 17
NXP Semiconductors
AN13003
VIN_5V
C194 C192
10 µF 10 µF DVFS_0V8
C193 C191
SW1IN SW1LX SW1LX 1 L1 2
10 µF 10 µF 6 1
0.47 µH
SW2IN
21 SW2LX SW2LX 1 L2 2 C184 C186 C188 C190
DVFS_DV8 24 22 µF 22 µF 22 µF 22 µF
0.47 µH
SW1FB C183 C185 C187 C189
GND 6 PGOOD PF5200_PGOOD 22 µF
SW2FB 22 µF 22 µF 22 µF
7
21
RESETMCU
VIN_5V 8 RESETBMCU
TBBEN GND GND GND GND GND GND GND GND
TBBEN_PF5200 11 XFAILB
VIN 6 XFAILB
12 PF52
PWRON
14 PWRON_IC
C195
1 µF SDA SYNC SYNC
SCL 17 13
SCL
SDA 18
GND
V1P5D V1P5D
10
VDDIO VDDIO
SWGND 15
27
NC VDDOTP PF5200_VDDOTP
23 19
C179 C180
6 20 1 µF 1 µF
GND AGND_1 AGND_2
GND GND GND GND aaa-039800
Figure 9. PF52 schematic for R-Car H3 VCORE power rails

13 / 17
NXP Semiconductors
AN13003
6 Bill of materials
Table 2 provides a list of the recommended components on R-Car H3 power solution
with NXP PMICs. The components are provided with an example part number, equivalent
components may be used.
Table 2. BOM
Value Quantity Part number Description Vendor Function
n/a 1 PF82 power management IC NXP PMIC
0.22 μF 1 GRT155C81E224KE01 25 V, ±10 %, X6S, 0402 Murata output capacitor
1.0 μF 17 GCM155C71A105KE38D 10 V, ±10 %, X7S, 0402 Murata input capacitor
2.2 μF 1 GRT155C71A225KE13 10 V, ±10 %, X7S, 0402 Murata output capacitor
4.7 μF 20 GRT188C81E475KE13 25 V, ±10 %, X6S, 0603 Murata output capacitor
0.1 μF 24 GCM155R71C104KA55D 16 V, ±10 %, X7R, 0402 Murata input and output capacitor
22 μF 36 GRT21BC81A226ME13 10 V, ±20 %, X6S, 0805 Murata output capacitor
1 nF 7 GCM155R71H102KA37D 50 V, ±10 %, X7R, 0402 Murata input capacitor
10 μF 4 CGA4J1X7R0J106K125AC 6.3 V, ±10 %, X7R, 0805 TDK input capacitor
1.0 μH 14 TFM252012ALMA1R0MTAA 4.7 A, ±20 %, SMD TDK output inductor
0.47 μH 2 VCHA042A-R47MS6 10.6 A, ±20 %, SMD CYNTEC output inductor
7 References
[1] PF5020 product summary page http://www.nxp.com/PF5020
[2] PF5024 product summary page http://www.nxp.com/PF5024
[3] PF52; contact your sales representative or FAE
[4] PF81_PF82 product summary page http://www.nxp.com/PF8100-PF8200
[5] Power management http://www.nxp.com/POWER
[6] Power management community https://community.nxp.com/community/Power-Management

14 / 17
NXP Semiconductors
AN13003
8 Legal information
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
8.1 Definitions customer’s third party customer(s). NXP does not accept any liability in this
respect.
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result Export control — This document as well as the item(s) described herein
in modifications or additions. NXP Semiconductors does not give any may be subject to export control regulations. Export might require a prior
representations or warranties as to the accuracy or completeness of authorization from competent authorities.
information included in a draft version of a document and shall have no
liability for the consequences of use of such information. Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
8.2 Disclaimers Security — Customer understands that all NXP products may be subject
to unidentified or documented vulnerabilities. Customer is responsible
for the design and operation of its applications and products throughout
Limited warranty and liability — Information in this document is believed
their lifecycles to reduce the effect of these vulnerabilities on customer’s
to be accurate and reliable. However, NXP Semiconductors does not
applications and products. Customer’s responsibility also extends to other
give any representations or warranties, expressed or implied, as to the
open and/or proprietary technologies supported by NXP products for use
accuracy or completeness of such information and shall have no liability
in customer’s applications. NXP accepts no liability for any vulnerability.
for the consequences of use of such information. NXP Semiconductors
Customer should regularly check security updates from NXP and follow up
takes no responsibility for the content in this document if provided by an
appropriately. Customer shall select products with security features that best
information source outside of NXP Semiconductors. In no event shall NXP
meet rules, regulations, and standards of the intended application and make
Semiconductors be liable for any indirect, incidental, punitive, special or
the ultimate design decisions regarding its products and is solely responsible
consequential damages (including - without limitation - lost profits, lost
for compliance with all legal, regulatory, and security related requirements
savings, business interruption, costs related to the removal or replacement
concerning its products, regardless of any information or support that may
of any products or rework charges) whether or not such damages are based
be provided by NXP. NXP has a Product Security Incident Response Team
on tort (including negligence), warranty, breach of contract or any other
(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,
legal theory. Notwithstanding any damages that customer might incur for
reporting, and solution release to security vulnerabilities of NXP products.
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP Suitability for use in automotive applications — This NXP product has
Semiconductors. been qualified for use in automotive applications. It has been developed in
accordance with ISO 26262, and has been ASIL-classified accordingly. If
this product is used by customer in the development of, or for incorporation
Right to make changes — NXP Semiconductors reserves the right to
into, products or services (a) used in safety critical applications or (b) in
make changes to information published in this document, including without
which failure could lead to death, personal injury, or severe physical or
limitation specifications and product descriptions, at any time and without
environmental damage (such products and services hereinafter referred
notice. This document supersedes and replaces all information supplied prior
to as “Critical Applications”), then customer makes the ultimate design
to the publication hereof.
decisions regarding its products and is solely responsible for compliance with
all legal, regulatory, safety, and security related requirements concerning
Applications — Applications that are described herein for any of these
its products, regardless of any information or support that may be provided
products are for illustrative purposes only. NXP Semiconductors makes
by NXP. As such, customer assumes all risk related to use of any products
no representation or warranty that such applications will be suitable
in Critical Applications and NXP and its suppliers shall not be liable for
for the specified use without further testing or modification. Customers
any such use by customer. Accordingly, customer will indemnify and hold
are responsible for the design and operation of their applications and
NXP harmless from any claims, liabilities, damages and associated costs
products using NXP Semiconductors products, and NXP Semiconductors
and expenses (including attorneys’ fees) that NXP may incur related to
accepts no liability for any assistance with applications or customer product
customer’s incorporation of any product in a Critical Application.
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with 8.3 Trademarks
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based Notice: All referenced brands, product names, service names and
on any weakness or default in the customer’s applications or products, or trademarks are the property of their respective owners.
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications NXP — wordmark and logo are trademarks of NXP B.V.

15 / 17
NXP Semiconductors
AN13003
Tables
Tab. 1. PMIC configuration ............................................5 Tab. 2. BOM ................................................................ 14
Figures
Fig. 1. NXP power solution for Renesas R-Car H3 ...... 4 Fig. 6. PF82 schematic for R-Car H3 power rails
Fig. 2. Renesas R-Car H3 power-up sequence ............6 (LDO part and BUCK part) ..............................10
Fig. 3. Renesas R-Car H3 power-down sequence ....... 7 Fig. 7. PF5020 schematic for R-Car H3 power
Fig. 4. Functional safety operation with Renesas rails .................................................................. 11
R-Car H3 ........................................................... 8 Fig. 8. PF5024 schematic for R-Car H3 two DDR
Fig. 5. PF82 schematic for R-Car H3 power rails power rails .......................................................12
(control I/Os part) .............................................. 9 Fig. 9. PF52 schematic for R-Car H3 VCORE
power rails .......................................................13

16 / 17
NXP Semiconductors
AN13003
Contents
1 Introduction ......................................................... 3
2 Description ...........................................................3
3 Power solution .................................................... 5
4 Functional safety .................................................7
5 Schematic ............................................................ 9
6 Bill of materials ................................................. 14
7 References ......................................................... 14
8 Legal information .............................................. 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2020. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 December 2020
Document identifier: AN13003

NXP PMIC Solution For Renesas R-Car H3 Processor: Rev. 1 - 9 December 2020 Application Note

Uploaded by

Copyright:

Available Formats

You might also like

NXP PMIC Solution For Renesas R-Car H3 Processor: Rev. 1 - 9 December 2020 Application Note

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

NXP PMIC Solution For Renesas R-Car H3 Processor: Rev. 1 - 9 December 2020 Application Note

Uploaded by

Copyright:

Available Formats

AN13003

NXP PMIC solution for Renesas R-Car H3 processor

Application note Rev. 1 — 9 December 2020

Application note Rev. 1 — 9 December 2020

Figure 1. NXP power solution for Renesas R-Car H3

Application note Rev. 1 — 9 December 2020

Table 1. PMIC configuration

Application note Rev. 1 — 9 December 2020

PF82 BUCK5 DDR0_1V8

PF82 BUCK6 DDR1_1V8

PF5020 BUCK3 D2_3V3

PF82 BUCK1 and BUCK2 D_1V8

PF5024 BUCK3 and BUCK4 DDR1_1V1

PF82 LDO3 VLDO_SD3

Figure 2. Renesas R-Car H3 power-up sequence

Application note Rev. 1 — 9 December 2020

PF82 BUCK5 DDR0_1V8

PF82 BUCK6 DDR1_1V8

PF82 BUCK1 to BUCK4 VDD_0V8

PF82 BUCK1 and BUCK2 DVFS_0V8

PF5020 BUCK3 D2_3V3

PF82 BUCK1 and BUCK2 D_1V8

PF5024 BUCK3 and BUCK4 DDR1_1V1

PF82 LDO1 VLDO_SD0

PF82 LDO3 VLDO_SD3 500 µs

Figure 3. Renesas R-Car H3 power-down sequence

Application note Rev. 1 — 9 December 2020

Figure 4. Functional safety operation with Renesas R-Car H3

Application note Rev. 1 — 9 December 2020

Application note Rev. 1 — 9 December 2020

R25 SW1FB_B SW1FB

GND R29 SW7FB_B SW7FB NC

GND GND aaa-039797

Application note Rev. 1 — 9 December 2020

C79 C84 C83 C82

PF5020_EN3 GND GND GND GND aaa-039798

Figure 7. PF5020 schematic for R-Car H3 power rails

Application note Rev. 1 — 9 December 2020

DDR1_1V1 GND GND GND

PF5024_EN3 GND GND aaa-039799

Figure 8. PF5024 schematic for R-Car H3 two DDR power rails

Application note Rev. 1 — 9 December 2020

GND GND GND GND aaa-039800

Figure 9. PF52 schematic for R-Car H3 VCORE power rails

Application note Rev. 1 — 9 December 2020

Application note Rev. 1 — 9 December 2020

Application note Rev. 1 — 9 December 2020

Application note Rev. 1 — 9 December 2020

© NXP B.V. 2020. All rights reserved.

You might also like